0-In Design Automation
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0-In Design Automation Employees
Employee
Years
Job
Industry
Neil Hand Neil Hand's 0-In Design Automation Experience October 2002 - September 2004
Job Principal at Trilobe, Inc.
Industry Semiconductors
Experience
Trilobe, Inc. October 2012 - Present
Codasip January 2014 - Present
Methodics May 2013 - March 2015
Cadence Design Systems September 2006 - October 2012
Mentor Graphics September 2004 - September 2006
0-In Design Automation October 2002 - September 2004
Averant 2000 - 2002
Get2Chip 1998 - 2000
Synopsys August 1996 - January 1998
Ericsson 1991 - 1996
Skills
Product Marketing, Product Management, Messaging, Market Analysis, Competitive Analysis, Go-to-market Strategy, Product Launch, Cross-functional Team..., Product Development, Start-ups, Business Strategy, Enterprise Software, Semiconductors, SoC, ASIC, EDA, SaaS, System Design, Semiconductor Device, IC, Strategic Partnerships, Positioning, Mergers & Acquisitions, Business Development, Business Planning, Outbound Marketing, Requirements Gathering, Product Lifecycle..., Systems Design, Sales Strategy, Presentations, IP, Web Development, Integration, Demand Generation, Consulting, Partner Management, Business Alliances, Sales Operations, Firmware, Marketing Strategy, Embedded Systems
Education
Queensland University of Technology 1986 — 1990
Bachelor of Engineering, Electronics and Communications
Queensland University of Technology 1986 — 1990
Bachelor Applied Science, Computing
Trilobe, Inc. October 2012 - Present
Codasip January 2014 - Present
Methodics May 2013 - March 2015
Cadence Design Systems September 2006 - October 2012
Mentor Graphics September 2004 - September 2006
0-In Design Automation October 2002 - September 2004
Averant 2000 - 2002
Get2Chip 1998 - 2000
Synopsys August 1996 - January 1998
Ericsson 1991 - 1996
Skills
Product Marketing, Product Management, Messaging, Market Analysis, Competitive Analysis, Go-to-market Strategy, Product Launch, Cross-functional Team..., Product Development, Start-ups, Business Strategy, Enterprise Software, Semiconductors, SoC, ASIC, EDA, SaaS, System Design, Semiconductor Device, IC, Strategic Partnerships, Positioning, Mergers & Acquisitions, Business Development, Business Planning, Outbound Marketing, Requirements Gathering, Product Lifecycle..., Systems Design, Sales Strategy, Presentations, IP, Web Development, Integration, Demand Generation, Consulting, Partner Management, Business Alliances, Sales Operations, Firmware, Marketing Strategy, Embedded Systems
Education
Queensland University of Technology 1986 — 1990
Bachelor of Engineering, Electronics and Communications
Queensland University of Technology 1986 — 1990
Bachelor Applied Science, Computing
Seyul Choe Seyul Choe's 0-In Design Automation Experience January 2002 - February 2004
Job Former VP of Asia Pacific at CoWare, Inc.
Industry Computer Software
Experience
CoWare, Inc. January 2005 - March 2010
CoWare, Inc January 2005 - March 2010
0-In Design Automation (acquired by Mentor Graphics) 2002 - 2005
0-In Design Automation January 2002 - February 2004
Education
San Jose State University 1980 — 1986
BS, Computer Engineering
CoWare, Inc. January 2005 - March 2010
CoWare, Inc January 2005 - March 2010
0-In Design Automation (acquired by Mentor Graphics) 2002 - 2005
0-In Design Automation January 2002 - February 2004
Education
San Jose State University 1980 — 1986
BS, Computer Engineering
Jenson Ho Jenson Ho's 0-In Design Automation Experience September 2000 - September 2004
Job Engineering Manager, IT expert
Industry Computer Software
Experience
Mentor Graphics May 2011 - Present
NVIDIA November 2010 - May 2011
Mentor Graphics September 2004 - October 2010
0-In Design Automation September 2000 - September 2004
eGain Communications January 2000 - September 2000
IBM June 1998 - September 1999
University of Texas at Austin April 1997 - June 1998
University of Texas at Austin December 1995 - April 1997
Skills
Linux, Windows, Mac OS X, Software Engineering, Continuous Integration, Build Automation, Solaris, Puppet, Perl, Shell Scripting, Python, VMware Server, Apache, Operating Systems, Unix, Integration, Web Services, Android, Testing, Test Automation, Servers, Bash
Education
Santa Clara University 2005 — 2009
Master of Business Administration (M.B.A.), Leading People & Organizations, Managing People & Technology, Entrepreneurship
The University of Texas at Austin 1995 — 1999
B.Sc, Electrical and Computer Engineering
Mentor Graphics May 2011 - Present
NVIDIA November 2010 - May 2011
Mentor Graphics September 2004 - October 2010
0-In Design Automation September 2000 - September 2004
eGain Communications January 2000 - September 2000
IBM June 1998 - September 1999
University of Texas at Austin April 1997 - June 1998
University of Texas at Austin December 1995 - April 1997
Skills
Linux, Windows, Mac OS X, Software Engineering, Continuous Integration, Build Automation, Solaris, Puppet, Perl, Shell Scripting, Python, VMware Server, Apache, Operating Systems, Unix, Integration, Web Services, Android, Testing, Test Automation, Servers, Bash
Education
Santa Clara University 2005 — 2009
Master of Business Administration (M.B.A.), Leading People & Organizations, Managing People & Technology, Entrepreneurship
The University of Texas at Austin 1995 — 1999
B.Sc, Electrical and Computer Engineering
Dong Wang Dong Wang's 0-In Design Automation Experience May 2003 - August 2004
Job Software Engineer at Databricks
Industry Computer Software
Experience
Databricks June 2014 - Present
Twitter November 2009 - June 2014
Yahoo! June 2008 - October 2009
Synopsys September 2004 - May 2008
0-In Design Automation May 2003 - August 2004
Carnegie Mellon University 1998 - 2003
Skills
Hadoop, Distributed Systems, Scalability, MapReduce, Algorithms, Python, Machine Learning, Java, Software Engineering, Ruby, C++, Big Data, Open Source, Analytics, Apache Pig
Education
Carnegie Mellon University 1999 — 2003
Ph.D., ECE
Carnegie Mellon University 1998 — 1999
M.S., ECE
Beijing Institute of Technology 1991 — 1995
B.S., CSE
Databricks June 2014 - Present
Twitter November 2009 - June 2014
Yahoo! June 2008 - October 2009
Synopsys September 2004 - May 2008
0-In Design Automation May 2003 - August 2004
Carnegie Mellon University 1998 - 2003
Skills
Hadoop, Distributed Systems, Scalability, MapReduce, Algorithms, Python, Machine Learning, Java, Software Engineering, Ruby, C++, Big Data, Open Source, Analytics, Apache Pig
Education
Carnegie Mellon University 1999 — 2003
Ph.D., ECE
Carnegie Mellon University 1998 — 1999
M.S., ECE
Beijing Institute of Technology 1991 — 1995
B.S., CSE
Jean-Charles Giomi Jean-Charles Giomi's 0-In Design Automation Experience September 1996 - September 2000
Job Vice President, R&D at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems April 2009 - Present
Cadence Design Systems, Inc. April 2005 - April 2009
Cadence Design Systems, Inc. April 2003 - April 2005
Get2Chip.com, Inc. September 2000 - April 2003
0-In Design Automation September 1996 - September 2000
Compass Design Automation January 1992 - September 1996
Education
Stanford University 1991 — 1992
Visiting Scholar, Electrical Engineering
Institut polytechnique de Grenoble 1985 — 1991
M.S., Electrical Engineering
Ecole Nationale Supérieure d'Informatique et de Mathématiques Appliquées de Grenoble 1987 — 1990
B.S., Computer Science
Cadence Design Systems April 2009 - Present
Cadence Design Systems, Inc. April 2005 - April 2009
Cadence Design Systems, Inc. April 2003 - April 2005
Get2Chip.com, Inc. September 2000 - April 2003
0-In Design Automation September 1996 - September 2000
Compass Design Automation January 1992 - September 1996
Education
Stanford University 1991 — 1992
Visiting Scholar, Electrical Engineering
Institut polytechnique de Grenoble 1985 — 1991
M.S., Electrical Engineering
Ecole Nationale Supérieure d'Informatique et de Mathématiques Appliquées de Grenoble 1987 — 1990
B.S., Computer Science
Andrew Seawright Andrew Seawright's 0-In Design Automation Experience 2002 - 2004
Job Principal Engineer Mentor Graphics
Industry Computer Software
Experience
Mentor Graphics January 2002 - Present
0-In Design Automation 2002 - 2004
Clearwater Networks January 2001 - December 2001
Chameleon Systems, Inc. January 1999 - December 2000
Synopsys, Inc. July 1993 - January 1999
Skills
EDA, Verilog, Logic Synthesis, RTL design, Formal Verification, SystemVerilog, ASIC, Functional Verification, Compilers, R&D, Semiconductors, Debugging, TCL, FPGA, VHDL, VLSI, Computer Architecture, Static Timing Analysis, SoC, RTL Design
Education
University of California, Santa Barbara 1989 — 1995
Ph.D., Electrical and Computer Engineering
Rutgers University-New Brunswick 1985 — 1989
BSEE, Electrical Engineering
Bronx High School of Science 1981 — 1985
Mentor Graphics January 2002 - Present
0-In Design Automation 2002 - 2004
Clearwater Networks January 2001 - December 2001
Chameleon Systems, Inc. January 1999 - December 2000
Synopsys, Inc. July 1993 - January 1999
Skills
EDA, Verilog, Logic Synthesis, RTL design, Formal Verification, SystemVerilog, ASIC, Functional Verification, Compilers, R&D, Semiconductors, Debugging, TCL, FPGA, VHDL, VLSI, Computer Architecture, Static Timing Analysis, SoC, RTL Design
Education
University of California, Santa Barbara 1989 — 1995
Ph.D., Electrical and Computer Engineering
Rutgers University-New Brunswick 1985 — 1989
BSEE, Electrical Engineering
Bronx High School of Science 1981 — 1985
Richard Ho's 0-In Design Automation Experience July 1996 - September 2004
Job Hardware Googler
Industry Semiconductors
Experience
Google February 2014 - Present
Calxeda, Inc. May 2013 - January 2014
D. E. Shaw Research September 2005 - April 2013
Accellera June 2008 - October 2012
Mentor Graphics September 2004 - September 2005
0-In Design Automation July 1996 - September 2004
Skills
Formal Verification, SystemVerilog, Verilog, C, EDA, Python, Computer Science, ASIC, Functional Verification, High Performance..., Algorithms, Debugging, Simulations, SoC, ARM, Computer Architecture, Xilinx, TCL, RTL design, Processors, VLSI, Microprocessors, Perl, RTL Design
Education
Stanford University 1990 — 1996
Ph.D, Computer Science
UCLA Anderson School of Management Extension
Technical Management Program
The University of Manchester 1986 — 1990
M.Eng, B.Sc (Hons), Microelectronic Systems Engineering
Google February 2014 - Present
Calxeda, Inc. May 2013 - January 2014
D. E. Shaw Research September 2005 - April 2013
Accellera June 2008 - October 2012
Mentor Graphics September 2004 - September 2005
0-In Design Automation July 1996 - September 2004
Skills
Formal Verification, SystemVerilog, Verilog, C, EDA, Python, Computer Science, ASIC, Functional Verification, High Performance..., Algorithms, Debugging, Simulations, SoC, ARM, Computer Architecture, Xilinx, TCL, RTL design, Processors, VLSI, Microprocessors, Perl, RTL Design
Education
Stanford University 1990 — 1996
Ph.D, Computer Science
UCLA Anderson School of Management Extension
Technical Management Program
The University of Manchester 1986 — 1990
M.Eng, B.Sc (Hons), Microelectronic Systems Engineering
David Landoll's 0-In Design Automation Experience September 1997 - January 2005
Job Solutions Architect at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems March 2015 - Present
Synopsys September 2013 - February 2015
Mentor Graphics January 2005 - September 2013
0-In Design Automation September 1997 - January 2005
Synopsys October 1995 - September 1997
Synopsys 1992 - 1995
Amdahl Corp. 1990 - 1992
Honeywell Bull 1989 - 1990
Hewlett-Packard 1988 - 1988
Skills
ASIC, Debugging, Embedded Systems, Simulations, Verilog, SystemVerilog, EDA, Assertion Based..., Static Timing Analysis, TCL, Formal Verification, Functional Verification, Logic Synthesis, RTL verification, SoC, Integrated Circuit..., VHDL, Testing, RTL design, Semiconductors, SystemC, ARM, Computer Architecture, Microprocessors, Hardware Architecture, RTL Design
Education
Santa Clara University 1994 — 1998
MBA, Buniness
University of Arizona 1986 — 1989
BSEE, Engineering
New Mexico Institute of Mining and Technology 1984 — 1986
2 years toward BS, Computer Science
Cadence Design Systems March 2015 - Present
Synopsys September 2013 - February 2015
Mentor Graphics January 2005 - September 2013
0-In Design Automation September 1997 - January 2005
Synopsys October 1995 - September 1997
Synopsys 1992 - 1995
Amdahl Corp. 1990 - 1992
Honeywell Bull 1989 - 1990
Hewlett-Packard 1988 - 1988
Skills
ASIC, Debugging, Embedded Systems, Simulations, Verilog, SystemVerilog, EDA, Assertion Based..., Static Timing Analysis, TCL, Formal Verification, Functional Verification, Logic Synthesis, RTL verification, SoC, Integrated Circuit..., VHDL, Testing, RTL design, Semiconductors, SystemC, ARM, Computer Architecture, Microprocessors, Hardware Architecture, RTL Design
Education
Santa Clara University 1994 — 1998
MBA, Buniness
University of Arizona 1986 — 1989
BSEE, Engineering
New Mexico Institute of Mining and Technology 1984 — 1986
2 years toward BS, Computer Science
David Dill's 0-In Design Automation Experience 1996 - 1997
Job Professor of Computer Science, Stanford University
Industry Computer Software
Experience
Stanford University September 1987 - Present
0-In Design Automation 1996 - 1997
Skills
Formal Verification, Computational biology, Voting Technology
Education
Carnegie Mellon University
PhD, Computer Science
Massachusetts Institute of Technology 1975 — 1979
6-3, Computer Science
Stanford University September 1987 - Present
0-In Design Automation 1996 - 1997
Skills
Formal Verification, Computational biology, Voting Technology
Education
Carnegie Mellon University
PhD, Computer Science
Massachusetts Institute of Technology 1975 — 1979
6-3, Computer Science
Jason Niatas's 0-In Design Automation Experience 2002 - 2004
Job Product Solutions Sales Manager at Synopsys
Industry Computer Software
Experience
Synopsys January 2010 - Present
VaST Systems November 2006 - January 2010
VaST Systems Technology 2006 - January 2010
Cadence Design Systems, Inc. 2004 - 2006
Verisity 2004 - 2005
0-In Design Automation 2002 - 2004
Cadence Design Systems 2000 - 2002
Synopsys, Incorporated 1994 - 2000
LSI Logic 1989 - 1994
Skills
EDA, Semiconductors, ASIC, Enterprise Software, Solution Selling, SoC, Product Marketing, Strategic Partnerships, Start-ups, Product Management, Sales, Product Launch, Salesforce.com, IC, Management, Verilog, Business Development, Processors
Education
Rutgers, The State University of New Jersey-New Brunswick 1981 — 1985
BS, Electrical Engineering
Trenton Central High School 1978 — 1981
Synopsys January 2010 - Present
VaST Systems November 2006 - January 2010
VaST Systems Technology 2006 - January 2010
Cadence Design Systems, Inc. 2004 - 2006
Verisity 2004 - 2005
0-In Design Automation 2002 - 2004
Cadence Design Systems 2000 - 2002
Synopsys, Incorporated 1994 - 2000
LSI Logic 1989 - 1994
Skills
EDA, Semiconductors, ASIC, Enterprise Software, Solution Selling, SoC, Product Marketing, Strategic Partnerships, Start-ups, Product Management, Sales, Product Launch, Salesforce.com, IC, Management, Verilog, Business Development, Processors
Education
Rutgers, The State University of New Jersey-New Brunswick 1981 — 1985
BS, Electrical Engineering
Trenton Central High School 1978 — 1981
Priya Viswanathan's 0-In Design Automation Experience April 2003 - September 2004
Job Staff Engineer at Mentor Graphics
Industry Computer Software
Experience
Mentor Graphics September 2004 - Present
0-In Design Automation April 2003 - September 2004
Synopsys July 1999 - October 2003
Skills
Assertion Based..., Clock Domain Crossing..., C, RTL synthesis, EDA, HDLs -..., EDA software development, C++, Logic Synthesis, SystemVerilog, VHDL, Verilog, ASIC, Debugging, SoC, Formal Verification, TCL, Perl, Algorithms, RTL Design
Education
San Jose State University 2003 — 2005
MS
Bengal Engineering and Science University, Shibpur 1995 — 1999
BE
Assembly of God Church School 1990 — 1995
High School
Mentor Graphics September 2004 - Present
0-In Design Automation April 2003 - September 2004
Synopsys July 1999 - October 2003
Skills
Assertion Based..., Clock Domain Crossing..., C, RTL synthesis, EDA, HDLs -..., EDA software development, C++, Logic Synthesis, SystemVerilog, VHDL, Verilog, ASIC, Debugging, SoC, Formal Verification, TCL, Perl, Algorithms, RTL Design
Education
San Jose State University 2003 — 2005
MS
Bengal Engineering and Science University, Shibpur 1995 — 1999
BE
Assembly of God Church School 1990 — 1995
High School