Atoptech Company
Industry: Company
DescriptionFounded: 2004 Parent organization: Avatar Integrated Systems, Inc.
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Atoptech Employees
Employee
Years
Job
Industry
Cole Noppenberg Cole Noppenberg's Atoptech Experience October 2013 - Present
Job Director at Black Star Coop Pub and Brewery
Industry Computer Software
Experience
Black Star Co-op Pub and Brewery November 2014 - Present
Atoptech October 2013 - Present
Qualcomm 2012 - Present
MDA Analytics 2010 - 2010
S3 Matching Technologies 2009 - 2009
Texas Instruments 2005 - 2009
Skills
Timing Closure, Primetime, Debugging, Low-power Design, Floorplanning, Physical Design, Linux, ASIC, IC, Static Timing Analysis, VLSI, Logic Synthesis, Microprocessors
Education
Texas Tech University
MSEE
University of Florida
BS, Computer and Electrical Engineering
Black Star Co-op Pub and Brewery November 2014 - Present
Atoptech October 2013 - Present
Qualcomm 2012 - Present
MDA Analytics 2010 - 2010
S3 Matching Technologies 2009 - 2009
Texas Instruments 2005 - 2009
Skills
Timing Closure, Primetime, Debugging, Low-power Design, Floorplanning, Physical Design, Linux, ASIC, IC, Static Timing Analysis, VLSI, Logic Synthesis, Microprocessors
Education
Texas Tech University
MSEE
University of Florida
BS, Computer and Electrical Engineering
Sunil Thattarakkal Sunil Thattarakkal's Atoptech Experience March 2010 - April 2014
Job Application Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems May 2014 - Present
Atoptech March 2010 - April 2014
Symmid Semiconductor Technology October 2006 - May 2009
Information Technology Program, USC October 2004 - February 2006
I2 Technologies June 2003 - January 2004
Skills
Place & Route, Timing Closure, Floorplanning, Static Timing Analysis, Verilog, Physical Design, EDA, Primetime, ASIC, SoC, Logic Synthesis, LVS, DRC, Clock Tree Synthesis, Formal Verification, RTL coding, Timing, Cadence
Education
University of Southern California 2004 — 2005
MS, Electrical Engineering (VLSI Design)
National Institute of Technology Calicut 1998 — 2002
B.Tech, Electrical & Electronics Engineering
Cadence Design Systems May 2014 - Present
Atoptech March 2010 - April 2014
Symmid Semiconductor Technology October 2006 - May 2009
Information Technology Program, USC October 2004 - February 2006
I2 Technologies June 2003 - January 2004
Skills
Place & Route, Timing Closure, Floorplanning, Static Timing Analysis, Verilog, Physical Design, EDA, Primetime, ASIC, SoC, Logic Synthesis, LVS, DRC, Clock Tree Synthesis, Formal Verification, RTL coding, Timing, Cadence
Education
University of Southern California 2004 — 2005
MS, Electrical Engineering (VLSI Design)
National Institute of Technology Calicut 1998 — 2002
B.Tech, Electrical & Electronics Engineering
Li-Feng Lin Li-Feng Lin's Atoptech Experience 2011 - Present
Job Senior R&D Engineer（Atoptech）
Industry Computer Software
Experience
Atoptech 2011 - Present
Incentia Design Systems, Inc. 2004 - 2010
Skills
Static Timing Analysis, Optimization, Multithreading, Distributed Systems
Education
國立清華大學 2002 — 2004
Department of Computer Science, Master's degree
國立臺灣師範大學 1998 — 2002
Department of Information and Computer Education, Bachelor's degree
Concordia Middle School
協同中學
Atoptech 2011 - Present
Incentia Design Systems, Inc. 2004 - 2010
Skills
Static Timing Analysis, Optimization, Multithreading, Distributed Systems
Education
國立清華大學 2002 — 2004
Department of Computer Science, Master's degree
國立臺灣師範大學 1998 — 2002
Department of Information and Computer Education, Bachelor's degree
Concordia Middle School
協同中學
Yueh-Tung (Nicole) Chao Yueh-Tung (Nicole) Chao's Atoptech Experience January 2015 - Present
Job Senior R&D Engineer at Atoptech
Industry Computer Software
Experience
Atoptech January 2015 - Present
Atoptech May 2014 - December 2014
Atoptech October 2012 - May 2014
Sonics, Inc. March 2012 - September 2012
Skills
EDA, C++, Verilog, C, Debugging, TCL, Embedded Software, ARM, Low-power Design, ASIC, Perl, Algorithms, SoC, Semiconductors, Python, FPGA, Embedded Systems, Linux, VLSI
Education
KTH Royal Institute of Technology 2011 — 2012
Exchange Student, Information and Communication Technology
National Taiwan University 2009 — 2011
Master's degree, Electronics Design Automation
National Tsing Hua University 2005 — 2009
Bachelor's degree, Computer Science
Atoptech January 2015 - Present
Atoptech May 2014 - December 2014
Atoptech October 2012 - May 2014
Sonics, Inc. March 2012 - September 2012
Skills
EDA, C++, Verilog, C, Debugging, TCL, Embedded Software, ARM, Low-power Design, ASIC, Perl, Algorithms, SoC, Semiconductors, Python, FPGA, Embedded Systems, Linux, VLSI
Education
KTH Royal Institute of Technology 2011 — 2012
Exchange Student, Information and Communication Technology
National Taiwan University 2009 — 2011
Master's degree, Electronics Design Automation
National Tsing Hua University 2005 — 2009
Bachelor's degree, Computer Science
Tien Chang Hsu Tien Chang Hsu's Atoptech Experience March 2012 - Present
Job Senior R&D Engineer
Industry Computer Software
Experience
Atoptech March 2012 - Present
Synopsys January 2007 - February 2012
Skills
C++, C, Algorithms, EDA, Software Development, VLSI, Simulations, Linux, SoC, Programming, Python
Education
National Taiwan University 2004 — 2006
Master's Degree, Electronic Design Automation
National Taiwan University 1999 — 2004
Bachelor's Degree, Department of Electrical Engineering
Atoptech March 2012 - Present
Synopsys January 2007 - February 2012
Skills
C++, C, Algorithms, EDA, Software Development, VLSI, Simulations, Linux, SoC, Programming, Python
Education
National Taiwan University 2004 — 2006
Master's Degree, Electronic Design Automation
National Taiwan University 1999 — 2004
Bachelor's Degree, Department of Electrical Engineering
Tanmay Sapkal Tanmay Sapkal's Atoptech Experience July 2013 - March 2014
Job Graduate Student at Georgia Tech
Industry Semiconductors
Experience
Georgia Institute of Technology August 2014 - Present
Georgia Institute of Technology July 2014 - Present
The-Urban-Voyager November 2013 - Present
NVIDIA May 2015 - August 2015
Atoptech July 2013 - March 2014
Click n' Cherish May 2013 - February 2014
Indian Institute of Science May 2012 - July 2013
Nuclear Power Corporation of India Ltd. May 2011 - July 2011
Skills
C, C++, Matlab, Programming, Windows, Microsoft Office, HTML, Linux, Research, Microsoft Excel, Microsoft Word, PowerPoint, EDA, VLSI, Computer Architecture, Photography, Physical Design, Low-power Design, Circuit Design, VHDL, Perl, Algorithms, Verilog, ASIC, FPGA, Embedded Systems, Unix, Xilinx, SPICE, Digital Signal..., PSpice, Data Structures
Education
Georgia Institute of Technology 2014 — 2016
Master of Science (M.S.), Electrical and Electronics Engineering, GPA : 4.0/4.0
National Institute of Technology Karnataka 2009 — 2013
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering, GPA: 4.0/4.0
Atomic Energy Central School 1996 — 2009
Higher Secondary (School) Certificate, Science, Electronics, A+
Georgia Institute of Technology August 2014 - Present
Georgia Institute of Technology July 2014 - Present
The-Urban-Voyager November 2013 - Present
NVIDIA May 2015 - August 2015
Atoptech July 2013 - March 2014
Click n' Cherish May 2013 - February 2014
Indian Institute of Science May 2012 - July 2013
Nuclear Power Corporation of India Ltd. May 2011 - July 2011
Skills
C, C++, Matlab, Programming, Windows, Microsoft Office, HTML, Linux, Research, Microsoft Excel, Microsoft Word, PowerPoint, EDA, VLSI, Computer Architecture, Photography, Physical Design, Low-power Design, Circuit Design, VHDL, Perl, Algorithms, Verilog, ASIC, FPGA, Embedded Systems, Unix, Xilinx, SPICE, Digital Signal..., PSpice, Data Structures
Education
Georgia Institute of Technology 2014 — 2016
Master of Science (M.S.), Electrical and Electronics Engineering, GPA : 4.0/4.0
National Institute of Technology Karnataka 2009 — 2013
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering, GPA: 4.0/4.0
Atomic Energy Central School 1996 — 2009
Higher Secondary (School) Certificate, Science, Electronics, A+
Deepesh Bagmar Deepesh Bagmar's Atoptech Experience March 2015 - Present
Job Applications Engineer at Atoptech
Industry Semiconductors
Experience
Atoptech March 2015 - Present
Skills
Logic Synthesis, Conformal LEC, Static Timing Analysis, Cadence Virtuoso, Perl, Logic Analyzer, LEC, Design Compiler, Formal Verification, Synopsys Primetime, Design Vision, VCS, Verilog, C, TCL, Allegro, IXIA, MATLAB, ASIC, Hardware, Debugging, ICC, Python, Floorplanning, Clock Tree Synthesis, Place and Route
Education
UCSC Silicon Valley Extension 2015 — 2015
Certificate program, VLSI Engineering, Computer Programming
San Jose State University 2009 — 2011
MS, Electrical Engineering
Anna University 2005 — 2009
B.E., Electronics and Communication Engineering
Atoptech March 2015 - Present
Skills
Logic Synthesis, Conformal LEC, Static Timing Analysis, Cadence Virtuoso, Perl, Logic Analyzer, LEC, Design Compiler, Formal Verification, Synopsys Primetime, Design Vision, VCS, Verilog, C, TCL, Allegro, IXIA, MATLAB, ASIC, Hardware, Debugging, ICC, Python, Floorplanning, Clock Tree Synthesis, Place and Route
Education
UCSC Silicon Valley Extension 2015 — 2015
Certificate program, VLSI Engineering, Computer Programming
San Jose State University 2009 — 2011
MS, Electrical Engineering
Anna University 2005 — 2009
B.E., Electronics and Communication Engineering
Giuseppe Scafidi Polino Giuseppe Scafidi Polino's Atoptech Experience March 2011 - March 2012
Job Methodology Engineer at Broadcom
Industry Computer Software
Experience
Broadcom November 2011 - Present
Atoptech March 2011 - March 2012
Synopsys May 2008 - July 2011
Synopsys November 2003 - May 2008
synopsys March 2001 - October 2003
Avant! 2000 - 2001
Avant! 1999 - 2000
STMicroelectronics 1997 - 1999
STMicroelectronics 1995 - 1997
Skills
Physical Design, TCL, EDA, SoC, Static Timing Analysis, ASIC, Place & Route, Verilog
Education
Università degli Studi di Pavia 1989 — 1995
Laurea (Master), Computer Engineer
Broadcom November 2011 - Present
Atoptech March 2011 - March 2012
Synopsys May 2008 - July 2011
Synopsys November 2003 - May 2008
synopsys March 2001 - October 2003
Avant! 2000 - 2001
Avant! 1999 - 2000
STMicroelectronics 1997 - 1999
STMicroelectronics 1995 - 1997
Skills
Physical Design, TCL, EDA, SoC, Static Timing Analysis, ASIC, Place & Route, Verilog
Education
Università degli Studi di Pavia 1989 — 1995
Laurea (Master), Computer Engineer
Mingfu Gong's Atoptech Experience April 2012 - April 2015
Job Principal Engineer at Atoptech
Industry Computer Software
Experience
ASML April 2015 - Present
Atoptech April 2012 - April 2015
Synopsys December 2011 - April 2012
Synopsys November 2009 - November 2011
Synopsys June 2008 - October 2009
Mentor Graphics February 2005 - June 2008
Tera systems October 1999 - January 2005
IBM EDA Lab. October 1996 - October 1999
Amiable Technologies June 1992 - September 1996
Tsinghua University October 1984 - September 1990
Skills
EDA, AMS Floorplanning, Routing, STA Engine, Design Methodology, Algorithms, TCL, Device Drivers, ASIC, Perl, VLSI, Floorplanning, SoC, FPGA, Static Timing Analysis, Physical Design, Debugging, Integrated Circuit..., RTL design, Low-power Design, IC
Education
Saint Joseph's University 1990 — 1992
MSCS, AI, Algorithm
Tsinghua University 1982 — 1984
MSEE, Communication systems, CAD and ASIC design
Dalian University of Technology 1978 — 1982
BSEE, Radio electronics, TV systems, RF circuits and information theory
ASML April 2015 - Present
Atoptech April 2012 - April 2015
Synopsys December 2011 - April 2012
Synopsys November 2009 - November 2011
Synopsys June 2008 - October 2009
Mentor Graphics February 2005 - June 2008
Tera systems October 1999 - January 2005
IBM EDA Lab. October 1996 - October 1999
Amiable Technologies June 1992 - September 1996
Tsinghua University October 1984 - September 1990
Skills
EDA, AMS Floorplanning, Routing, STA Engine, Design Methodology, Algorithms, TCL, Device Drivers, ASIC, Perl, VLSI, Floorplanning, SoC, FPGA, Static Timing Analysis, Physical Design, Debugging, Integrated Circuit..., RTL design, Low-power Design, IC
Education
Saint Joseph's University 1990 — 1992
MSCS, AI, Algorithm
Tsinghua University 1982 — 1984
MSEE, Communication systems, CAD and ASIC design
Dalian University of Technology 1978 — 1982
BSEE, Radio electronics, TV systems, RF circuits and information theory
Travis Lemmer's Atoptech Experience September 2012 - Present
Job Sr. Staff Applications Engineer at Atoptech
Industry Design
Experience
Atoptech September 2012 - Present
Synopsys April 2012 - September 2012
Magma Design Automation July 2003 - April 2012
Cygnal Integrated Products February 2003 - May 2003
Advanced Micro Devices 2000 - 2002
Philips Semiconductor 1999 - 2000
VLSI Technologies, Inc. 1996 - 1999
United States Air Force July 1992 - July 1996
Skills
Timing Closure, Automation, Static Timing Analysis, Low Power Design, Physical Design, Clock Tree Synthesis, EDA, Low-power Design, IC, VLSI, SoC, ASIC, TCL, Semiconductors, Primetime, Verilog, Magma, DRC, Floorplanning, Processors, DFT, Physical Verification, Timing, CMOS, Formal Verification, LVS, Integrated Circuit..., RTL design, Signal Integrity, FPGA, Functional Verification, Microprocessors, Mixed Signal
Education
The University of Texas at Austin 2000 — 2003
BSEE, Computer and Semiconductor Engineering
Atoptech September 2012 - Present
Synopsys April 2012 - September 2012
Magma Design Automation July 2003 - April 2012
Cygnal Integrated Products February 2003 - May 2003
Advanced Micro Devices 2000 - 2002
Philips Semiconductor 1999 - 2000
VLSI Technologies, Inc. 1996 - 1999
United States Air Force July 1992 - July 1996
Skills
Timing Closure, Automation, Static Timing Analysis, Low Power Design, Physical Design, Clock Tree Synthesis, EDA, Low-power Design, IC, VLSI, SoC, ASIC, TCL, Semiconductors, Primetime, Verilog, Magma, DRC, Floorplanning, Processors, DFT, Physical Verification, Timing, CMOS, Formal Verification, LVS, Integrated Circuit..., RTL design, Signal Integrity, FPGA, Functional Verification, Microprocessors, Mixed Signal
Education
The University of Texas at Austin 2000 — 2003
BSEE, Computer and Semiconductor Engineering
Debshankar Saha's Atoptech Experience April 2010 - January 2011
Job Digital Physical Design, Staff Solutions , Strategic Accounts at Cadence Design Systems
Industry Computer Hardware
Experience
Cadence Design Systems June 2015 - Present
Mentor Graphics Corporation January 2012 - Present
Mentor Graphics January 2011 - Present
Mentor Graphics Corporation January 2011 - Present
Atoptech April 2010 - January 2011
Atoptech Inc April 2010 - December 2010
Cadence Design Systems Inc. May 1998 - May 2010
AE January 2001 - April 2010
Cadence Design Systems I Pvt. Ltd. January 1998 - January 2001
ST Micro 1998 - 2000
Skills
EDA, ASIC, SoC, Clock Tree Synthesis, Physical Design, Static Timing Analysis, TCL, Timing Closure, Semiconductors, VLSI, IC, Cadence, Microprocessors, Cross-functional Team..., Place & Route, Parasitic Extraction, Timing, Perl, Low-power Design, Verilog, Integrated Circuit..., Simulations, Functional Verification, RTL design, Debugging, FPGA, SystemVerilog, Processors, Mixed Signal, ARM, Signal Integrity, Computer Architecture, Logic Synthesis, DFT, VHDL, Embedded Systems, Analog, Power Management, CMOS, ModelSim, Hardware Architecture, Circuit Design, Analog Circuit Design, RTL Design
Education
Jadavpur University 1984 — 1988
BE, Electronics & Telecommunication Engg
Cadence Design Systems June 2015 - Present
Mentor Graphics Corporation January 2012 - Present
Mentor Graphics January 2011 - Present
Mentor Graphics Corporation January 2011 - Present
Atoptech April 2010 - January 2011
Atoptech Inc April 2010 - December 2010
Cadence Design Systems Inc. May 1998 - May 2010
AE January 2001 - April 2010
Cadence Design Systems I Pvt. Ltd. January 1998 - January 2001
ST Micro 1998 - 2000
Skills
EDA, ASIC, SoC, Clock Tree Synthesis, Physical Design, Static Timing Analysis, TCL, Timing Closure, Semiconductors, VLSI, IC, Cadence, Microprocessors, Cross-functional Team..., Place & Route, Parasitic Extraction, Timing, Perl, Low-power Design, Verilog, Integrated Circuit..., Simulations, Functional Verification, RTL design, Debugging, FPGA, SystemVerilog, Processors, Mixed Signal, ARM, Signal Integrity, Computer Architecture, Logic Synthesis, DFT, VHDL, Embedded Systems, Analog, Power Management, CMOS, ModelSim, Hardware Architecture, Circuit Design, Analog Circuit Design, RTL Design
Education
Jadavpur University 1984 — 1988
BE, Electronics & Telecommunication Engg
Vaibhav Gokhale's Atoptech Experience April 2013 - Present
Job Staff Application Engineer at Atoptech
Industry Electrical/Electronic Manufacturing
Experience
Atoptech April 2013 - Present
Atoptech April 2013 - Present
Intersil Corporation June 2008 - April 2013
Intersil June 2008 - April 2012
Intersil Corporation June 2008 - April 2012
Skills
Place & Route, Design Compiler..., Design Compiler..., DFT Compiler, Synopsys Primetime, Tetramax, Encounter Power System, Cadence Conformal, Python, Perl, TCL, Cross Talk and Signal..., Static Timing Analysis, Cadence, Physical Design, SoC, Cadence Virtuoso, Logic Synthesis
Education
San Jose State University
Master of Science, Electrical Engineering (VLSI Design)
San Jose State University
Master of Science, Electrical Engineering (VLSI Design)
San Jose State University 2007 — 2007
University of Pune 2002 — 2006
BE, Electrical
University of Pune
Bachelor of Engineering, Electrical Engineering
University of Pune
Bachelor of Engineering, Electrical Engineering
Atoptech April 2013 - Present
Atoptech April 2013 - Present
Intersil Corporation June 2008 - April 2013
Intersil June 2008 - April 2012
Intersil Corporation June 2008 - April 2012
Skills
Place & Route, Design Compiler..., Design Compiler..., DFT Compiler, Synopsys Primetime, Tetramax, Encounter Power System, Cadence Conformal, Python, Perl, TCL, Cross Talk and Signal..., Static Timing Analysis, Cadence, Physical Design, SoC, Cadence Virtuoso, Logic Synthesis
Education
San Jose State University
Master of Science, Electrical Engineering (VLSI Design)
San Jose State University
Master of Science, Electrical Engineering (VLSI Design)
San Jose State University 2007 — 2007
University of Pune 2002 — 2006
BE, Electrical
University of Pune
Bachelor of Engineering, Electrical Engineering
University of Pune
Bachelor of Engineering, Electrical Engineering
Lin Yuan's Atoptech Experience April 2013 - Present
Job Software Engineer at Atoptech
Industry Computer Software
Experience
Atoptech April 2013 - Present
Synopsys April 2012 - April 2013
Synopsys May 2008 - April 2012
Synopsys June 2006 - May 2008
Microsoft June 2005 - August 2005
Skills
C++, Algorithms, C, Machine Learning, Java, Verilog, FPGA, EDA, Embedded Systems, TCL, Integrated Circuit..., Simulations, Yacc, Lex, Software Engineering, VLSI, Software Development, Software Design
Education
University of Maryland College Park 2001 — 2006
Ph.D., Computer Engineering
Xi'an Jiaotong University 1996 — 2001
B.S., Information and Communication Engineering
High School Attached to Hunan Normal University
Atoptech April 2013 - Present
Synopsys April 2012 - April 2013
Synopsys May 2008 - April 2012
Synopsys June 2006 - May 2008
Microsoft June 2005 - August 2005
Skills
C++, Algorithms, C, Machine Learning, Java, Verilog, FPGA, EDA, Embedded Systems, TCL, Integrated Circuit..., Simulations, Yacc, Lex, Software Engineering, VLSI, Software Development, Software Design
Education
University of Maryland College Park 2001 — 2006
Ph.D., Computer Engineering
Xi'an Jiaotong University 1996 — 2001
B.S., Information and Communication Engineering
High School Attached to Hunan Normal University
Odysseus Fang's Atoptech Experience February 2010 - Present
Job
Industry Computer Software
Experience
Atoptech February 2010 - Present
Cadence Design Systems July 2007 - August 2009
Synopsys August 2003 - July 2007
eWave System, Inc. June 2001 - July 2003
WavePlus Technology Co., Ltd. October 1999 - June 2001
Siemens Telecommunications System Limited June 1998 - September 1999
Skills
TCL, Verilog, Logic Analyzer, C++, VHDL, Perl, Java, Programming, Operating Systems, Csh, Spectrum Analyzer, Awk, IC, EDA, C, Debugging, FPGA, RTL design, VLSI, Assembly, ModelSim, ASIC, Static Timing Analysis, Linux, Unix, Shell Scripting, CVS, SoC, Testing, Microprocessors, Windows, HTML, CSS
Education
National Tsing Hua University 1994 — 1996
Master
National Tsing Hua University 1989 — 1994
Bachelor
Atoptech February 2010 - Present
Cadence Design Systems July 2007 - August 2009
Synopsys August 2003 - July 2007
eWave System, Inc. June 2001 - July 2003
WavePlus Technology Co., Ltd. October 1999 - June 2001
Siemens Telecommunications System Limited June 1998 - September 1999
Skills
TCL, Verilog, Logic Analyzer, C++, VHDL, Perl, Java, Programming, Operating Systems, Csh, Spectrum Analyzer, Awk, IC, EDA, C, Debugging, FPGA, RTL design, VLSI, Assembly, ModelSim, ASIC, Static Timing Analysis, Linux, Unix, Shell Scripting, CVS, SoC, Testing, Microprocessors, Windows, HTML, CSS
Education
National Tsing Hua University 1994 — 1996
Master
National Tsing Hua University 1989 — 1994
Bachelor
Dennis Shumaker's Atoptech Experience June 2012 - Present
Job Lead Applications Engineer at Atoptech
Industry Semiconductors
Experience
Atoptech June 2012 - Present
ST Microelectronics August 2010 - July 2012
Sigma Designs June 2009 - August 2010
Magma Design Automation September 2003 - February 2009
LSI Logic May 1999 - April 2003
Advanced Micro Devices 1998 - 1999
Synopsys May 1995 - March 1998
Skills
Static Timing Analysis, Physical Design, ASIC, TCL, DRC, Floorplanning
Education
Lawrence Technological University 1982 — 1986
BS, Electrical Engineering
Atoptech June 2012 - Present
ST Microelectronics August 2010 - July 2012
Sigma Designs June 2009 - August 2010
Magma Design Automation September 2003 - February 2009
LSI Logic May 1999 - April 2003
Advanced Micro Devices 1998 - 1999
Synopsys May 1995 - March 1998
Skills
Static Timing Analysis, Physical Design, ASIC, TCL, DRC, Floorplanning
Education
Lawrence Technological University 1982 — 1986
BS, Electrical Engineering
Jue-Hsien Chern's Atoptech Experience December 2009 - Present
Job Semiconductors Professional
Industry Semiconductors
Experience
Atoptech December 2009 - Present
Atoptech February 2009 - December 2009
Mentor Graphics January 2000 - November 2008
Avant! January 1998 - August 1999
TMA 1994 - 1997
Texas Instruments 1984 - 1994
Education
University at Buffalo 1978 — 1981
Ph.D., Engineering
National Taiwan University 1976 — 1978
MS, Civil Engineering
Atoptech December 2009 - Present
Atoptech February 2009 - December 2009
Mentor Graphics January 2000 - November 2008
Avant! January 1998 - August 1999
TMA 1994 - 1997
Texas Instruments 1984 - 1994
Education
University at Buffalo 1978 — 1981
Ph.D., Engineering
National Taiwan University 1976 — 1978
MS, Civil Engineering
Antony Tseng's Atoptech Experience EngineerSynopsysSeptember 1999 - June 2005
Job Principal Engineer at Atoptech
Industry Computer Software
Experience
Atoptech EngineerSynopsysSeptember 1999 - June 2005
Intel Corporation January 1996 - September 1999
Synthesys Technologies, Inc., August 1994 - December 1995
Education
The University of Texas at Austin 1992 — 1994
Master, Computer Engineer
National Taiwan University 1986 — 1990
BS, Electrical Engineering
Atoptech EngineerSynopsysSeptember 1999 - June 2005
Intel Corporation January 1996 - September 1999
Synthesys Technologies, Inc., August 1994 - December 1995
Education
The University of Texas at Austin 1992 — 1994
Master, Computer Engineer
National Taiwan University 1986 — 1990
BS, Electrical Engineering
Philippe Troin's Atoptech Experience December 2004 - January 2006
Job CTO at Cold Creek Technologies
Industry Computer Software
Experience
Cold Creek Technologies April 2012 - Present
FifSource March 2006 - Present
Radius Marketing May 2010 - December 2011
GroupPulse 2010 - 2010
Splunk 2007 - 2009
BuzzLogic 2006 - 2008
Atoptech December 2004 - January 2006
Synopsys August 2002 - September 2004
CommerceFlow January 2001 - June 2002
Aristo Technology May 1998 - January 2001
Skills
Perl, EDA, TCL, Linux, C++, C, Verilog, Distributed Systems, Algorithms, Scalability, Software Development, VHDL, Java, Debugging, Start-ups, Big Data, Python, Hadoop, Semiconductors, Bash, Software Engineering, System Architecture, Shell Scripting, Unix
Education
Institut polytechnique de Grenoble
Cold Creek Technologies April 2012 - Present
FifSource March 2006 - Present
Radius Marketing May 2010 - December 2011
GroupPulse 2010 - 2010
Splunk 2007 - 2009
BuzzLogic 2006 - 2008
Atoptech December 2004 - January 2006
Synopsys August 2002 - September 2004
CommerceFlow January 2001 - June 2002
Aristo Technology May 1998 - January 2001
Skills
Perl, EDA, TCL, Linux, C++, C, Verilog, Distributed Systems, Algorithms, Scalability, Software Development, VHDL, Java, Debugging, Start-ups, Big Data, Python, Hadoop, Semiconductors, Bash, Software Engineering, System Architecture, Shell Scripting, Unix
Education
Institut polytechnique de Grenoble
Ganping Sun's Atoptech Experience 2005 - 2012
Job Sr. Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2013 - Present
Cadence Design Systems 2012 - July 2013
Atoptech 2005 - 2012
Synopsys 2002 - 2005
Avanti 2001 - 2002
Education
Tsinghua University
B.E., M.E.
University of California, Berkeley
M.S, Ph.D.
Cadence Design Systems July 2013 - Present
Cadence Design Systems 2012 - July 2013
Atoptech 2005 - 2012
Synopsys 2002 - 2005
Avanti 2001 - 2002
Education
Tsinghua University
B.E., M.E.
University of California, Berkeley
M.S, Ph.D.
Bennet Kao's Atoptech Experience 2013 - Present
Job ASIC Physical Design Engineer
Industry Semiconductors
Experience
Atoptech 2013 - Present
Uniquify Inc 2010 - 2013
Uniquify Inc November 2007 - September 2010
Skills
Static Timing Analysis, VLSI, Verilog, Timing Closure, ASIC, SoC, DFT, Primetime, Physical Verification, Floorplanning, Timing, Power Analysis, Logic Synthesis
Education
UCSD 2002 — 2007
Bachelor of Science (B.S.), Electrical Engineering
Atoptech 2013 - Present
Uniquify Inc 2010 - 2013
Uniquify Inc November 2007 - September 2010
Skills
Static Timing Analysis, VLSI, Verilog, Timing Closure, ASIC, SoC, DFT, Primetime, Physical Verification, Floorplanning, Timing, Power Analysis, Logic Synthesis
Education
UCSD 2002 — 2007
Bachelor of Science (B.S.), Electrical Engineering
Phil Potter's Atoptech Experience June 2013 - Present
Job Applications Engineer at Atoptech
Industry Information Technology and Services
Experience
Atoptech June 2013 - Present
Skills
Cadence Virtuoso, Electrical Engineering, CMOS, IC, Hardware, Computer Hardware, Perl, Microprocessors, Cadence Virtuoso XL, Team Leadership, Circuit Design, Integrated Circuit..., Floorplanning, Static Timing Analysis, VHDL, VLSI, Semiconductors, Logic Synthesis, TCL, Verilog, EDA, Hardware Architecture, Processors, SoC, Debugging, Computer Architecture, RTL design, FPGA, Timing Closure
Education
University of Southern California 2002 — 2005
MS, Electrical Engineering
University of Southern California 1998 — 2002
BS, Electrical Engineering
Atoptech June 2013 - Present
Skills
Cadence Virtuoso, Electrical Engineering, CMOS, IC, Hardware, Computer Hardware, Perl, Microprocessors, Cadence Virtuoso XL, Team Leadership, Circuit Design, Integrated Circuit..., Floorplanning, Static Timing Analysis, VHDL, VLSI, Semiconductors, Logic Synthesis, TCL, Verilog, EDA, Hardware Architecture, Processors, SoC, Debugging, Computer Architecture, RTL design, FPGA, Timing Closure
Education
University of Southern California 2002 — 2005
MS, Electrical Engineering
University of Southern California 1998 — 2002
BS, Electrical Engineering
Hsin-Chia Tseng's Atoptech Experience July 2013 - Present
Job R&D Engineer at Atoptech
Industry Computer Software
Experience
Atoptech July 2013 - Present
Atoptech June 2009 - June 2013
Synopsys June 2002 - June 2009
Avant! June 1997 - June 2002
Skills
EDA, DRC, Layout Editor, Place & Route, Detail Router, Verilog, ASIC, Semiconductors
Education
National Taiwan University 1992 — 1995
Master of Science (M.S.), Electrical and Electronics Engineering
National Chiao Tung University 1988 — 1992
Bachelor of Science (B.S.), Computer Science and Information Engineering
Atoptech July 2013 - Present
Atoptech June 2009 - June 2013
Synopsys June 2002 - June 2009
Avant! June 1997 - June 2002
Skills
EDA, DRC, Layout Editor, Place & Route, Detail Router, Verilog, ASIC, Semiconductors
Education
National Taiwan University 1992 — 1995
Master of Science (M.S.), Electrical and Electronics Engineering
National Chiao Tung University 1988 — 1992
Bachelor of Science (B.S.), Computer Science and Information Engineering
Deloitte
PwC
Ernst & Young
Walgreens
Procter & Gamble
KPMG
PricewaterhouseCoopers
EY