Cadence Design System
Industry: Software company
DescriptionCadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. Headquarters: San Jose, CA CEO: Lip-Bu Tan (Jan 2009–) Revenue: 1.816 billion USD (2016) Subsidiaries: Sigrity, Tensilica, nusemi inc, Chip Estimate Corp,
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Cadence Design System Employees
Employee
Years
Job
Industry
Atlas Yeo Atlas Yeo's Cadence Design System Experience July 2003 - November 2003
Job IT Manager West Coast USA Region at ANSYS, Inc.
Industry Computer Software
Experience
ANSYS, Inc. April 2014 - Present
Apache Design Solutions October 2007 - April 2014
Magma Design Automation June 2006 - October 2007
Jasper Design Automation November 2003 - June 2006
Cadence Design System July 2003 - November 2003
Verplex Systems November 2000 - July 2003
GWCom 2000 - 2000
Skills
Unix, Linux, Solaris, Bash, C, VMware, Perl, Project Management, IT Operations, IT Management, Vendor Management, Network Administration, Apache, Software Development, Shell Scripting, Strategy, Start-ups, Networking, Operating Systems, EDA, Debugging, Cloud Computing, Wireless, System Architecture, C++
Education
Iowa State University 1995 — 1998
Bsc Electrical Engineering, Electrical Engineering
Iowa State University 1995 — 1998
Bachelor of Science (B.S.), Electrical and Electronics Engineering
ANSYS, Inc. April 2014 - Present
Apache Design Solutions October 2007 - April 2014
Magma Design Automation June 2006 - October 2007
Jasper Design Automation November 2003 - June 2006
Cadence Design System July 2003 - November 2003
Verplex Systems November 2000 - July 2003
GWCom 2000 - 2000
Skills
Unix, Linux, Solaris, Bash, C, VMware, Perl, Project Management, IT Operations, IT Management, Vendor Management, Network Administration, Apache, Software Development, Shell Scripting, Strategy, Start-ups, Networking, Operating Systems, EDA, Debugging, Cloud Computing, Wireless, System Architecture, C++
Education
Iowa State University 1995 — 1998
Bsc Electrical Engineering, Electrical Engineering
Iowa State University 1995 — 1998
Bachelor of Science (B.S.), Electrical and Electronics Engineering
Joy Ghosh, Ph.D. Joy Ghosh, Ph.D.'s Cadence Design System Experience May 2003 - August 2003
Job Manager, R&D at VMware
Industry Computer Software
Experience
VMware June 2015 - Present
VMware June 2014 - Present
VMware June 2013 - June 2014
VMware June 2011 - June 2013
Yahoo! Inc. September 2006 - June 2011
State University of New York at Buffalo August 2001 - August 2006
Nokia Research Center June 2005 - August 2005
Fujitsu Labs of America January 2005 - May 2005
Cadence Design System May 2003 - August 2003
Cadence Design System May 2002 - August 2002
Skills
Distributed Systems, EDA, Algorithms, Perl, C/C++ STL, Python, PHP, Scalable Architecture, Client/server, Server Architecture, Network Communications, C++, High Performance..., Java, C, Software Design, REST, Integration, Testing, Operating Systems, Architectures, Software Engineering, Shell Scripting, Architecture
Education
University at Buffalo 2001 — 2006
MS, PhD, Computer Science
Jadavpur University 1995 — 1999
B.E., Computer Science
VMware June 2015 - Present
VMware June 2014 - Present
VMware June 2013 - June 2014
VMware June 2011 - June 2013
Yahoo! Inc. September 2006 - June 2011
State University of New York at Buffalo August 2001 - August 2006
Nokia Research Center June 2005 - August 2005
Fujitsu Labs of America January 2005 - May 2005
Cadence Design System May 2003 - August 2003
Cadence Design System May 2002 - August 2002
Skills
Distributed Systems, EDA, Algorithms, Perl, C/C++ STL, Python, PHP, Scalable Architecture, Client/server, Server Architecture, Network Communications, C++, High Performance..., Java, C, Software Design, REST, Integration, Testing, Operating Systems, Architectures, Software Engineering, Shell Scripting, Architecture
Education
University at Buffalo 2001 — 2006
MS, PhD, Computer Science
Jadavpur University 1995 — 1999
B.E., Computer Science
Sarvesh Kumar Varshnay Sarvesh Kumar Varshnay's Cadence Design System Experience December 2004 - March 2006
Job Senior Service Architect CA Technologies
Industry Information Technology and Services
Experience
CA Technologies February 2008 - Present
IBM India Pvt Ltd May 2005 - April 2006
Cadence Design System December 2004 - March 2006
Oracle India Pvt Ltd January 2004 - December 2004
Parsec Technology Ltd July 2000 - September 2002
Skills
HTML, Integration, Agile Methodologies, Telecommunications, Security, SOA, Software Development, Siteminder, Java, Java Enterprise Edition, Web Services, Solution Architecture, C, C++, Software Project..., XML, Linux, Unix, Management, Eclipse, Spring, Design Patterns, Perl, Object Oriented Design, Servlets, Multithreading, Distributed Systems, Hibernate, JSP, Software Engineering, Tomcat, Scrum, Struts, Enterprise Architecture, JMS, Software Design
Education
Indian Institute of Technology, Roorkee 1996 — 2000
B.Tech, Computer Science & Technology
IDPL Inter Collge, Rishikesh 1994 — 1996
SSC, Maths
CA Technologies February 2008 - Present
IBM India Pvt Ltd May 2005 - April 2006
Cadence Design System December 2004 - March 2006
Oracle India Pvt Ltd January 2004 - December 2004
Parsec Technology Ltd July 2000 - September 2002
Skills
HTML, Integration, Agile Methodologies, Telecommunications, Security, SOA, Software Development, Siteminder, Java, Java Enterprise Edition, Web Services, Solution Architecture, C, C++, Software Project..., XML, Linux, Unix, Management, Eclipse, Spring, Design Patterns, Perl, Object Oriented Design, Servlets, Multithreading, Distributed Systems, Hibernate, JSP, Software Engineering, Tomcat, Scrum, Struts, Enterprise Architecture, JMS, Software Design
Education
Indian Institute of Technology, Roorkee 1996 — 2000
B.Tech, Computer Science & Technology
IDPL Inter Collge, Rishikesh 1994 — 1996
SSC, Maths
Monjur Alam Monjur Alam's Cadence Design System Experience March 2008 - February 2012
Job Graduate Research Assistant at Georgia State University
Industry Computer & Network Security
Experience
Georgia State University August 2013 - Present
Applied Research Works India Pvt. Ltd. February 2012 - July 2013
Cadence Design System March 2008 - February 2012
Indian Institute of Technology, Kharagpur May 2005 - February 2008
Skills
C++, C, Algorithms, Java, Linux, Perl, VLSI, Software Development, Python, Matlab
Education
Georgia State University 2013 — 2015
Master's Degree, Computer Science
Indian Institute of Technology, Kharagpur 2005 — 2008
MS, CSE
West Bengal University of Technology 2001 — 2005
B.Tech, Information Technology
Georgia State University August 2013 - Present
Applied Research Works India Pvt. Ltd. February 2012 - July 2013
Cadence Design System March 2008 - February 2012
Indian Institute of Technology, Kharagpur May 2005 - February 2008
Skills
C++, C, Algorithms, Java, Linux, Perl, VLSI, Software Development, Python, Matlab
Education
Georgia State University 2013 — 2015
Master's Degree, Computer Science
Indian Institute of Technology, Kharagpur 2005 — 2008
MS, CSE
West Bengal University of Technology 2001 — 2005
B.Tech, Information Technology
Chang-Hong Hsu Chang-Hong Hsu's Cadence Design System Experience July 2008 - August 2008
Job PHD Candidate at University of Michigan
Industry Electrical/Electronic Manufacturing
Experience
University of Michigan September 2014 - Present
University of Michigan September 2014 - Present
University of Michigan September 2013 - Present
University of Michigan September 2012 - Present
Academia Sinica, Taiwan December 2011 - July 2012
Department of Electrical Engineering at National Taiwan University September 2009 - June 2010
Cadence Design System July 2008 - August 2008
Skills
EDA, Software Engineering, CAD, Electrical Engineering, Verilog, Matlab, Algorithms, C++, C, Programming, Vim, Linux, Machine Learning, HTML, FPGA, Embedded Systems, VLSI, Microprocessors, Computer Architecture, Verification, Formal Verification, Electronics, Digital Design, Simulation, Circuit Design, Digital Electronics, JavaScript, PHP, Hardware Design, Python, Software Verification, Simulations, RTL design, Perl, Image Processing, ARM, Debugging, LaTeX, Hardware Architecture
Education
University of Michigan 2012 — 2017
Doctor of Philosophy (PhD), Computer Engineering
National Taiwan University 2008 — 2011
Master of Science (MS), Electrical Engineering, 4.0
National Taiwan University 2004 — 2008
Bachelor of Science (BS), Electrical Engineering
University of Michigan September 2014 - Present
University of Michigan September 2014 - Present
University of Michigan September 2013 - Present
University of Michigan September 2012 - Present
Academia Sinica, Taiwan December 2011 - July 2012
Department of Electrical Engineering at National Taiwan University September 2009 - June 2010
Cadence Design System July 2008 - August 2008
Skills
EDA, Software Engineering, CAD, Electrical Engineering, Verilog, Matlab, Algorithms, C++, C, Programming, Vim, Linux, Machine Learning, HTML, FPGA, Embedded Systems, VLSI, Microprocessors, Computer Architecture, Verification, Formal Verification, Electronics, Digital Design, Simulation, Circuit Design, Digital Electronics, JavaScript, PHP, Hardware Design, Python, Software Verification, Simulations, RTL design, Perl, Image Processing, ARM, Debugging, LaTeX, Hardware Architecture
Education
University of Michigan 2012 — 2017
Doctor of Philosophy (PhD), Computer Engineering
National Taiwan University 2008 — 2011
Master of Science (MS), Electrical Engineering, 4.0
National Taiwan University 2004 — 2008
Bachelor of Science (BS), Electrical Engineering
Ting-Yuan Sung Ting-Yuan Sung's Cadence Design System Experience 1993 - 1995
Job Design Automation Engineer at Intel Corporation
Industry Computer Software
Experience
Intel Corporation August 2012 - Present
Synopsys 2005 - 2012
Nassda Inc 2002 - 2005
Synplicity Inc 1999 - 2001
National Semiconductor 1995 - 1997
Cadence Design System 1993 - 1995
Silvar-Lisco Inc 1989 - 1993
Skills
C, C++, Fortran, YACC,..., HSIM, HSPICE, Amplify,..., Linux, PC/Window,..., GDB/Linux, Visual..., EDA, Verilog, VLSI, Mixed Signal, Semiconductors, Simulations, Circuit Design, Software Engineering, Software Development, ASIC, Static Timing Analysis, Logic Synthesis, Debugging, FPGA, Analog
Education
University of Colorado at Boulder 1987 — 1989
Master's degree, Electrical and Computer Engineering
Chung Yuan Christian University
Bachelor's degree, Electronics Engineering
Intel Corporation August 2012 - Present
Synopsys 2005 - 2012
Nassda Inc 2002 - 2005
Synplicity Inc 1999 - 2001
National Semiconductor 1995 - 1997
Cadence Design System 1993 - 1995
Silvar-Lisco Inc 1989 - 1993
Skills
C, C++, Fortran, YACC,..., HSIM, HSPICE, Amplify,..., Linux, PC/Window,..., GDB/Linux, Visual..., EDA, Verilog, VLSI, Mixed Signal, Semiconductors, Simulations, Circuit Design, Software Engineering, Software Development, ASIC, Static Timing Analysis, Logic Synthesis, Debugging, FPGA, Analog
Education
University of Colorado at Boulder 1987 — 1989
Master's degree, Electrical and Computer Engineering
Chung Yuan Christian University
Bachelor's degree, Electronics Engineering
Tom Valind Tom Valind's Cadence Design System Experience February 1999 - February 2004
Job Product Engineer for Encounter Test at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems February 2004 - Present
Cadence Design System February 1999 - February 2004
Cadence Design Systems, Inc February 1996 - February 1999
Unisys 1980 - 1996
Skills
Verilog, EDA, TCL, Linux, Perl, DFT, C++, Simulations, Testing, ASIC, Unix, ATPG
Education
Michigan State University
Cadence Design Systems February 2004 - Present
Cadence Design System February 1999 - February 2004
Cadence Design Systems, Inc February 1996 - February 1999
Unisys 1980 - 1996
Skills
Verilog, EDA, TCL, Linux, Perl, DFT, C++, Simulations, Testing, ASIC, Unix, ATPG
Education
Michigan State University
Martin Pitasi Martin Pitasi's Cadence Design System Experience 1995 - 1998
Job at HTE Associates, Inc.
Industry Electrical/Electronic Manufacturing
Experience
HTE Associates April 1999 - Present
General Compression February 2009 - March 2009
Teradyne, Inc. March 2008 - September 2008
BAE Systems November 2007 - March 2008
Cadence Design System 1995 - 1998
Hewlett-Packard/Apollo 1988 - 1995
Teradyne, Inc. November 1979 - October 1988
American Science and Engineering 1974 - 1979
Education
Northeastern University 1962 — 1966
BS, Mechanical Engineering
Wentworth Institute of Technology 1960 — 1962
Associates, Mechanical Engineering-MEP
HTE Associates April 1999 - Present
General Compression February 2009 - March 2009
Teradyne, Inc. March 2008 - September 2008
BAE Systems November 2007 - March 2008
Cadence Design System 1995 - 1998
Hewlett-Packard/Apollo 1988 - 1995
Teradyne, Inc. November 1979 - October 1988
American Science and Engineering 1974 - 1979
Education
Northeastern University 1962 — 1966
BS, Mechanical Engineering
Wentworth Institute of Technology 1960 — 1962
Associates, Mechanical Engineering-MEP
Katherine Gambino Katherine Gambino's Cadence Design System Experience 2000 - January 2012
Job Senior Sales Executive, Semiconductor IP, EDA Software, Consulting Services
Industry Semiconductors
Experience
Cadence Design Systems 2012 - 2015
Cadence Design System 2000 - January 2012
Cadence 1996 - 2000
Valid Logic Systems and Cadence Design Systems 1991 - 1996
Valid Logic Systems (merged with Cadence Design Systems) 1986 - 1991
Telesis, merged with Valid Logic Systems 1984 - 1986
Skills
ASIC, EDA, Marketing, SoC, IC, Public Relations, Semiconductors, Physical Verification, Marketing Communications, CMOS, Analog Circuit Design, FPGA, Product Marketing, DRC, LVS, Integrated Circuit..., Analog, Mixed Signal, TCL, Technical Marketing, Management, Cross-functional Team..., Sales Presentations, Marketing Strategy, Strategic Sales, Intellectual Property, Sales Process, Strategic Sales Plans, Sales Management, Sales Strategy, Salesforce.com
Education
Barnard College
Political Science and Government
Barnard College, Columbia University
Political Science
Cadence Design Systems 2012 - 2015
Cadence Design System 2000 - January 2012
Cadence 1996 - 2000
Valid Logic Systems and Cadence Design Systems 1991 - 1996
Valid Logic Systems (merged with Cadence Design Systems) 1986 - 1991
Telesis, merged with Valid Logic Systems 1984 - 1986
Skills
ASIC, EDA, Marketing, SoC, IC, Public Relations, Semiconductors, Physical Verification, Marketing Communications, CMOS, Analog Circuit Design, FPGA, Product Marketing, DRC, LVS, Integrated Circuit..., Analog, Mixed Signal, TCL, Technical Marketing, Management, Cross-functional Team..., Sales Presentations, Marketing Strategy, Strategic Sales, Intellectual Property, Sales Process, Strategic Sales Plans, Sales Management, Sales Strategy, Salesforce.com
Education
Barnard College
Political Science and Government
Barnard College, Columbia University
Political Science
Sergio Peratoner Sergio Peratoner's Cadence Design System Experience 2001 - Present
Job Account Manager Technical at CDN
Industry Computer Software
Experience
Cadence Design Systems 2001 - Present
Cadence Design System 2001 - Present
Skills
EDA, Linux, IC, VHDL, SoC, Semiconductors, ASIC, Mixed Signal, Verilog, VLSI, Analog, Debugging, FPGA, Perl
Education
University of Southern California
Master's Degree, Electrical Engineering - Communications Systems, M.S.E.E
University of Southern California
Bachelor's Degree, Bachelor's Electrical Engineering, Bachelor's Degree
Don Bosco Technical Institute
Associate's Degree, Associate's Degree Electronics Technology
Cadence Design Systems 2001 - Present
Cadence Design System 2001 - Present
Skills
EDA, Linux, IC, VHDL, SoC, Semiconductors, ASIC, Mixed Signal, Verilog, VLSI, Analog, Debugging, FPGA, Perl
Education
University of Southern California
Master's Degree, Electrical Engineering - Communications Systems, M.S.E.E
University of Southern California
Bachelor's Degree, Bachelor's Electrical Engineering, Bachelor's Degree
Don Bosco Technical Institute
Associate's Degree, Associate's Degree Electronics Technology
Allan Chan Allan Chan's Cadence Design System Experience May 1996 - May 1998
Job
Industry Semiconductors
Experience
Sigma Designs December 2014 - Present
Sigma Designs October 2009 - December 2014
CopperGate Communications (acquired by Sigma Designs) October 2008 - October 2009
Opnext, Inc July 2007 - October 2008
Innovative Communications Engineering, LLC October 2006 - June 2007
PMC-Sierra October 2005 - March 2007
AMCC June 1999 - July 2005
Cimaron Communications Corporation (Acquired by AMCC in June 1999) May 1998 - June 1999
Cadence Design System May 1996 - May 1998
Northeastern University June 1995 - May 1996
Skills
Ethernet, ATM, IP, OTN, HDLC, SONET, HPNA, HomePlugAV, G.hn, SDH, ATM networks, Testing, Hardware Architecture, IC, Analog, Semiconductors, Wireless, Debugging, Verilog, VLSI, Firmware, ASIC, EDA, SoC, Mixed Signal, Semiconductor Industry, FPGA, RTL design, Electronics, Simulations, Hardware
Education
Northeastern University 1994 — 1996
M.Sc., Electrical Engineering, GPA of 3.424/4.0
Northeastern University 1990 — 1994
B.Sc., Electrical Engineering, Graduated Magna Cum Laude; GPA of 3.639/4.0
Ghana International School 1979 — 1990
Cambridge 0-level and A-level
Sigma Designs December 2014 - Present
Sigma Designs October 2009 - December 2014
CopperGate Communications (acquired by Sigma Designs) October 2008 - October 2009
Opnext, Inc July 2007 - October 2008
Innovative Communications Engineering, LLC October 2006 - June 2007
PMC-Sierra October 2005 - March 2007
AMCC June 1999 - July 2005
Cimaron Communications Corporation (Acquired by AMCC in June 1999) May 1998 - June 1999
Cadence Design System May 1996 - May 1998
Northeastern University June 1995 - May 1996
Skills
Ethernet, ATM, IP, OTN, HDLC, SONET, HPNA, HomePlugAV, G.hn, SDH, ATM networks, Testing, Hardware Architecture, IC, Analog, Semiconductors, Wireless, Debugging, Verilog, VLSI, Firmware, ASIC, EDA, SoC, Mixed Signal, Semiconductor Industry, FPGA, RTL design, Electronics, Simulations, Hardware
Education
Northeastern University 1994 — 1996
M.Sc., Electrical Engineering, GPA of 3.424/4.0
Northeastern University 1990 — 1994
B.Sc., Electrical Engineering, Graduated Magna Cum Laude; GPA of 3.639/4.0
Ghana International School 1979 — 1990
Cambridge 0-level and A-level
Dennis L. Schneider's Cadence Design System Experience 2002 - January 2003
Job
Industry Information Technology and Services
Experience
DC Enterprises January 2005 - Present
Minnesota State Representative Race January 2006 - November 2008
MN DFL 2004 - 2008
Cadence Deisgn Systems 1999 - December 2004
Cadence Design Systems 1999 - 2004
Cadence Design System 2002 - January 2003
U.S. Senator Mark Dayton 1996 - 2002
Unisys 1967 - 1996
Skills
Project Management, Project Planning, People Skills, Problem Solving, Closings, Getting The Job Done, Get Along Well with..., Politics, TCL, Strategy, EDA, Budgets, Start-ups, Management, Program Management, Team Building, ASIC, Management Consulting, SoC, Product Management, Software Engineering, Verilog, Enterprise Architecture, New Business Development, Strategic Partnerships, Cloud Computing, Software Development, Semiconductors, Hardware, Integration, Simulations, Perl, Professional Services, Cross-functional Team..., Testing, Enterprise Software, Physical Design, Debugging, IT Strategy, System Architecture, FPGA, Leadership, Product Marketing, IC
Education
Case Western Reserve University 1964 — 1967
BS Eng
DC Enterprises January 2005 - Present
Minnesota State Representative Race January 2006 - November 2008
MN DFL 2004 - 2008
Cadence Deisgn Systems 1999 - December 2004
Cadence Design Systems 1999 - 2004
Cadence Design System 2002 - January 2003
U.S. Senator Mark Dayton 1996 - 2002
Unisys 1967 - 1996
Skills
Project Management, Project Planning, People Skills, Problem Solving, Closings, Getting The Job Done, Get Along Well with..., Politics, TCL, Strategy, EDA, Budgets, Start-ups, Management, Program Management, Team Building, ASIC, Management Consulting, SoC, Product Management, Software Engineering, Verilog, Enterprise Architecture, New Business Development, Strategic Partnerships, Cloud Computing, Software Development, Semiconductors, Hardware, Integration, Simulations, Perl, Professional Services, Cross-functional Team..., Testing, Enterprise Software, Physical Design, Debugging, IT Strategy, System Architecture, FPGA, Leadership, Product Marketing, IC
Education
Case Western Reserve University 1964 — 1967
BS Eng
Jay Sweeney's Cadence Design System Experience 1989 - 2004
Job Principal at Advanced Math and Science Academy Charter School skilled at turn around and change management
Industry Executive Office
Experience
Advanced Math and Science Academy Charter School December 2005 - Present
Self employed January 2005 - November 2011
Takumi Technologies January 2005 - December 2005
Think3 2004 - 2005
Cadence Design System 1989 - 2004
Cadence Design Systems 1989 - 2004
Cadence 1989 - 2004
DEC 1983 - 1989
Digital Equipment Corporation 1983 - 1989
Skills
SaaS, Enterprise Software, Sales, Business Strategy, Leadership, Curriculum Design, Strategic Planning, Public Speaking, Management, Strategic Partnerships, Go-to-market Strategy, Start-ups, Sales Operations, Solution Selling, Project Management, Curriculum Development, Consulting, Marketing, Teaching, Research
Education
Northeastern University 1983 — 1985
BSEE, Electrical Engineering
Assumption College 1976 — 1980
BAEC, Economics
Advanced Math and Science Academy Charter School December 2005 - Present
Self employed January 2005 - November 2011
Takumi Technologies January 2005 - December 2005
Think3 2004 - 2005
Cadence Design System 1989 - 2004
Cadence Design Systems 1989 - 2004
Cadence 1989 - 2004
DEC 1983 - 1989
Digital Equipment Corporation 1983 - 1989
Skills
SaaS, Enterprise Software, Sales, Business Strategy, Leadership, Curriculum Design, Strategic Planning, Public Speaking, Management, Strategic Partnerships, Go-to-market Strategy, Start-ups, Sales Operations, Solution Selling, Project Management, Curriculum Development, Consulting, Marketing, Teaching, Research
Education
Northeastern University 1983 — 1985
BSEE, Electrical Engineering
Assumption College 1976 — 1980
BAEC, Economics
Luh-Luh Ting's Cadence Design System Experience June 1990 - June 1994
Job Technical Leader at Cisco
Industry Telecommunications
Experience
Cisco Systems April 2006 - Present
Marvell January 2006 - April 2006
Luminous Networks Inc. December 2000 - December 2005
Combrio Networks 1998 - 2000
NeoParadigm Labs, Inc. June 1996 - September 1998
Synopsys June 1994 - June 1996
Cadence Design System June 1990 - June 1994
Skills
Embedded Systems, Network Processors
Education
Penn State University 1988 — 1990
MS, Computer Science
National Chiao Tung University 1984 — 1988
BS, Computer Science and Information Engineering
Cisco Systems April 2006 - Present
Marvell January 2006 - April 2006
Luminous Networks Inc. December 2000 - December 2005
Combrio Networks 1998 - 2000
NeoParadigm Labs, Inc. June 1996 - September 1998
Synopsys June 1994 - June 1996
Cadence Design System June 1990 - June 1994
Skills
Embedded Systems, Network Processors
Education
Penn State University 1988 — 1990
MS, Computer Science
National Chiao Tung University 1984 — 1988
BS, Computer Science and Information Engineering
Lin Sheng's Cadence Design System Experience January 1998 - February 2002
Job Design Manager at Texas Instruments
Industry Semiconductors
Experience
Texas Instruments April 2010 - Present
Texas Instruments Corp. February 2006 - August 2010
LTC February 2002 - January 2006
Cadence Design System January 1998 - February 2002
Skills
Mixed Signal, Power Management, IC, Analog, Analog Circuit Design, ASIC, Integrated Circuit..., CMOS, SoC, Circuit Design, Semiconductors, PLL, VLSI, Cadence Virtuoso, EDA
Education
Mississippi State University 1995 — 1997
MS, Electrical Engineer
Tsinghua University 1985 — 1990
BSEE, Electrical Engineering
Texas Instruments April 2010 - Present
Texas Instruments Corp. February 2006 - August 2010
LTC February 2002 - January 2006
Cadence Design System January 1998 - February 2002
Skills
Mixed Signal, Power Management, IC, Analog, Analog Circuit Design, ASIC, Integrated Circuit..., CMOS, SoC, Circuit Design, Semiconductors, PLL, VLSI, Cadence Virtuoso, EDA
Education
Mississippi State University 1995 — 1997
MS, Electrical Engineer
Tsinghua University 1985 — 1990
BSEE, Electrical Engineering
Yung-Ming Fang's Cadence Design System Experience Sr Member of Consulting StaffCadence Design Systems2003 - Present
Job Sr Member of Consulting Staff at Cadence Design System
Industry Computer Software
Experience
Cadence Design System Sr Member of Consulting StaffCadence Design Systems2003 - Present
Education
The University of Texas at Austin 1989 — 1996
Cadence Design System Sr Member of Consulting StaffCadence Design Systems2003 - Present
Education
The University of Texas at Austin 1989 — 1996
Lei Yin's Cadence Design System Experience March 2003 - September 2012
Job EDA professional
Industry Semiconductors
Experience
Gear Design Solutions September 2012 - Present
ANSYS, Inc. 2015 - 2015
ANSYS, Inc. 2015 - 2015
Cadence Design System March 2003 - September 2012
Celestry 2001 - 2003
Ultima Interconnect Technology Inc September 2000 - January 2001
Skills
C++, Linux, Perl, EDA, Unix Shell Scripting
Education
Southeast University 1990 — 2000
Ph. D, Microwave & Millimeter Waves Theory and Technologoies
Gear Design Solutions September 2012 - Present
ANSYS, Inc. 2015 - 2015
ANSYS, Inc. 2015 - 2015
Cadence Design System March 2003 - September 2012
Celestry 2001 - 2003
Ultima Interconnect Technology Inc September 2000 - January 2001
Skills
C++, Linux, Perl, EDA, Unix Shell Scripting
Education
Southeast University 1990 — 2000
Ph. D, Microwave & Millimeter Waves Theory and Technologoies
Mike Corry's Cadence Design System Experience 2001 - 2002
Job Senior VLSI Logic Designer at TI
Industry Semiconductors
Experience
TI SR. VLSI Logic DesignerTexas Instruments2003 - Present
Cadence Design System 2001 - 2002
Skills
Mixed Signal, Physical Design, Power Management, IC, Semiconductors, ASIC, SoC, DRC, CMOS, VLSI, Cadence Virtuoso, DFT, Debugging, Embedded Systems, LVS, Low-power Design, Semiconductor Industry, Verilog
Education
The University of Texas at Austin 1979 — 1982
TI SR. VLSI Logic DesignerTexas Instruments2003 - Present
Cadence Design System 2001 - 2002
Skills
Mixed Signal, Physical Design, Power Management, IC, Semiconductors, ASIC, SoC, DRC, CMOS, VLSI, Cadence Virtuoso, DFT, Debugging, Embedded Systems, LVS, Low-power Design, Semiconductor Industry, Verilog
Education
The University of Texas at Austin 1979 — 1982
Vardhani Harpanahalli's Cadence Design System Experience Sr Product Validation ManagerCadence Design SystemsFebruary 1997 - Present
Job Sr Product Validation Manager at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design System Sr Product Validation ManagerCadence Design SystemsFebruary 1997 - Present
Skills
EDA, ASIC, Product Lifecycle..., SoC, Go-to-market Strategy, C, SaaS, Product Marketing, Enterprise Software, TCL, VLSI, IC, Verilog, Semiconductors, Simulations
Education
University of Massachusetts Lowell 1993 — 1995
Cadence Design System Sr Product Validation ManagerCadence Design SystemsFebruary 1997 - Present
Skills
EDA, ASIC, Product Lifecycle..., SoC, Go-to-market Strategy, C, SaaS, Product Marketing, Enterprise Software, TCL, VLSI, IC, Verilog, Semiconductors, Simulations
Education
University of Massachusetts Lowell 1993 — 1995
amir borazjani's Cadence Design System Experience 2001 - 2005
Job staff application engineer at world hearing organization
Industry Computer Hardware
Experience
Cadence Design Systems February 2001 - November 2005
Cadence Design System 2001 - 2005
Cadmos January 2000 - February 2001
Synopsys March 1997 - December 1999
Xicor inc. February 1986 - March 1997
Education
Florida International University 1983 — 1985
Iowa State University 1980 — 1983
bachelor, industrial engineering
Cadence Design Systems February 2001 - November 2005
Cadence Design System 2001 - 2005
Cadmos January 2000 - February 2001
Synopsys March 1997 - December 1999
Xicor inc. February 1986 - March 1997
Education
Florida International University 1983 — 1985
Iowa State University 1980 — 1983
bachelor, industrial engineering
Alka Arora's Cadence Design System Experience January 2007 - January 2011
Job Product Engineer
Industry Semiconductors
Experience
Qualcomm December 2011 - July 2014
Cadence Design System January 2007 - January 2011
Skills
Logic Synthesis, EDA, VLSI, Physical Design, TCL, Formal Verification, Verilog, First Encounter, Floorplanning, Conformal, Static Timing Analysis, DRC, SoC, SystemVerilog, Functional Verification, ASIC, IC, RTL design, VHDL
Education
CDAC 2006 — 2007
Post Graduate diploma in VLSI And Embedded
Kurukshetra University 2001 — 2005
B.TECH, Electronics & Comm
Qualcomm December 2011 - July 2014
Cadence Design System January 2007 - January 2011
Skills
Logic Synthesis, EDA, VLSI, Physical Design, TCL, Formal Verification, Verilog, First Encounter, Floorplanning, Conformal, Static Timing Analysis, DRC, SoC, SystemVerilog, Functional Verification, ASIC, IC, RTL design, VHDL
Education
CDAC 2006 — 2007
Post Graduate diploma in VLSI And Embedded
Kurukshetra University 2001 — 2005
B.TECH, Electronics & Comm
Hewlett-Packard
SAP
Symantec
Intuit
HP
salesforce.com
Bloomberg LP
Autodesk