LarMon Design Inc
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LarMon Design Inc Employees
Employee
Years
Job
Industry
Michael Spagon Michael Spagon's LarMon Design Inc Experience August 2011 - August 2012
Job Physical Design Engineer at Intel Corporation
Industry Electrical/Electronic Manufacturing
Experience
Intel Corporation June 2013 - Present
HDH October 2012 - February 2013
LarMon Design Inc. August 2011 - August 2012
Education
The University of Texas at Austin 2015 — 2017
Masters of Science, Software engineering, 4.0 (Current)
The University of Texas at Austin 2007 — 2011
Bachelors of Science, Electrical and Computer Engineering
Westlake High School 2004 — 2007
Intel Corporation June 2013 - Present
HDH October 2012 - February 2013
LarMon Design Inc. August 2011 - August 2012
Education
The University of Texas at Austin 2015 — 2017
Masters of Science, Software engineering, 4.0 (Current)
The University of Texas at Austin 2007 — 2011
Bachelors of Science, Electrical and Computer Engineering
Westlake High School 2004 — 2007
Huan Dinh Huan Dinh's LarMon Design Inc Experience April 2010 - June 2013
Job
Industry Computer Hardware
Experience
AMD June 2013 - July 2015
LarMon Design Inc April 2010 - June 2013
Spansion November 2005 - March 2009
Education
The University of Texas at San Antonio 2005 — 2008
Master’s Degree, Computer Engineering
The University of Texas at San Antonio 1999 — 2002
Bachelor’s Degree, Electrical Enginnering
AMD June 2013 - July 2015
LarMon Design Inc April 2010 - June 2013
Spansion November 2005 - March 2009
Education
The University of Texas at San Antonio 2005 — 2008
Master’s Degree, Computer Engineering
The University of Texas at San Antonio 1999 — 2002
Bachelor’s Degree, Electrical Enginnering
Henry Thomas Jr.'s LarMon Design Inc Experience March 2009 - August 2010
Job Contract IC Layout Designer
Industry Electrical/Electronic Manufacturing
Experience
Qualcomm March 2014 - December 2014
Qualcomm September 2012 - November 2013
LarMon Design Inc. March 2009 - August 2010
AMD 2009 - 2009
Analog Devices May 2008 - August 2008
Analog Devices May 2008 - August 2008
Analog Devices May 2008 - August 2008
Maxim Integrated Products May 1984 - January 2008
Microtune 2008 - 2008
Dallas Semiconductor / Maxim 1984 - 2008
Skills
Mixed Signal, LVS, Dracula, CMOS, Cadence Virtuoso, DRC, Analog, Layout
Education
Palm Beach Community College 1974 — 1976
Qualcomm March 2014 - December 2014
Qualcomm September 2012 - November 2013
LarMon Design Inc. March 2009 - August 2010
AMD 2009 - 2009
Analog Devices May 2008 - August 2008
Analog Devices May 2008 - August 2008
Analog Devices May 2008 - August 2008
Maxim Integrated Products May 1984 - January 2008
Microtune 2008 - 2008
Dallas Semiconductor / Maxim 1984 - 2008
Skills
Mixed Signal, LVS, Dracula, CMOS, Cadence Virtuoso, DRC, Analog, Layout
Education
Palm Beach Community College 1974 — 1976
Mozammel Khan's LarMon Design Inc Experience May 2010 - November 2011
Job Computer Hardware Professional
Industry Computer Hardware
Experience
NVIDIA December 2011 - Present
LarMon Design Inc. May 2010 - November 2011
Catalyte IC Design May 2008 - April 2010
AMD January 2004 - April 2008
Cypress Semiconductor August 1997 - December 2003
AMD October 1995 - March 1997
Skills
Static Timing Analysis, Physical Verification, DRC, Low-power Design, Physical Design, Cadence, Analog Circuit Design
Education
City University of New York City College 1989 — 1991
Master's degree, Electrical Engineering
NVIDIA December 2011 - Present
LarMon Design Inc. May 2010 - November 2011
Catalyte IC Design May 2008 - April 2010
AMD January 2004 - April 2008
Cypress Semiconductor August 1997 - December 2003
AMD October 1995 - March 1997
Skills
Static Timing Analysis, Physical Verification, DRC, Low-power Design, Physical Design, Cadence, Analog Circuit Design
Education
City University of New York City College 1989 — 1991
Master's degree, Electrical Engineering
Nasim Uddin's LarMon Design Inc Experience April 2010 - January 2011
Job Component Design Engineer at Intel Corporation
Industry Computer Hardware
Experience
Intel Corporation January 2011 - Present
LarMon Design Inc. April 2010 - January 2011
Catalyte IC Design May 2009 - March 2010
AMD December 1995 - June 2008
Skills
IC, Integrated Circuit..., EDA, Primetime, Physical Design, SoC, Low-power Design, Logic Synthesis, Formal Verification, LVS, DRC, Microprocessors, Floorplanning, Physical Verification, Timing, Schematic Capture, ASIC, Verilog, VLSI, Integration, Static Timing Analysis, Semiconductors, Timing Closure, Mixed Signal, Processors
Education
Oklahoma State University 1992 — 1994
MS, Electrical Engineering
Bangladesh University of Engineering and Technology 1986 — 1991
BSc, Electrical & Electronic Engineering
Intel Corporation January 2011 - Present
LarMon Design Inc. April 2010 - January 2011
Catalyte IC Design May 2009 - March 2010
AMD December 1995 - June 2008
Skills
IC, Integrated Circuit..., EDA, Primetime, Physical Design, SoC, Low-power Design, Logic Synthesis, Formal Verification, LVS, DRC, Microprocessors, Floorplanning, Physical Verification, Timing, Schematic Capture, ASIC, Verilog, VLSI, Integration, Static Timing Analysis, Semiconductors, Timing Closure, Mixed Signal, Processors
Education
Oklahoma State University 1992 — 1994
MS, Electrical Engineering
Bangladesh University of Engineering and Technology 1986 — 1991
BSc, Electrical & Electronic Engineering
Larry Monks's LarMon Design Inc Experience April 2010 - December 2012
Job PresidentLarMon Design
Industry Semiconductors
Experience
LarMon Design Inc. April 2010 - December 2012
Spansion January 1999 - April 2010
Advanced Micro Devices 1985 - 1999
Motorola 1981 - 1985
Texas Instruments (Houston) 1976 - 1981
Skills
Semiconductors, LVS, IC, IC layout, Analog, CMOS, ASIC, DRC, Verilog, Floorplanning, Cadence Virtuoso, Physical Design, Mixed Signal, Circuit Design, Semiconductor Industry, Analog Circuit Design, VLSI, Physical Verification, EDA, SoC, Debugging, Cadence, Integrated Circuit..., Microprocessors, SRAM, Low-power Design, Timing Closure
Education
Kilgore College 1974 — 1976
AA
Longview High School
LarMon Design Inc. April 2010 - December 2012
Spansion January 1999 - April 2010
Advanced Micro Devices 1985 - 1999
Motorola 1981 - 1985
Texas Instruments (Houston) 1976 - 1981
Skills
Semiconductors, LVS, IC, IC layout, Analog, CMOS, ASIC, DRC, Verilog, Floorplanning, Cadence Virtuoso, Physical Design, Mixed Signal, Circuit Design, Semiconductor Industry, Analog Circuit Design, VLSI, Physical Verification, EDA, SoC, Debugging, Cadence, Integrated Circuit..., Microprocessors, SRAM, Low-power Design, Timing Closure
Education
Kilgore College 1974 — 1976
AA
Longview High School
FerNanda Lentz's LarMon Design Inc Experience 2010 - 2010
Job Mask Designer at AMD
Industry Semiconductors
Experience
AMD September 2011 - Present
Silicon Laboratories July 2010 - September 2011
AMD 2010 - 2010
LarMon Design Inc. 2010 - 2010
Skills
DRC, LVS, Mixed Signal, Floorplanning, Physical Verification, IC, CMOS, Physical Design, PLL, Cadence Virtuoso, Analog
Education
The University of Texas at Austin 1996 — 2000
Business Economics
AMD September 2011 - Present
Silicon Laboratories July 2010 - September 2011
AMD 2010 - 2010
LarMon Design Inc. 2010 - 2010
Skills
DRC, LVS, Mixed Signal, Floorplanning, Physical Verification, IC, CMOS, Physical Design, PLL, Cadence Virtuoso, Analog
Education
The University of Texas at Austin 1996 — 2000
Business Economics
Huan Dinh's LarMon Design Inc Experience April 2010 - June 2013
Job Low Power Circuit Designer –Austin, TX at AMD
Industry Computer Hardware
Experience
AMD June 2013 - July 2015
LarMon Design Inc. April 2010 - June 2013
Spansion November 2005 - March 2009
Skills
IC, LNA, Digital Imaging, VLSI, Cadence Virtuoso, Analog, Amplifiers, Sensors, Perl, Static Timing Analysis, Physical Design, CMOS, Verilog
Education
The University of Texas at San Antonio 2005 — 2008
MS Computer Engineering Fall/2008, Analog and Mixed-Signals. Low Noise Image Sensors, High Resolution Imaging Sensors
AMD June 2013 - July 2015
LarMon Design Inc. April 2010 - June 2013
Spansion November 2005 - March 2009
Skills
IC, LNA, Digital Imaging, VLSI, Cadence Virtuoso, Analog, Amplifiers, Sensors, Perl, Static Timing Analysis, Physical Design, CMOS, Verilog
Education
The University of Texas at San Antonio 2005 — 2008
MS Computer Engineering Fall/2008, Analog and Mixed-Signals. Low Noise Image Sensors, High Resolution Imaging Sensors
Steven Hoholik's LarMon Design Inc Experience August 2011 - August 2012
Job Engineering Scientist Associate at Applied Research Labs
Industry Information Technology and Services
Experience
Applied Research Labs June 2014 - Present
National Instruments December 2012 - June 2014
LarMon Design Inc. August 2011 - August 2012
Guitar Center June 2008 - January 2009
Skills
Mathematics, Cadence Virtuoso, Unix, Calibre, LVS, DRC, Numerical Analysis, Matlab, Powershell, C#, Visual Studio, MSTest, MSBuild, TFS, Virtual Machine Manager, Windows Server, Microsoft Excel, Java, SQL, HTML, Windows, JavaScript, XP, Computer Hardware, Troubleshooting, Red Hat Linux, Perl, C++, Linear Algebra, Linguistics, German, Web Design
Education
The University of Texas at Austin 2007 — 2010
BS, Computational Mathematics
Applied Research Labs June 2014 - Present
National Instruments December 2012 - June 2014
LarMon Design Inc. August 2011 - August 2012
Guitar Center June 2008 - January 2009
Skills
Mathematics, Cadence Virtuoso, Unix, Calibre, LVS, DRC, Numerical Analysis, Matlab, Powershell, C#, Visual Studio, MSTest, MSBuild, TFS, Virtual Machine Manager, Windows Server, Microsoft Excel, Java, SQL, HTML, Windows, JavaScript, XP, Computer Hardware, Troubleshooting, Red Hat Linux, Perl, C++, Linear Algebra, Linguistics, German, Web Design
Education
The University of Texas at Austin 2007 — 2010
BS, Computational Mathematics
Rahul Kalyan's LarMon Design Inc Experience July 2010 - August 2012
Job Physical Design Engineer at Freescale Semiconductor
Industry Semiconductors
Experience
Freescale Semiconductor September 2012 - Present
LarMon Design Inc. July 2010 - August 2012
Skills
Physical Design, Static Timing Analysis, Timing Closure, QRC, Cadence Encounter, Unix Shell Scripting, TCL, GNU Make, Parasitic Extraction, Verilog, Logic Synthesis, Cadence Virtuoso, VHDL, Embedded Systems, C, DRC, Unix, ModelSim, Cadence Skill, VLSI CAD, Matlab, Multisim, TI DSPs, Motorola Assembly, Calibre, Place, Cadence, Microsoft Office, VLSI
Education
The University of Texas at Austin 2006 — 2010
BS, Computer Engineering
Freescale Semiconductor September 2012 - Present
LarMon Design Inc. July 2010 - August 2012
Skills
Physical Design, Static Timing Analysis, Timing Closure, QRC, Cadence Encounter, Unix Shell Scripting, TCL, GNU Make, Parasitic Extraction, Verilog, Logic Synthesis, Cadence Virtuoso, VHDL, Embedded Systems, C, DRC, Unix, ModelSim, Cadence Skill, VLSI CAD, Matlab, Multisim, TI DSPs, Motorola Assembly, Calibre, Place, Cadence, Microsoft Office, VLSI
Education
The University of Texas at Austin 2006 — 2010
BS, Computer Engineering