PerfectVIPs Company
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PerfectVIPs Employees
Employee
Years
Job
Industry
Arth Mehta Arth Mehta's PerfectVIPs Experience February 2013 - August 2013
Job ASIC Verification Engineer
Industry Semiconductors
Experience
Intel Corporation March 2015 - Present
PLX Technology August 2013 - Present
PerfectVIPs February 2013 - August 2013
VeriFast Technologies January 2013 - May 2013
George Mason University September 2011 - December 2012
Skills
SystemVerilog, PCIe, VMM, UVM, VCS, Verdi, Functional Verification, IES Virtual Environment, Simvision, Verilog, VHDL, FPGA, Xilinx, Synopsys tools, C, Perl, Xilinx ISE, Matlab, ASIC, Eclipse, Pspice, Computer Architecture, Microcontrollers, Altera, Simulations, Microprocessors, RTL coding, MIPS, Circuit Design, Computer Arithmetic, Static Timing Analysis, Digital Circuit Design, Assembly Language, Synopsys Primetime, RTL design, Assertion Based..., VLSI, Primetime, PSpice, Debugging, Cadence, Linux, Testing, Programming, SoC
Education
George Mason University 2010 — 2012
Master of Science (M.S.), Computer Engineering
University of Pune 2006 — 2010
B.E., Electronics and Telecommunication Engineering
Intel Corporation March 2015 - Present
PLX Technology August 2013 - Present
PerfectVIPs February 2013 - August 2013
VeriFast Technologies January 2013 - May 2013
George Mason University September 2011 - December 2012
Skills
SystemVerilog, PCIe, VMM, UVM, VCS, Verdi, Functional Verification, IES Virtual Environment, Simvision, Verilog, VHDL, FPGA, Xilinx, Synopsys tools, C, Perl, Xilinx ISE, Matlab, ASIC, Eclipse, Pspice, Computer Architecture, Microcontrollers, Altera, Simulations, Microprocessors, RTL coding, MIPS, Circuit Design, Computer Arithmetic, Static Timing Analysis, Digital Circuit Design, Assembly Language, Synopsys Primetime, RTL design, Assertion Based..., VLSI, Primetime, PSpice, Debugging, Cadence, Linux, Testing, Programming, SoC
Education
George Mason University 2010 — 2012
Master of Science (M.S.), Computer Engineering
University of Pune 2006 — 2010
B.E., Electronics and Telecommunication Engineering
Dipak Gondaliya Dipak Gondaliya's PerfectVIPs Experience December 2013 - Present
Job Verification Consultant at Broadcom
Industry Semiconductors
Experience
Broadcom October 2014 - Present
PerfectVIPs December 2013 - Present
Stealth Mode Startup Company February 2014 - October 2014
eInfochips May 2007 - November 2013
Rockwell Collins January 2011 - January 2013
Skills
RTL verification, Gate Level Simulation, Functional Verification, Open Verification..., Verilog, System Verilog, Unix Shell Scripting, Assertion Based..., Assertions, Code Coverage, functional coverage, DO-254, Tortoise SVN, Peer Reviews, IBM DOORS, ClearQuest, ModelSim, Perl Script, Spyglass, SPI, Debugging, VHDL, I2C, RTL coding, AXI, UVM, PCIe, SystemVerilog
Education
Dharmsinh Desai Institute of Technology 2003 — 2007
B.E., Elecronics and Communication engineering, B
Broadcom October 2014 - Present
PerfectVIPs December 2013 - Present
Stealth Mode Startup Company February 2014 - October 2014
eInfochips May 2007 - November 2013
Rockwell Collins January 2011 - January 2013
Skills
RTL verification, Gate Level Simulation, Functional Verification, Open Verification..., Verilog, System Verilog, Unix Shell Scripting, Assertion Based..., Assertions, Code Coverage, functional coverage, DO-254, Tortoise SVN, Peer Reviews, IBM DOORS, ClearQuest, ModelSim, Perl Script, Spyglass, SPI, Debugging, VHDL, I2C, RTL coding, AXI, UVM, PCIe, SystemVerilog
Education
Dharmsinh Desai Institute of Technology 2003 — 2007
B.E., Elecronics and Communication engineering, B
Khushbu Akabari Khushbu Akabari's PerfectVIPs Experience April 2013 - May 2014
Job Verification Engineer at Sonics, Inc.
Industry Electrical/Electronic Manufacturing
Experience
Sonics, Inc. June 2015 - Present
Quantenna Communications October 2014 - May 2015
VeriFast Technologies May 2014 - October 2014
PerfectVIPs April 2013 - May 2014
VeriFast Technologies January 2013 - May 2013
STEC, Inc. May 2012 - August 2012
Skills
Verilog, VLSI, VHDL, FPGA, Matlab, SystemVerilog, Functional Verification, Perl, Debugging, Xilinx ISE, Linux, ASIC, UVM, PCIe, C++, Perl Script, System Verilog, C/C++, Spartan 3, Riviera-PRO, ModelSim, AXI, Verdi, Python, Agile Methodologies, Assertions
Education
California State University-Fullerton 2010 — 2013
Master's degree, Electrical, Electronics and Communications Engineering
California State University-Fullerton 2010 — 2013
Master's degree, Electrical and Electronics Engineering
Sonics, Inc. June 2015 - Present
Quantenna Communications October 2014 - May 2015
VeriFast Technologies May 2014 - October 2014
PerfectVIPs April 2013 - May 2014
VeriFast Technologies January 2013 - May 2013
STEC, Inc. May 2012 - August 2012
Skills
Verilog, VLSI, VHDL, FPGA, Matlab, SystemVerilog, Functional Verification, Perl, Debugging, Xilinx ISE, Linux, ASIC, UVM, PCIe, C++, Perl Script, System Verilog, C/C++, Spartan 3, Riviera-PRO, ModelSim, AXI, Verdi, Python, Agile Methodologies, Assertions
Education
California State University-Fullerton 2010 — 2013
Master's degree, Electrical, Electronics and Communications Engineering
California State University-Fullerton 2010 — 2013
Master's degree, Electrical and Electronics Engineering
Naynesh Shah's PerfectVIPs Experience August 2012 - August 2013
Job Lead Customer engagement engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems November 2014 - Present
Qualcomm September 2013 - October 2014
PerfectVIPs August 2012 - August 2013
California State University, Northridge August 2010 - May 2012
Mtech Innovations Ltd December 2007 - December 2009
Nital computers June 2006 - June 2007
Skills
Verilog, ModelSim, FPGA, VHDL, ASIC, Xilinx, Embedded Systems, SystemVerilog, Microcontrollers, Perl, Orcad, PCB design, RTL design, Altera Quartus, Matlab, Embedded C, VLSI, C, Hardware, Xilinx ISE, Simulations, Functional Verification, Firmware, Linux, I2C, Oscilloscope, C++, RTL coding, Pspice, Signal Generators, Labview, ARM, Windows, MIPS, Assembly Language, Embedded Software, USB, Logic Analyzer, CRO, SPARTAN 3E, Virtex 4.0, Troubleshooting..., Mac OS, TCP/IP, RS232, USB 2.0, Logic Synthesis, UNIX, UVM, Debugging
Education
California State University-Northridge 2010 — 2012
M.S, Electrical Engineering specialised in field of Digital and Computer Engineering
University of Pune 2003 — 2007
B.E, Elecronics and Telecommunication
SVCP 2000 — 2003
Diploma, Industrial Electronics
Cadence Design Systems November 2014 - Present
Qualcomm September 2013 - October 2014
PerfectVIPs August 2012 - August 2013
California State University, Northridge August 2010 - May 2012
Mtech Innovations Ltd December 2007 - December 2009
Nital computers June 2006 - June 2007
Skills
Verilog, ModelSim, FPGA, VHDL, ASIC, Xilinx, Embedded Systems, SystemVerilog, Microcontrollers, Perl, Orcad, PCB design, RTL design, Altera Quartus, Matlab, Embedded C, VLSI, C, Hardware, Xilinx ISE, Simulations, Functional Verification, Firmware, Linux, I2C, Oscilloscope, C++, RTL coding, Pspice, Signal Generators, Labview, ARM, Windows, MIPS, Assembly Language, Embedded Software, USB, Logic Analyzer, CRO, SPARTAN 3E, Virtex 4.0, Troubleshooting..., Mac OS, TCP/IP, RS232, USB 2.0, Logic Synthesis, UNIX, UVM, Debugging
Education
California State University-Northridge 2010 — 2012
M.S, Electrical Engineering specialised in field of Digital and Computer Engineering
University of Pune 2003 — 2007
B.E, Elecronics and Telecommunication
SVCP 2000 — 2003
Diploma, Industrial Electronics
Vivek Rathi Vivek Rathi's PerfectVIPs Experience March 2013 - August 2013
Job ASIC Verification Engineer at Quantenna Communications
Industry Computer Hardware
Experience
Quantenna Communications August 2013 - Present
PerfectVIPs March 2013 - August 2013
VeriFast Technologies January 2013 - August 2013
Marvin Center,George Washington University March 2011 - December 2012
George Washington University January 2012 - August 2012
Skills
Python, Verilog, Cadence Virtuoso, Cadence Virtuoso Layout..., Cadence Spectre, Cadence, Agilent ADS, Sonnet, Amazon Web Services..., Computer Architecture, Tutoring, System Verilog, Embedded Systems, RTL design, RTL verification, Objective-C, Xcode, Cloud Computing, Aldec, Perl, ASIC, SystemVerilog, PCIe, Logic Design, VLSI, VHDL, RTL Design, UVM
Education
Udacity.com 2012 — 2016
Online Learning, Computer Science
The George Washington University 2011 — 2013
MS, Computer Engineering, 3.45
Pune University 2005 — 2009
BS, Electronics Engineering
Quantenna Communications August 2013 - Present
PerfectVIPs March 2013 - August 2013
VeriFast Technologies January 2013 - August 2013
Marvin Center,George Washington University March 2011 - December 2012
George Washington University January 2012 - August 2012
Skills
Python, Verilog, Cadence Virtuoso, Cadence Virtuoso Layout..., Cadence Spectre, Cadence, Agilent ADS, Sonnet, Amazon Web Services..., Computer Architecture, Tutoring, System Verilog, Embedded Systems, RTL design, RTL verification, Objective-C, Xcode, Cloud Computing, Aldec, Perl, ASIC, SystemVerilog, PCIe, Logic Design, VLSI, VHDL, RTL Design, UVM
Education
Udacity.com 2012 — 2016
Online Learning, Computer Science
The George Washington University 2011 — 2013
MS, Computer Engineering, 3.45
Pune University 2005 — 2009
BS, Electronics Engineering
dhairya bapodra dhairya bapodra's PerfectVIPs Experience December 2014 - Present
Job Consultant at Barefoot Networks
Industry Semiconductors
Experience
Barefoot Networks March 2015 - Present
PerfectVIPs December 2014 - Present
Mirafra Technologies January 2013 - November 2014
Cisco Systems January 2012 - November 2014
Mirafra Technologies January 2012 - December 2012
Uniquify Inc September 2010 - November 2011
Sibridge Technologies December 2009 - November 2010
DAIICT 2007 - 2009
Sarvajanic college of engineering and technology March 2007 - June 2007
Skills
Verilog, SystemVerilog, Logic Design, RTL design, USB, DDR, I2C, Digital Electronics, Perl, UVM, RTL coding, ASIC, RTL verification, SoC, FPGA, Debugging, Xilinx, Embedded Linux, Open Verification..., Functional Verification, AMBA AHB, SOC verification, PCIe
Education
DAIICT 2007 — 2009
M.Tech, ICT-VLSI-major, 7.44/10
South Gujarat University 2002 — 2006
BE, EC, Frist Division
Barefoot Networks March 2015 - Present
PerfectVIPs December 2014 - Present
Mirafra Technologies January 2013 - November 2014
Cisco Systems January 2012 - November 2014
Mirafra Technologies January 2012 - December 2012
Uniquify Inc September 2010 - November 2011
Sibridge Technologies December 2009 - November 2010
DAIICT 2007 - 2009
Sarvajanic college of engineering and technology March 2007 - June 2007
Skills
Verilog, SystemVerilog, Logic Design, RTL design, USB, DDR, I2C, Digital Electronics, Perl, UVM, RTL coding, ASIC, RTL verification, SoC, FPGA, Debugging, Xilinx, Embedded Linux, Open Verification..., Functional Verification, AMBA AHB, SOC verification, PCIe
Education
DAIICT 2007 — 2009
M.Tech, ICT-VLSI-major, 7.44/10
South Gujarat University 2002 — 2006
BE, EC, Frist Division
Rakesh Gohil Rakesh Gohil's PerfectVIPs Experience October 2011 - April 2012
Job Pre Silicon Verification/Validation Engineer at Intel Corporation
Industry Semiconductors
Experience
Intel Corporation January 2015 - Present
LSI Corporation April 2012 - January 2015
PerfectVIPs October 2011 - April 2012
Skills
Verilog, FPGA, VHDL, VLSI, ASIC, ModelSim, Xilinx, Simulink, RTL design, DFT, Hardware, Perl, Microprocessors, C++, SystemVerilog, Electronics, VCS, Linux, Unix, Semiconductors, Circuit Design, Computer Architecture, C, Debugging, Primetime, Functional Verification, NCSim, UVM, Veritas Cluster Server, Testing, Static Timing Analysis, Formal Verification, IC, Logic Design, Integrated Circuit..., AMBA AHB, Hardware Architecture, EDA, TCL, Open Verification..., SoC, Synopsys tools, RTL Design
Education
California State University-Northridge 2008 — 2011
Master of Science, Electrical Engineer
Maharaja Sayajirao University, Vadodara, Gujarat 2003 — 2007
B.E, Electronics Engineering
Intel Corporation January 2015 - Present
LSI Corporation April 2012 - January 2015
PerfectVIPs October 2011 - April 2012
Skills
Verilog, FPGA, VHDL, VLSI, ASIC, ModelSim, Xilinx, Simulink, RTL design, DFT, Hardware, Perl, Microprocessors, C++, SystemVerilog, Electronics, VCS, Linux, Unix, Semiconductors, Circuit Design, Computer Architecture, C, Debugging, Primetime, Functional Verification, NCSim, UVM, Veritas Cluster Server, Testing, Static Timing Analysis, Formal Verification, IC, Logic Design, Integrated Circuit..., AMBA AHB, Hardware Architecture, EDA, TCL, Open Verification..., SoC, Synopsys tools, RTL Design
Education
California State University-Northridge 2008 — 2011
Master of Science, Electrical Engineer
Maharaja Sayajirao University, Vadodara, Gujarat 2003 — 2007
B.E, Electronics Engineering
PINKALKUMAR PATEL PINKALKUMAR PATEL's PerfectVIPs Experience December 2011 - June 2012
Job Hardware Engineer at Cisco Systems
Industry Semiconductors
Experience
Cisco Systems June 2012 - Present
PerfectVIPs December 2011 - June 2012
Keyu Tech February 2011 - November 2011
Reliance Globalcom June 2007 - July 2008
Varaha Systems December 2006 - May 2007
Skills
SystemVerilog, Verilog, ModelSim, ASIC, VLSI, RTL design, PCI-Express
Education
San Jose State University 2008 — 2011
MS
Dharmsinh Desai Institute of Technology 2004 — 2007
BE
Cisco Systems June 2012 - Present
PerfectVIPs December 2011 - June 2012
Keyu Tech February 2011 - November 2011
Reliance Globalcom June 2007 - July 2008
Varaha Systems December 2006 - May 2007
Skills
SystemVerilog, Verilog, ModelSim, ASIC, VLSI, RTL design, PCI-Express
Education
San Jose State University 2008 — 2011
MS
Dharmsinh Desai Institute of Technology 2004 — 2007
BE
Mickey Singh's PerfectVIPs Experience July 2012 - December 2012
Job Design Engineer at Freescale Semiconductor
Industry Computer Hardware
Experience
Freescale Semiconductor January 2013 - Present
PerfectVIPs July 2012 - December 2012
Synopsys Inc September 2011 - September 2011
CSUN August 2010 - December 2010
NetMax Technologies January 2009 - December 2009
Skills
Verilog, VHDL, Orcad, Pspice, Xilinx ISE, C, C++, Perl, Simulink, Simvision, ModelSim, FPGA, ASIC, SATA 3.0, PCIe 3.0, Onfi, SystemVerilog, DFT Compiler, IC Compiler, Design Compiler, VCS, Primetime, VLSI, Functional Verification, RTL design, Debugging, Computer Engineering, Veritas Cluster Server, Formal Verification, PCIe
Education
California State University 2010 — 2011
MS, Electrical Engineering
Punjab Technical University 2004 — 2008
B.Tech, Electronics & Communication Engineering
Freescale Semiconductor January 2013 - Present
PerfectVIPs July 2012 - December 2012
Synopsys Inc September 2011 - September 2011
CSUN August 2010 - December 2010
NetMax Technologies January 2009 - December 2009
Skills
Verilog, VHDL, Orcad, Pspice, Xilinx ISE, C, C++, Perl, Simulink, Simvision, ModelSim, FPGA, ASIC, SATA 3.0, PCIe 3.0, Onfi, SystemVerilog, DFT Compiler, IC Compiler, Design Compiler, VCS, Primetime, VLSI, Functional Verification, RTL design, Debugging, Computer Engineering, Veritas Cluster Server, Formal Verification, PCIe
Education
California State University 2010 — 2011
MS, Electrical Engineering
Punjab Technical University 2004 — 2008
B.Tech, Electronics & Communication Engineering
Lakshman Prasad Vasam Lakshman Prasad Vasam's PerfectVIPs Experience July 2012 - August 2012
Job IP Verification Engineer at Intel Corporation
Industry Semiconductors
Experience
Intel Corporation August 2012 - Present
PerfectVIPs July 2012 - August 2012
Motorola Solutions January 2012 - June 2012
Skills
Cadence Virtuoso, Matlab, Cadence Schematic, Saber, MS Office Suite, C, Perl, Embedded C, Verilog, VHDL, Keil, Multisim, Synopsys, Mac OS X, Windows, Unix, ClearQuest, IBM Test Central, Cadence, ASIC, Test Automation, Pspice, ModelSim, Xilinx, VLSI, Integrated Circuit..., Microprocessors, Linux, Circuit Design, Microcontrollers, Simulink, Microsoft Office, Testing, FPGA
Education
Wright State University 2009 — 2011
Master's, Electrical Engineering
Kakatiya University 2004 — 2008
Bachelor of Science, Electronics & Instrumentation
Intel Corporation August 2012 - Present
PerfectVIPs July 2012 - August 2012
Motorola Solutions January 2012 - June 2012
Skills
Cadence Virtuoso, Matlab, Cadence Schematic, Saber, MS Office Suite, C, Perl, Embedded C, Verilog, VHDL, Keil, Multisim, Synopsys, Mac OS X, Windows, Unix, ClearQuest, IBM Test Central, Cadence, ASIC, Test Automation, Pspice, ModelSim, Xilinx, VLSI, Integrated Circuit..., Microprocessors, Linux, Circuit Design, Microcontrollers, Simulink, Microsoft Office, Testing, FPGA
Education
Wright State University 2009 — 2011
Master's, Electrical Engineering
Kakatiya University 2004 — 2008
Bachelor of Science, Electronics & Instrumentation
Raman Karamian's PerfectVIPs Experience 2012 - 2012
Job Senior Verification Engineer at Qualcomm
Industry Consumer Electronics
Experience
Qualcomm March 2012 - March 2013
PerfectVIPs 2012 - 2012
Intel Corporation December 2007 - April 2011
Intel Corporation January 2005 - December 2006
Intel Corporation July 1999 - January 2005
Intel Corporation April 1997 - July 1999
Intel Corporation June 1996 - April 1997
Skills
SystemVerilog, ModelSim, Verilog, Debugging, VLSI, Integrated Circuit..., Perl, Digital Signal..., Semiconductors, IC, DFT, Hardware Architecture, Testing, Simulations, ASIC, VHDL, Microcontrollers, Mixed Signal, Functional Verification, C, Embedded Systems, Microprocessors, Static Timing Analysis
Education
UC Davis 1993 — 1997
Bachelor's degree, Electrical and Electronics Engineering
Chabot College
Washington High
Qualcomm March 2012 - March 2013
PerfectVIPs 2012 - 2012
Intel Corporation December 2007 - April 2011
Intel Corporation January 2005 - December 2006
Intel Corporation July 1999 - January 2005
Intel Corporation April 1997 - July 1999
Intel Corporation June 1996 - April 1997
Skills
SystemVerilog, ModelSim, Verilog, Debugging, VLSI, Integrated Circuit..., Perl, Digital Signal..., Semiconductors, IC, DFT, Hardware Architecture, Testing, Simulations, ASIC, VHDL, Microcontrollers, Mixed Signal, Functional Verification, C, Embedded Systems, Microprocessors, Static Timing Analysis
Education
UC Davis 1993 — 1997
Bachelor's degree, Electrical and Electronics Engineering
Chabot College
Washington High
Kartiki Parekh's PerfectVIPs Experience March 2013 - Present
Job ASIC Verification Engineers Please Get in Touch!
Industry Semiconductors
Experience
PerfectVIPs March 2013 - Present
Parekh Household January 2005 - Present
Kumon October 2012 - March 2013
Your Kids 'R' Our Kids August 2009 - July 2010
Kangaroo Kids Education Limited June 2000 - January 2005
Skills
ASIC, AMBA AHB, Interviews, PCIe, Talent Acquisition, Sourcing, Screening Resumes, Human Resources, Temporary Placement
Education
The Maharaja Sayajirao University of Baroda 1997 — 2002
Master's degree
The Maharaja Sayajirao University of Baroda 1997 — 2000
Bachelor's degree
PerfectVIPs March 2013 - Present
Parekh Household January 2005 - Present
Kumon October 2012 - March 2013
Your Kids 'R' Our Kids August 2009 - July 2010
Kangaroo Kids Education Limited June 2000 - January 2005
Skills
ASIC, AMBA AHB, Interviews, PCIe, Talent Acquisition, Sourcing, Screening Resumes, Human Resources, Temporary Placement
Education
The Maharaja Sayajirao University of Baroda 1997 — 2002
Master's degree
The Maharaja Sayajirao University of Baroda 1997 — 2000
Bachelor's degree
Samvit Bharti's PerfectVIPs Experience August 2010 - Present
Job ASIC Verification Lead at PerfectVIPs
Industry Computer Hardware
Experience
PerfectVIPs August 2010 - Present
California State University, Sacramento January 2008 - January 2010
California State University, Sacramento September 2008 - May 2009
Reliance Communications July 2006 - July 2007
Reliance Communications January 2006 - May 2006
Skills
SystemVerilog, Verilog, Xilinx ISE, Synopsys tools, ModelSim, Perl, VHDL, TCL, L-Edit, Primetime, VLSI, RTL coding, C, Xilinx, PCIe, USB3.0, USB, Cadence, Logic Design, RTL Coding, FPGA, Logic Analyzer, Computer Architecture, ASIC, DFT
Education
California State University-Sacramento 2007 — 2010
MS, Electrical and Electronic Engineering, GPA: 3.9
Hemchandracharya North Gujarat University 2002 — 2006
BS, Electronics & Communications, GPA: 3.9
PerfectVIPs August 2010 - Present
California State University, Sacramento January 2008 - January 2010
California State University, Sacramento September 2008 - May 2009
Reliance Communications July 2006 - July 2007
Reliance Communications January 2006 - May 2006
Skills
SystemVerilog, Verilog, Xilinx ISE, Synopsys tools, ModelSim, Perl, VHDL, TCL, L-Edit, Primetime, VLSI, RTL coding, C, Xilinx, PCIe, USB3.0, USB, Cadence, Logic Design, RTL Coding, FPGA, Logic Analyzer, Computer Architecture, ASIC, DFT
Education
California State University-Sacramento 2007 — 2010
MS, Electrical and Electronic Engineering, GPA: 3.9
Hemchandracharya North Gujarat University 2002 — 2006
BS, Electronics & Communications, GPA: 3.9
Suresh Etikala's PerfectVIPs Experience July 2014 - Present
Job ASIC Verification Engineer
Industry Semiconductors
Experience
PerfectVIPs July 2014 - Present
Contractor @ NXP July 2013 - July 2014
Contractor @ ST Microelectronics October 2012 - June 2013
PMC-Sierra January 2012 - October 2012
Cypress Semiconductor May 2010 - January 2012
Wipro Technologies August 2008 - April 2010
Wipro Technologies July 2006 - August 2008
Skills
UVM, SystemVerilog, OVM, erm, Specman, APB, AMBA AHB, AXI, I2C, Open Verification..., Semiconductors, RTL design
Education
Manipal Institute of Technology 2009 — 2011
MS, VLSI - CAD
Jawaharlal Nehru Technological University 2002 — 2006
B.tech, ECE
Govt Polytechnic, Warangal,AP 1998 — 2001
DECE
PerfectVIPs July 2014 - Present
Contractor @ NXP July 2013 - July 2014
Contractor @ ST Microelectronics October 2012 - June 2013
PMC-Sierra January 2012 - October 2012
Cypress Semiconductor May 2010 - January 2012
Wipro Technologies August 2008 - April 2010
Wipro Technologies July 2006 - August 2008
Skills
UVM, SystemVerilog, OVM, erm, Specman, APB, AMBA AHB, AXI, I2C, Open Verification..., Semiconductors, RTL design
Education
Manipal Institute of Technology 2009 — 2011
MS, VLSI - CAD
Jawaharlal Nehru Technological University 2002 — 2006
B.tech, ECE
Govt Polytechnic, Warangal,AP 1998 — 2001
DECE