Samsung Austin R&D Center (SARC)
Address: 3900 N Capital of Texas Hwy, Austin, TX 78746 Hours: Closed ⋅ Opens 8AM Thursday8AM–6PMFriday8AM–6PMSaturdayClosedSundayClosedMonday8AM–6PMTuesday8AM–6PMWednesday8AM–6PMSuggest an edit Unable to add this file. Please check that it is a valid photo. Phone: (512) 425-2500Place name: : Category: : : : Website: : : Website: http://www.samsung.com/us/careers/ Category: Research and product development Suggest an editUnable to add this file. Please check that it is a valid photo. Unable to add this file. Please check that it is a valid photo. Questions & answers Ask a questionBe the first to ask a questionPopular times Thursdays MondaysTuesdaysWednesdaysThursdaysFridaysSaturdaysSundaysBased on visits to this place. : 6a9a12p3p6p9p12a3a6a9a12p3p6p9p12a3a6aPlan your visitClosed Sundays—pick another dayClosed Saturdays—pick another dayHistogram showing popular times on MondaysHistogram showing popular times on TuesdaysHistogram showing popular times on WednesdaysHistogram showing popular times on ThursdaysHistogram showing popular times on FridaysPeople typically spend 1.5-5.5 hours here Add a photoThanks for sharing!Your photo will be posted publicly on Google.Contribute MoreDoneUpload public photos of Samsung SARC Posting publicly on the Web Write a review Reviews"Good place to work :)" "I install the cubicle Furniture and they all are some Great People." "No help in fixing my Samsung galaxy note 4!!" View all Google reviews
Samsung Austin R&D Center (SARC) List of Employees There's an exhaustive list of past and present employees! Get comprehensive information on the number of employees at Samsung Austin R&D Center (SARC). You can filter them based on skills, years of employment, job, education, department, and prior employment.
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Samsung Austin R&D Center (SARC) Employees
Sagar Bhogela Samsung Austin R&D Center (SARC) May 2015 - Present
Qualcomm June 2011 - June 2014
Qualcomm May 2010 - July 2010
Skills
Verilog, Matlab, C, SoC, RTL design, VHDL, Linux, Microprocessors, JTAG, ASIC, Programming, Simulations, TCL
Education
Texas A&M University 2014 — 2016
Master's Degree, Electrical and Computer Engineering, 3.8/4.0
Indian Institute of Technology, Kharagpur 2007 — 2011
Bachelor of Technology, Electronics and Electrical Communication, 8.64/10
Samsung Austin R&D Center (SARC) March 2015 - Present
Samsung Austin R&D Center (SARC) March 2015 - Present
AMD September 2011 - March 2015
AMD November 2005 - August 2009
Hewlett-Packard May 2003 - October 2005
Hewlett-Packard May 1997 - April 2003
United Space Alliance February 1993 - April 1997
United Space Alliance September 1983 - January 1993
Skills
RTL design, Semiconductors, DFT, FPGA, Windows, CPLD, Board Development, Power Electronics, C++ Language, Java, Verilog, VHDL, x86 Assembly, 68k Assembly, 8051 Microcontroller, ARM, AMBA, ACPI, Bios, UEFI, Linux, VxW, Interrupts, SAS, SATA, PCIe, X86, VMEbus, PCI Standards, SCSI, ISA, I2C, USB, TCP/IP, Real Time, Cache Coherency, HyperTransport, FSB, DDR3, SMP, Logic Analyzer, Oscilloscope, Protocol Analysis, Analog Circuit Design, Digital Designs, Signal Integrity, Project Engineering, Orcad, Viewlogic, Allegro
Education
University of Houston-Clear Lake 2001 — 2005
Bachelor of Science (BS), Computer Engineering, Graduated Summa Cum Laude 3.98 GPA
San Jacinto College 1997 — 2001
General Studies, Pre Engineering, GPA 3.95
Karthik Prabhu Tamilarasan Samsung Austin R&D Center (SARC) May 2013 - Present
Freescale Semiconductor January 2011 - April 2013
Freescale Semiconductor September 2010 - December 2010
Skills
Functional Verification, Verilog, System Verilog, Perl, C, PowerPC, C++, SystemVerilog
Education
Texas A&M University, College Station 2008 — 2010
MASTER OF SCIENCE, Electrical and Computer Engineering
Anna University 2004 — 2008
Bachelor of Engineering, Electronics and Communication Engineering
Neil Panchal Apple 2012 - Present
Samsung Austin R&D Center (SARC) 2010 - 2012
IBM Corporation 2003 - 2010
Skills
SoC, ASIC, Logic Design, Physical Design, Clock Tree Synthesis, Constraint Development, Timing Closure, Static Timing Analysis, Synopsys Design Compiler, Synopsys ICC, Synopsys STAR-RC, Synopsys Primetime, IBM Booledozer, IBM ChipBench, IBM EinsTimer, IBM ChipEdit, IBM Verity, Cadence First Encounter, Cadence LEC, TCL, Verilog, DDR2, VLSI, Synopsys tools, Low-power Design, RTL design, Floorplanning, Place & Route, Debugging, Integrated Circuit..., Signal Integrity
Education
The University of Texas at Austin 2000 — 2002
MSEE, Electrical / Computer Engineering
The University of Texas at Austin 1997 — 2000
BSEE, Electrical / Computer Engineering
Samsung Austin R&D Center (SARC) January 2014 - Present
Samsung Austin R&D Center (SARC) January 2011 - December 2013
Samsung Austin R&D Center (SARC) August 2010 - December 2010
Intel March 2006 - August 2010
Intel October 2000 - March 2006
Motorola, Inc. 1992 - 2000
Electronics Corporation of India Ltd (ECIL) April 1989 - July 1989
Skills
Processors, Microprocessors, Semiconductors, IC, Verilog, Embedded Systems, Engineering Management, Perl, Product Management, Program Management, SoC, Engineering, Cross-functional Team..., Architecture, ASIC
Education
The University of Texas at Austin - The Red McCombs School of Business 2006 — 2008
Executive M.B.A, General Management
University of South Carolina-Columbia 1991 — 1992
M.S, Electrical & Computer Engineering
Osmania University 1986 — 1990
B.E, Electronics and Communication
Apple 2014 - Present
Samsung Austin R&D Center (SARC) 2010 - 2014
Marvell Semiconductors Inc. 2006 - 2010
Intel 2001 - 2006
Education
The University of Texas at Austin 2005 — 2013
Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering
University of Minnesota-Twin Cities 1999 — 2001
MSEE, Electrical and Computer Engineering
Korea University 1993 — 1999
B.E., Electrical Engineering
Samsung Austin R&D Center (SARC) November 2014 - Present
Samsung Austin R&D Center (SARC) April 2013 - Present
AMD July 2004 - April 2013
Sun Microsystems July 2000 - July 2004
Cadence Design Systems May 1999 - September 1999
Skills
Logic Design, TCL, Perl, Static Timing Analysis, Timing, Circuit Design, Integration, Layout, Physical Design, Physical Verification, CMOS, Primetime, Low Power Design, SRAM, LVS, Synopsys DC/ICC, SPICE, AMPLE (Mentor), EinsTlt, EinsTimer, Cadence Virtuoso, VLSI, Timing Closure, Synopsys tools, Cadence Skill, AMPLE, Logic Synthesis, Low-power Design, Microprocessors, Verilog, SoC, Cadence, Place & Route
Education
Carnegie Mellon University 1996 — 2000
NVIDIA April 2015 - Present
Department of Computer Science and Engineering at Texas A&M University August 2010 - May 2015
National Center for Toxicological Research, FDA May 2014 - August 2014
Samsung Austin R&D Center (SARC) May 2013 - August 2013
LG Electronics June 2011 - July 2011
Korea University August 2009 - December 2009
Samsung Electronics August 2007 - June 2009
R.O.K. Army March 2003 - June 2005
Skills
Algorithms, C++, Machine Learning, Linux, C, Data Mining, Computer Science, Matlab, Programming language:..., Embedded Systems, Java, Simulations, Computer Vision, Script: Matlab,..., Database : Mysql, Leadership: platoon..., Python, Signal Processing, Data Visualization, JavaScript, Hadoop, Mahout, Kibana, ElasticSearch
Education
Texas A&M University 2010 — 2015
Doctor of Philosophy (Ph.D.), Computer Science
Korea University 2005 — 2007
M.S., Electronics and Computer Engineering
Korea University 1999 — 2003
B.S., Electrical Engineering