Smartplay Inc
Description
Address: 1550 Bridgeboro Rd, Edgewater Park, NJ 08010 Hours: Closed ⋅ Opens 8AM Tue Monday8AM–5PMTuesday8AM–5PMWednesday8AM–5PMThursday8AM–5PMFriday8AM–5PMSaturdayClosedSundayClosedSuggest an edit Unable to add this file. Please check that it is a valid photo. Phone: (609) 880-1860Place name: : : Website: : : : Category: : Website: http://www.smartplay.com/ Category: Manufacturer Suggest an editUnable to add this file. Please check that it is a valid photo. Unable to add this file. Please check that it is a valid photo. Questions & answers Ask a questionBe the first to ask a question Add a photoThanks for sharing!Your photo will be posted publicly on Google.Contribute MoreDoneUpload public photos of Smartplay International Inc Posting publicly on the Web Write a review Reviews 2 Google reviews
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Smartplay Inc Employees
Employee
Years
Job
Industry
Balamurugan Muthaiah Balamurugan Muthaiah's Smartplay Inc Experience July 2012 - December 2013
Job Senior Verification Engineer at QuickLogic
Industry Semiconductors
Experience
QuickLogic December 2013 - Present
Smartplay Inc July 2012 - December 2013
Smartplay Technologies July 2010 - July 2012
Flowgic India Pvt Ltd June 2007 - July 2010
Skills
AHB, I2C, UART, SPI, JTAG, I2S, DDR3, SystemVerilog, SoC, FPGA, RTL design, NCSim, Functional Verification, Verilog, ModelSim, ASIC, VHDL, VLSI, VCS, RTL coding, AMBA AHB, Processors, Altera, UVM, Perl, C, ARM
Education
Sandeepani School of VLSI Design 2006 — 2007
PG Diploma, VLSI Design (Mentor Graphics Certification)
Anna University 2002 — 2006
BE, Electronics and Communication Engineering
QuickLogic December 2013 - Present
Smartplay Inc July 2012 - December 2013
Smartplay Technologies July 2010 - July 2012
Flowgic India Pvt Ltd June 2007 - July 2010
Skills
AHB, I2C, UART, SPI, JTAG, I2S, DDR3, SystemVerilog, SoC, FPGA, RTL design, NCSim, Functional Verification, Verilog, ModelSim, ASIC, VHDL, VLSI, VCS, RTL coding, AMBA AHB, Processors, Altera, UVM, Perl, C, ARM
Education
Sandeepani School of VLSI Design 2006 — 2007
PG Diploma, VLSI Design (Mentor Graphics Certification)
Anna University 2002 — 2006
BE, Electronics and Communication Engineering
Guruvaiah Repakula Guruvaiah Repakula's Smartplay Inc Experience May 2012 - October 2014
Job Staff Engineer at Qualcomm
Industry Semiconductors
Experience
Qualcomm October 2014 - Present
Smartplay Inc May 2012 - October 2014
Smartplay Technologies Private Limited March 2009 - May 2012
MindTree Ltd December 2007 - February 2009
Wipro July 2005 - November 2007
Skills
Physical Design, Timing Closure, Logic Synthesis, RTL design, SoC, VLSI, Formal Verification, Verilog, SystemVerilog, EDA, TCL, ASIC, Static Timing Analysis, DRC, Functional Verification, LVS, Floorplanning, Physical Verification, Clock Tree Synthesis
Education
Sri Venkateswara University 2001 — 2005
B.Tech, Electronics & Communication Engineering
Qualcomm October 2014 - Present
Smartplay Inc May 2012 - October 2014
Smartplay Technologies Private Limited March 2009 - May 2012
MindTree Ltd December 2007 - February 2009
Wipro July 2005 - November 2007
Skills
Physical Design, Timing Closure, Logic Synthesis, RTL design, SoC, VLSI, Formal Verification, Verilog, SystemVerilog, EDA, TCL, ASIC, Static Timing Analysis, DRC, Functional Verification, LVS, Floorplanning, Physical Verification, Clock Tree Synthesis
Education
Sri Venkateswara University 2001 — 2005
B.Tech, Electronics & Communication Engineering
Arpit Seksaria Arpit Seksaria's Smartplay Inc Experience March 2013 - March 2015
Job Staff Engineer at Qualcomm
Industry Electrical/Electronic Manufacturing
Experience
Qualcomm March 2015 - Present
Smartplay Inc March 2013 - March 2015
Mirafra Technologies October 2011 - March 2013
Vitesse Semiconductors July 2006 - October 2011
Skills
SystemVerilog, Functional Verification, Verilog, VLSI, ASIC, Logic Analyzer, TCL, Semiconductors, Ethernet, Perl, SoC, RTL design, Open Verification..., Debugging, RTL Design, FPGA
Education
International Institute of Information Technology 2004 — 2006
M Tech, VLSI Engineering
Nagarjuna University 2000 — 2004
B Tech, Electronics & Communication Engg.
Vignan Vidyalayas 1998 — 2000
Intermediate, MPC
Qualcomm March 2015 - Present
Smartplay Inc March 2013 - March 2015
Mirafra Technologies October 2011 - March 2013
Vitesse Semiconductors July 2006 - October 2011
Skills
SystemVerilog, Functional Verification, Verilog, VLSI, ASIC, Logic Analyzer, TCL, Semiconductors, Ethernet, Perl, SoC, RTL design, Open Verification..., Debugging, RTL Design, FPGA
Education
International Institute of Information Technology 2004 — 2006
M Tech, VLSI Engineering
Nagarjuna University 2000 — 2004
B Tech, Electronics & Communication Engg.
Vignan Vidyalayas 1998 — 2000
Intermediate, MPC
Puneet Malhotra Puneet Malhotra's Smartplay Inc Experience July 2015 - Present
Job Lead Engineer at Smartplay, Inc.
Industry Semiconductors
Experience
SmartPlay inc. July 2015 - Present
SmartPlay Technologies December 2012 - July 2015
Synapse Design Automation Inc. May 2011 - November 2012
NetLogic Microsystems( Now part of Broadcom India Pvt Ltd) May 2005 - April 2011
Skills
Physical Design, Static Timing Analysis, VLSI, Timing Closure, Floorplanning, Physical Verification, DRC, LVS, ASIC, SoC, Primetime, Timing
Education
Sandeepani 2005 — 2005
post graduate diploma, VLSI
Kurukshetra University 2000 — 2004
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
SmartPlay inc. July 2015 - Present
SmartPlay Technologies December 2012 - July 2015
Synapse Design Automation Inc. May 2011 - November 2012
NetLogic Microsystems( Now part of Broadcom India Pvt Ltd) May 2005 - April 2011
Skills
Physical Design, Static Timing Analysis, VLSI, Timing Closure, Floorplanning, Physical Verification, DRC, LVS, ASIC, SoC, Primetime, Timing
Education
Sandeepani 2005 — 2005
post graduate diploma, VLSI
Kurukshetra University 2000 — 2004
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
Shivaji Pawar Shivaji Pawar's Smartplay Inc Experience October 2013 - Present
Job ASIC Physical Design Engineer at SmartPlay Inc.
Industry Semiconductors
Experience
SmartPlay Inc. October 2013 - Present
SmartPlay India July 2012 - October 2013
LSI Corporation August 2010 - July 2012
Skills
Physical Design, Timing Closure, DRC, LVS, Primetime, TCL, Physical Verification, Floorplanning, Clock Tree Synthesis, Formal Verification, IR drop analysis, ASIC, Logic Synthesis, Low Power Design, Flow automation, Synthesis, IC Compiler, Unix Shell Scripting, Backend Development, Prime Rail, CustomDesigner, PrimeRail, IC Validator, Calibre, Waveform Editor, IC Work Bench, IC Compiler 2, Test chip implementation, PNR, Shell Scripting
Education
College of Engineering Pune 2006 — 2010
Bachelor of Technology (B.Tech.), Electronics and Telecommunications
SmartPlay Inc. October 2013 - Present
SmartPlay India July 2012 - October 2013
LSI Corporation August 2010 - July 2012
Skills
Physical Design, Timing Closure, DRC, LVS, Primetime, TCL, Physical Verification, Floorplanning, Clock Tree Synthesis, Formal Verification, IR drop analysis, ASIC, Logic Synthesis, Low Power Design, Flow automation, Synthesis, IC Compiler, Unix Shell Scripting, Backend Development, Prime Rail, CustomDesigner, PrimeRail, IC Validator, Calibre, Waveform Editor, IC Work Bench, IC Compiler 2, Test chip implementation, PNR, Shell Scripting
Education
College of Engineering Pune 2006 — 2010
Bachelor of Technology (B.Tech.), Electronics and Telecommunications
Harsha Vardhan Airpula's Smartplay Inc Experience March 2012 - Present
Job Lead ASIC Design Verification Engineer at Smartplay Inc
Industry Semiconductors
Experience
Smartplay Inc March 2012 - Present
SmartPlay Technologies July 2010 - March 2012
Infotech Enterprises February 2007 - July 2010
Education
Jawaharlal Nehru Technological University 2000 — 2004
B Tech, ECE
University of California, Santa Cruz 2006 — 2007
Certification course, VLSI Logic Design
Smartplay Inc March 2012 - Present
SmartPlay Technologies July 2010 - March 2012
Infotech Enterprises February 2007 - July 2010
Education
Jawaharlal Nehru Technological University 2000 — 2004
B Tech, ECE
University of California, Santa Cruz 2006 — 2007
Certification course, VLSI Logic Design
Anmol Sondhi Anmol Sondhi's Smartplay Inc Experience March 2011 - February 2013
Job VLSI design/verification expert
Industry Semiconductors
Experience
Qualcomm February 2013 - Present
SmartPlay Inc March 2011 - February 2013
Qualcomm March 2011 - February 2013
Mirafra Technologies February 2010 - March 2011
Cisco February 2010 - March 2011
Mirafra Technologies March 2008 - February 2010
Qualcomm November 2009 - January 2010
Broadcom May 2008 - October 2009
Freescale Semiconductor July 2005 - March 2008
Skills
Debugging, SystemVerilog, SoC, ASIC, Simulations, Verilog, RTL design, TCL, VLSI, EDA, Formal Verification, USB, Static Timing Analysis, RTL Design
Education
Indian Institute of Technology, Bombay 2000 — 2005
B Tech; M Tech, Microelectronics
BSP SSS - 10, Bhilai
10+2
Qualcomm February 2013 - Present
SmartPlay Inc March 2011 - February 2013
Qualcomm March 2011 - February 2013
Mirafra Technologies February 2010 - March 2011
Cisco February 2010 - March 2011
Mirafra Technologies March 2008 - February 2010
Qualcomm November 2009 - January 2010
Broadcom May 2008 - October 2009
Freescale Semiconductor July 2005 - March 2008
Skills
Debugging, SystemVerilog, SoC, ASIC, Simulations, Verilog, RTL design, TCL, VLSI, EDA, Formal Verification, USB, Static Timing Analysis, RTL Design
Education
Indian Institute of Technology, Bombay 2000 — 2005
B Tech; M Tech, Microelectronics
BSP SSS - 10, Bhilai
10+2
Suman Paul's Smartplay Inc Experience April 2010 - July 2012
Job Staff Application Consultant at Synopsys
Industry Semiconductors
Experience
Synopsys August 2012 - Present
Smartplay Inc. April 2010 - July 2012
SmartPlay Technologies April 2008 - April 2010
Synopsys August 2005 - March 2008
Intel October 2003 - August 2005
Texas Instruments July 2000 - October 2003
Skills
Low Power Design, Physical Design, ARM, SoC, Timing Closure, Pre-Sales Technical..., ASIC, EDA, Digital Signal..., Low-power Design, VLSI, Static Timing Analysis, TCL, Logic Synthesis, Timing, RTL design
Education
Bengal Engineering and Science University, Shibpur 1996 — 2000
B.E.
Synopsys August 2012 - Present
Smartplay Inc. April 2010 - July 2012
SmartPlay Technologies April 2008 - April 2010
Synopsys August 2005 - March 2008
Intel October 2003 - August 2005
Texas Instruments July 2000 - October 2003
Skills
Low Power Design, Physical Design, ARM, SoC, Timing Closure, Pre-Sales Technical..., ASIC, EDA, Digital Signal..., Low-power Design, VLSI, Static Timing Analysis, TCL, Logic Synthesis, Timing, RTL design
Education
Bengal Engineering and Science University, Shibpur 1996 — 2000
B.E.
Dhaneesh Krishnan's Smartplay Inc Experience September 2013 - Present
Job Lead ASIC Physical Design Engineer at Smartplay Inc
Industry Semiconductors
Experience
Smartplay Inc September 2013 - Present
Smartplay Inc September 2013 - Present
SmartPlay Technologies (I) Pvt Ltd November 2010 - September 2013
Texas Instruments India Pvt Ltd. May 2004 - December 2010
United Microelectronic Solutions Ltd. January 2004 - June 2004
Advanced Micronic Devices Ltd November 2001 - January 2004
Skills
Layout, ASIC, VLSI, Physical Design, SoC, Verilog, Static Timing Analysis, EDA, CMOS, TCL
Education
Coventry University 2009 — 2012
MSc Engineering in VLSI System Design, Microelectronics
NTTF Electronics Training Centre 1997 — 2000
Diploma In Electronics, Electronics
Smartplay Inc September 2013 - Present
Smartplay Inc September 2013 - Present
SmartPlay Technologies (I) Pvt Ltd November 2010 - September 2013
Texas Instruments India Pvt Ltd. May 2004 - December 2010
United Microelectronic Solutions Ltd. January 2004 - June 2004
Advanced Micronic Devices Ltd November 2001 - January 2004
Skills
Layout, ASIC, VLSI, Physical Design, SoC, Verilog, Static Timing Analysis, EDA, CMOS, TCL
Education
Coventry University 2009 — 2012
MSc Engineering in VLSI System Design, Microelectronics
NTTF Electronics Training Centre 1997 — 2000
Diploma In Electronics, Electronics
Mukul Kaushik's Smartplay Inc Experience May 2015 - Present
Job Senior Engineer at SmartPlay (An Aricent Company)
Industry Semiconductors
Experience
Smartplay Inc. May 2015 - Present
SmartPlay Technologies January 2013 - May 2015
Tata Elxsi April 2012 - January 2013
renesas electronics europe gmbh September 2012 - October 2012
Tata Elxsi October 2009 - April 2012
Intel Microelectronics, Malaysia March 2011 - December 2011
Tata Elxsi September 2007 - September 2009
Skills
Verilog, VHDL, Digital Design, SystemVerilog, ASIC, VLSI, Perl, Semiconductors, RTL design, Simulation, ModelSim, FPGA, VCS, Formal Verification, Functional Verification, SoC
Education
Punjab Technical University 2002 — 2006
Bachelor of Technology (B.Tech.), ECE
Manipal Academy of Higher Education
Master of Science (MS), Microelectronics
Smartplay Inc. May 2015 - Present
SmartPlay Technologies January 2013 - May 2015
Tata Elxsi April 2012 - January 2013
renesas electronics europe gmbh September 2012 - October 2012
Tata Elxsi October 2009 - April 2012
Intel Microelectronics, Malaysia March 2011 - December 2011
Tata Elxsi September 2007 - September 2009
Skills
Verilog, VHDL, Digital Design, SystemVerilog, ASIC, VLSI, Perl, Semiconductors, RTL design, Simulation, ModelSim, FPGA, VCS, Formal Verification, Functional Verification, SoC
Education
Punjab Technical University 2002 — 2006
Bachelor of Technology (B.Tech.), ECE
Manipal Academy of Higher Education
Master of Science (MS), Microelectronics
Phani Suresh P's Smartplay Inc Experience April 2013 - March 2014
Job Principal Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems April 2014 - Present
SmartPlay Inc April 2013 - March 2014
SmartPlay Technologies December 2010 - March 2013
ST Microelectronics August 2007 - December 2010
Ample Communications July 2006 - August 2007
Future Techno Designs January 2004 - July 2006
Skills
Validation, Project Management, Analog, Analog Circuit Design, PCIe, Display Port, ASIC, PLL, Project Proposals, Technical Recruiting, Project Coordination, SERDES, Power Management, Jitter, Physical Design, CMOS, Static Timing Analysis, VLSI, Cadence, Proposal Writing, Semiconductors, Verilog, VHDL, SystemVerilog, SoC, RTL design, Functional Verification, DRC, EDA, LVS, Integrated Circuit..., Mixed Signal, Spectre, RTL coding, IC, ModelSim
Education
National Institute of Technology, Warangal 2002 — 2003
M.Tech, VLSI System Design
Andhra University 1998 — 2002
B.E, Electronics & Communication Engg
Cadence Design Systems April 2014 - Present
SmartPlay Inc April 2013 - March 2014
SmartPlay Technologies December 2010 - March 2013
ST Microelectronics August 2007 - December 2010
Ample Communications July 2006 - August 2007
Future Techno Designs January 2004 - July 2006
Skills
Validation, Project Management, Analog, Analog Circuit Design, PCIe, Display Port, ASIC, PLL, Project Proposals, Technical Recruiting, Project Coordination, SERDES, Power Management, Jitter, Physical Design, CMOS, Static Timing Analysis, VLSI, Cadence, Proposal Writing, Semiconductors, Verilog, VHDL, SystemVerilog, SoC, RTL design, Functional Verification, DRC, EDA, LVS, Integrated Circuit..., Mixed Signal, Spectre, RTL coding, IC, ModelSim
Education
National Institute of Technology, Warangal 2002 — 2003
M.Tech, VLSI System Design
Andhra University 1998 — 2002
B.E, Electronics & Communication Engg
Tarini Prasad Baliar Singh's Smartplay Inc Experience March 2012 - Present
Job Senior design verification engineer at Smartplay Inc
Industry Semiconductors
Experience
Smartplay Inc March 2012 - Present
Smartplay Technologies August 2010 - March 2012
Xilinx November 2008 - July 2010
Ichip Technolgy India Ltd May 2008 - August 2008
Synopsys July 2006 - April 2008
Transwitch 2005 - 2006
C-DOT 2003 - 2005
Skills
VLSI, SystemVerilog, Open Verification..., ASIC, SoC, Verilog, VHDL, UVM, RTL coding, Functional Verification, ARM, DDR3, Ethernet, AXI, OVM
Education
Birla Institute of Technology and Science, Pilani 2002 — 2003
M.E., Communication Engg
Bangalore University 1996 — 2000
B.E., E & C
B J B College 1993 — 1995
10+2, Science
Smartplay Inc March 2012 - Present
Smartplay Technologies August 2010 - March 2012
Xilinx November 2008 - July 2010
Ichip Technolgy India Ltd May 2008 - August 2008
Synopsys July 2006 - April 2008
Transwitch 2005 - 2006
C-DOT 2003 - 2005
Skills
VLSI, SystemVerilog, Open Verification..., ASIC, SoC, Verilog, VHDL, UVM, RTL coding, Functional Verification, ARM, DDR3, Ethernet, AXI, OVM
Education
Birla Institute of Technology and Science, Pilani 2002 — 2003
M.E., Communication Engg
Bangalore University 1996 — 2000
B.E., E & C
B J B College 1993 — 1995
10+2, Science
Raghavendra Reddy P's Smartplay Inc Experience February 2014 - September 2014
Job Staff Design verification Engineer at Synaptics Inc
Industry Semiconductors
Experience
Synaptics Inc September 2014 - Present
Smartplay Inc February 2014 - September 2014
Smartplay Inc February 2012 - January 2014
Smartplay Technologies July 2010 - January 2012
Masamb Electronics Systems August 2009 - July 2010
Pw Systems October 2008 - May 2009
StellarIP Solutions Pvt Ltd February 2007 - September 2008
Vedant Organisation July 2006 - January 2007
Skills
Verilog, ASIC, SystemVerilog, SoC, VLSI, Formal Verification, EDA, Open Verification..., Specman, Perl, Cadence, Firmware, C, C++, Functional Verification, RTL design, NCSim, Static Timing Analysis, VHDL, ModelSim
Education
Jawaharlal Nehru Technological University 2002 — 2006
Bachelor of Technology (BTech), ECE
Ratnam Junior College, Nellore 1999 — 2001
Intermediate, MPC
Saradha vidhya Nilayam 1998 — 1999
10th Class
Synaptics Inc September 2014 - Present
Smartplay Inc February 2014 - September 2014
Smartplay Inc February 2012 - January 2014
Smartplay Technologies July 2010 - January 2012
Masamb Electronics Systems August 2009 - July 2010
Pw Systems October 2008 - May 2009
StellarIP Solutions Pvt Ltd February 2007 - September 2008
Vedant Organisation July 2006 - January 2007
Skills
Verilog, ASIC, SystemVerilog, SoC, VLSI, Formal Verification, EDA, Open Verification..., Specman, Perl, Cadence, Firmware, C, C++, Functional Verification, RTL design, NCSim, Static Timing Analysis, VHDL, ModelSim
Education
Jawaharlal Nehru Technological University 2002 — 2006
Bachelor of Technology (BTech), ECE
Ratnam Junior College, Nellore 1999 — 2001
Intermediate, MPC
Saradha vidhya Nilayam 1998 — 1999
10th Class
Gopinadh Chitturi's Smartplay Inc Experience January 2013 - Present
Job Technical Lead Consultant at Intel
Industry Semiconductors
Experience
Smartplay INC January 2013 - Present
Open-Silicon June 2007 - January 2013
Skills
Timing Closure, Clock Tree Synthesis, SystemVerilog, ASIC, RTL design, Physical Design, SoC, VLSI, Physical Verification, Static Timing Analysis, Verilog, TCL, Floorplanning, LVS, DRC
Education
University of Southampton 2004 — 2006
Master's degree, Micro Electronics Systems Design, First Class with Distinction
B. M. S. College of Engineering 1999 — 2003
Bachelor's degree, Electronics and Communications Engineering
Smartplay INC January 2013 - Present
Open-Silicon June 2007 - January 2013
Skills
Timing Closure, Clock Tree Synthesis, SystemVerilog, ASIC, RTL design, Physical Design, SoC, VLSI, Physical Verification, Static Timing Analysis, Verilog, TCL, Floorplanning, LVS, DRC
Education
University of Southampton 2004 — 2006
Master's degree, Micro Electronics Systems Design, First Class with Distinction
B. M. S. College of Engineering 1999 — 2003
Bachelor's degree, Electronics and Communications Engineering
Prasad Shinde's Smartplay Inc Experience September 2012 - Present
Job Asic Physical Design Engineer at Smartplay Inc
Industry Semiconductors
Experience
Smartplay Inc September 2012 - Present
SmartPlay Technologies September 2011 - August 2012
KPIT Cummins Infosystems Limited March 2010 - September 2011
MindTree October 2006 - February 2010
Silicon Interfaces February 2006 - October 2006
Skills
Physical Design, Timing Closure, Floorplann, Clock Tree Synthesis, Physical Verification, Route, Parasitic Extraction, Power Analysis, ASIC, Cadence, Routing, TCL, LVS, IC, Formal Verification, VLSI, SoC, Static Timing Analysis, Primetime, DRC, Verilog, EDA
Education
JLPT Administrative Examination 2009 — 2009
JLPT level 3, Japanese Language
University of Mumbai 2000 — 2004
B.E. (2004), Electronics
Smartplay Inc September 2012 - Present
SmartPlay Technologies September 2011 - August 2012
KPIT Cummins Infosystems Limited March 2010 - September 2011
MindTree October 2006 - February 2010
Silicon Interfaces February 2006 - October 2006
Skills
Physical Design, Timing Closure, Floorplann, Clock Tree Synthesis, Physical Verification, Route, Parasitic Extraction, Power Analysis, ASIC, Cadence, Routing, TCL, LVS, IC, Formal Verification, VLSI, SoC, Static Timing Analysis, Primetime, DRC, Verilog, EDA
Education
JLPT Administrative Examination 2009 — 2009
JLPT level 3, Japanese Language
University of Mumbai 2000 — 2004
B.E. (2004), Electronics
Gopala Krishnayya Boyapati's Smartplay Inc Experience January 2009 - Present
Job Sr.Design Engineer at Smartplay Inc
Industry Semiconductors
Experience
SmartPlay Inc January 2009 - Present
AMD June 2010 - January 2013
Qualcomm June 2009 - June 2010
Dgipro systems Pvt Ltd July 2006 - December 2008
Skills
VLSI, ASIC, SoC, SystemVerilog, RTL design, Physical Design, Verilog, Timing Closure, TCL, EDA, Static Timing Analysis, ModelSim, VHDL, Functional Verification, FPGA, Integrated Circuit..., Semiconductors, Cadence, Debugging, ARM, Embedded Systems
Education
Jawaharlal Nehru Technological University 2004 — 2006
Mtech, DSCE
Vellamal Engineering College 1997 — 2000
BE, ECE
VKR & VNB Poly
DECE, ECE
SmartPlay Inc January 2009 - Present
AMD June 2010 - January 2013
Qualcomm June 2009 - June 2010
Dgipro systems Pvt Ltd July 2006 - December 2008
Skills
VLSI, ASIC, SoC, SystemVerilog, RTL design, Physical Design, Verilog, Timing Closure, TCL, EDA, Static Timing Analysis, ModelSim, VHDL, Functional Verification, FPGA, Integrated Circuit..., Semiconductors, Cadence, Debugging, ARM, Embedded Systems
Education
Jawaharlal Nehru Technological University 2004 — 2006
Mtech, DSCE
Vellamal Engineering College 1997 — 2000
BE, ECE
VKR & VNB Poly
DECE, ECE
KALYAN KUMAR THOTA's Smartplay Inc Experience December 2005 - Present
Job Sr. Physical Design Engineer at Smartplay Inc
Industry Semiconductors
Experience
Smartplay Inc December 2005 - Present
TTM India Pvt Ltd July 2004 - November 2005
Education
Periyar University 2000 — 2004
Bachelor of Engineering, Electronics & Communication
Smartplay Inc December 2005 - Present
TTM India Pvt Ltd July 2004 - November 2005
Education
Periyar University 2000 — 2004
Bachelor of Engineering, Electronics & Communication
Pancham Sharma's Smartplay Inc Experience January 2013 - May 2015
Job Staff VLSI Engineer at Atmel Corporation
Industry Semiconductors
Experience
Atmel Corporation May 2015 - Present
Qualcomm January 2013 - May 2015
Smartplay inc. January 2013 - May 2015
SmartPlay Technologies July 2010 - January 2013
ST Microelectronics 2008 - December 2012
ST-Ericsson 2008 - 2012
MindTree Ltd. November 2007 - June 2010
HCL Technologies 2005 - 2007
Skills
Low-power Design, UPF, CPF, Static Timing Analysis, ASIC, FPGA, Logic Synthesis, Spyglass, CDC, Verilog, Equivalence Checking, DFT Compiler, RTL design, Scan Insertion, Formality, Synthesis, STA, FPGA Validation, ASIC Prototyping, Equivalence Checks, Formal Verification
Education
Vedant, Semiconductor Complex Ltd.(Indian Space and Research Organisation) 2005 — 2006
APGD in VLSI Design
Shivaji University 2001 — 2005
B.E
DAV Public School New Shimla 1999 — 2001
12
St.Edward's School, Shimla 1989 — 1999
10
Atmel Corporation May 2015 - Present
Qualcomm January 2013 - May 2015
Smartplay inc. January 2013 - May 2015
SmartPlay Technologies July 2010 - January 2013
ST Microelectronics 2008 - December 2012
ST-Ericsson 2008 - 2012
MindTree Ltd. November 2007 - June 2010
HCL Technologies 2005 - 2007
Skills
Low-power Design, UPF, CPF, Static Timing Analysis, ASIC, FPGA, Logic Synthesis, Spyglass, CDC, Verilog, Equivalence Checking, DFT Compiler, RTL design, Scan Insertion, Formality, Synthesis, STA, FPGA Validation, ASIC Prototyping, Equivalence Checks, Formal Verification
Education
Vedant, Semiconductor Complex Ltd.(Indian Space and Research Organisation) 2005 — 2006
APGD in VLSI Design
Shivaji University 2001 — 2005
B.E
DAV Public School New Shimla 1999 — 2001
12
St.Edward's School, Shimla 1989 — 1999
10
Ankur Rajvanshi's Smartplay Inc Experience May 2014 - Present
Job Sr Design Verification Engineer at SmartPlay Inc
Industry Semiconductors
Experience
SmartPlay Inc May 2014 - Present
SmartPlay Technologies India Pvt Ltd May 2013 - May 2014
SMSilicon Semiconductor Pvt. Ltd. February 2011 - May 2013
iKoa Semiconductor India Pvt. Ltd. July 2008 - January 2011
Skills
SystemVerilog, VLSI, TCL, RTL design, Static Timing Analysis, ASIC, Integrated Circuit..., Functional Verification, NCSim, SoC, Verilog, FPGA, UVM, VHDL, Low-power Design, VMM, Computer Architecture, EDA, Emulation
Education
International Institute of Information Technology 2006 — 2008
M.Tech, VLSI & Embedded Systems
CDAC,Noida 2005 — 2005
PGDEVD, Embedded Systems & VLSI design
Engineering College Ajmer 2001 — 2005
B.E., Electronics and Communication Engg
SmartPlay Inc May 2014 - Present
SmartPlay Technologies India Pvt Ltd May 2013 - May 2014
SMSilicon Semiconductor Pvt. Ltd. February 2011 - May 2013
iKoa Semiconductor India Pvt. Ltd. July 2008 - January 2011
Skills
SystemVerilog, VLSI, TCL, RTL design, Static Timing Analysis, ASIC, Integrated Circuit..., Functional Verification, NCSim, SoC, Verilog, FPGA, UVM, VHDL, Low-power Design, VMM, Computer Architecture, EDA, Emulation
Education
International Institute of Information Technology 2006 — 2008
M.Tech, VLSI & Embedded Systems
CDAC,Noida 2005 — 2005
PGDEVD, Embedded Systems & VLSI design
Engineering College Ajmer 2001 — 2005
B.E., Electronics and Communication Engg
Prashanth reddy gade's Smartplay Inc Experience December 2013 - Present
Job Sr. Engineer at Qualcomm
Industry Semiconductors
Experience
SMARTPLAY INC December 2013 - Present
LSI Corporation January 2013 - October 2013
Qualcomm September 2007 - December 2012
Skills
SystemVerilog, Debugging, Computer Architecture, C++, ClearCase, UVM, Verilog, OVM
Education
Indian Institute of Technology, Guwahati 2005 — 2007
M.Tech, VLSI & Signal processing
Jawaharlal Nehru Technological University 2001 — 2005
Bachelor's degree, Electronics and communication Engineering
SMARTPLAY INC December 2013 - Present
LSI Corporation January 2013 - October 2013
Qualcomm September 2007 - December 2012
Skills
SystemVerilog, Debugging, Computer Architecture, C++, ClearCase, UVM, Verilog, OVM
Education
Indian Institute of Technology, Guwahati 2005 — 2007
M.Tech, VLSI & Signal processing
Jawaharlal Nehru Technological University 2001 — 2005
Bachelor's degree, Electronics and communication Engineering
Ravi Kalyan PG's Smartplay Inc Experience February 2012 - April 2014
Job Senior Verification Engineer at Qualcomm
Industry Semiconductors
Experience
Qualcomm April 2014 - Present
Smartplay Inc February 2012 - April 2014
SmartPlay Technologies December 2009 - January 2012
GDA Technologies (LnT Infotech) August 2004 - November 2009
Skills
SystemVerilog, ASIC, SoC, Verilog, ARM, C, Perl, Semiconductors, C++, VLSI, TCL, Debugging, I2C, PCIe, UVM, AMBA AHB, AXI
Education
SASTRA 2002 — 2004
Master of Technology (MTech), VLSI Design, A
University of Madras 1997 — 2001
Bachelor of Engineering (B.E.), Electrical and Electronics Engineering, A
Qualcomm April 2014 - Present
Smartplay Inc February 2012 - April 2014
SmartPlay Technologies December 2009 - January 2012
GDA Technologies (LnT Infotech) August 2004 - November 2009
Skills
SystemVerilog, ASIC, SoC, Verilog, ARM, C, Perl, Semiconductors, C++, VLSI, TCL, Debugging, I2C, PCIe, UVM, AMBA AHB, AXI
Education
SASTRA 2002 — 2004
Master of Technology (MTech), VLSI Design, A
University of Madras 1997 — 2001
Bachelor of Engineering (B.E.), Electrical and Electronics Engineering, A
Srinivas Yedla's Smartplay Inc Experience May 2014 - Present
Job Computer System Engineer at Smartplay Inc
Industry Computer Software
Experience
Smartplay Inc May 2014 - Present
Aricent March 2008 - January 2011
Wipro Technologies January 2006 - February 2008
Skills
Embedded Systems, Linux Device drivers, Nucleus RTOS, USB drivers, I2C drivers, Sensors drivers, I2C..., BSP, ARM, debugging tools...
Education
Jawaharlal Nehru Technological University 1999 — 2003
Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering, 1st
Smartplay Inc May 2014 - Present
Aricent March 2008 - January 2011
Wipro Technologies January 2006 - February 2008
Skills
Embedded Systems, Linux Device drivers, Nucleus RTOS, USB drivers, I2C drivers, Sensors drivers, I2C..., BSP, ARM, debugging tools...
Education
Jawaharlal Nehru Technological University 1999 — 2003
Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering, 1st
Srikanth Suraneni's Smartplay Inc Experience February 2008 - Present
Job Senior Engineer at SmartPlay Technologies
Industry Semiconductors
Experience
Smartplay Inc February 2008 - Present
Mindtree Ltd. August 2006 - January 2008
Skills
Physical Design, Floorplanning, Place & Route, Clock Tree Synthesis, Static Timing Analysis, Timing Closure, TCL
Education
Osmania University 2003 — 2005
Master of Engineering (MEng), VLSI and Embedded systems
Smartplay Inc February 2008 - Present
Mindtree Ltd. August 2006 - January 2008
Skills
Physical Design, Floorplanning, Place & Route, Clock Tree Synthesis, Static Timing Analysis, Timing Closure, TCL
Education
Osmania University 2003 — 2005
Master of Engineering (MEng), VLSI and Embedded systems