Cadence Design Systems
Industry: Software company
DescriptionCadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. CEO: Lip-Bu Tan (Jan 2009–) Headquarters: San Jose, California, United States Revenue: 1.816 billion USD (2016) Subsidiaries: Sigrity, Tensilica, Chip Estimate Corp, nusemi inc,
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Cadence Design Systems Employees
Employee
Years
Job
Industry
Brett Metz Brett Metz's Cadence Design Systems Experience August 2000 - June 2003
Job Sr. Account Executive, Altium Inc.
Industry Computer Software
Experience
Altium January 2010 - Present
Altium 2009 - Present
Nine Dot Connects January 2010 - October 2014
TechBridge Solutions, Inc. September 2009 - January 2010
EMA Design Automation July 2003 - September 2009
Cadence Design Systems August 2000 - June 2003
OrCAD Inc July 1998 - August 2000
Sucessfull Money Managemnt Seminars July 1995 - August 1998
Education
New Mexico State University 1991 — 1995
Bachelor of Science, Psychology / Criminal Justice
Aztec 1987 — 1989
Altium January 2010 - Present
Altium 2009 - Present
Nine Dot Connects January 2010 - October 2014
TechBridge Solutions, Inc. September 2009 - January 2010
EMA Design Automation July 2003 - September 2009
Cadence Design Systems August 2000 - June 2003
OrCAD Inc July 1998 - August 2000
Sucessfull Money Managemnt Seminars July 1995 - August 1998
Education
New Mexico State University 1991 — 1995
Bachelor of Science, Psychology / Criminal Justice
Aztec 1987 — 1989
Sue Sun Sue Sun's Cadence Design Systems Experience 1991 - 2009
Job President at emReal Corporation
Industry Computer Software
Experience
emReal Corporation PresidentAcumenTech2011 - 2013
a networking start up 2011 - 2011
Monolithic Power Systems, Inc. 2009 - 2011
Cadence Design Systems 1991 - 2009
Cirrus Logic 1985 - 1991
Skills
Enthusiastic..., Team Leadership, Team Building, Persistency, Technical Leadership, Team Management, Product Management, Organizational..., Organizational..., Cross-functional Team..., Teamwork, Creative Problem Solving, Alumni Affairs
Education
National Taiwan University
Bachelor of Science (BS)
The University of Texas at Dallas
Master's degree, Computer Science
emReal Corporation PresidentAcumenTech2011 - 2013
a networking start up 2011 - 2011
Monolithic Power Systems, Inc. 2009 - 2011
Cadence Design Systems 1991 - 2009
Cirrus Logic 1985 - 1991
Skills
Enthusiastic..., Team Leadership, Team Building, Persistency, Technical Leadership, Team Management, Product Management, Organizational..., Organizational..., Cross-functional Team..., Teamwork, Creative Problem Solving, Alumni Affairs
Education
National Taiwan University
Bachelor of Science (BS)
The University of Texas at Dallas
Master's degree, Computer Science
Kevin Guay's Cadence Design Systems Experience August 2002 - February 2005
Job Principal Member of Technical Staff EDA Engineer at Maxim Integrated
Industry Semiconductors
Experience
Maxim Integrated Products September 2011 - Present
Maxim Integrated September 2011 - Present
Cambridge Analog Technologies, Inc. 2009 - September 2011
IBM October 2005 - October 2009
Cadence Design Systems August 2002 - February 2005
Cadence Design Systems August 1999 - August 2002
IBM April 1996 - August 1999
IBM Global Services May 1989 - April 1996
Skills
Programming Languages, Hercules, EDA, Physical Design, VLSI, Cadence Virtuoso, Skill Programming, Sales Support, Sales Operations, Process Development, Software Development..., Design Methodology, Productivity Improvement, Productivity Enhancement, Calibre, Physical Verification, CAD, Software Project..., International Project..., Critical Chain Project..., ASIC, Process Simulation, Analog, PLL, Mixed Signal, SoC, IC, Debugging, Analog Circuit Design, BiCMOS, Circuit Design, Cadence, Virtuoso, Semiconductors, CMOS
Education
New England Institute of Technology 1988 — 1989
Maxim Integrated Products September 2011 - Present
Maxim Integrated September 2011 - Present
Cambridge Analog Technologies, Inc. 2009 - September 2011
IBM October 2005 - October 2009
Cadence Design Systems August 2002 - February 2005
Cadence Design Systems August 1999 - August 2002
IBM April 1996 - August 1999
IBM Global Services May 1989 - April 1996
Skills
Programming Languages, Hercules, EDA, Physical Design, VLSI, Cadence Virtuoso, Skill Programming, Sales Support, Sales Operations, Process Development, Software Development..., Design Methodology, Productivity Improvement, Productivity Enhancement, Calibre, Physical Verification, CAD, Software Project..., International Project..., Critical Chain Project..., ASIC, Process Simulation, Analog, PLL, Mixed Signal, SoC, IC, Debugging, Analog Circuit Design, BiCMOS, Circuit Design, Cadence, Virtuoso, Semiconductors, CMOS
Education
New England Institute of Technology 1988 — 1989
Holt Ennis Holt Ennis's Cadence Design Systems Experience November 1990 - July 1994
Job Contract Technical Writer at VST Inc.
Industry Computer Software
Experience
Akamai Technologies July 2014 - September 2014
Picis Inc. (part of UnitedHealth Group) August 2005 - August 2012
Parametric Technology January 2005 - August 2005
Aprilis Inc. February 2004 - October 2004
Parametric Technology January 1996 - December 2003
GTE July 1994 - April 1996
Cadence Design Systems November 1990 - July 1994
Litton Airtron Hylectronics 1989 - 1990
Offtech 1988 - 1989
Early Positions and Part-time Contract Work 1979 - 1988
Skills
MadCap Flare, FrameMaker, Captivate, PowerPoint, Visual Studio, Iso 9000, C, Integration, XML, Software Documentation, Testing, Project Planning, Online Help, Databases, Technical Documentation, Manuals, Technical Communication, RoboHelp, Single Sourcing, Visio, SnagIt, SharePoint, Technical Writing, Medical Devices, Defect Tracking, Change Orders, PDM, Configuration Management, Product Definition, Online Help Development, Content Management, HP Quality Center, Hands-on Training, End User Training, Software Quality..., Instructor-led Training, Scrum, Quality Assurance
Education
Middlesex Community College 1989 — 1990
Technical Writing Certificate, Technical Writing
ATI 1987 — 1988
Electronics Certificate, Electronics
New England School of Law 1975 — 1978
JD, Law
Tufts University 1970 — 1974
BFA, Fine/Studio Arts, General
Various
Akamai Technologies July 2014 - September 2014
Picis Inc. (part of UnitedHealth Group) August 2005 - August 2012
Parametric Technology January 2005 - August 2005
Aprilis Inc. February 2004 - October 2004
Parametric Technology January 1996 - December 2003
GTE July 1994 - April 1996
Cadence Design Systems November 1990 - July 1994
Litton Airtron Hylectronics 1989 - 1990
Offtech 1988 - 1989
Early Positions and Part-time Contract Work 1979 - 1988
Skills
MadCap Flare, FrameMaker, Captivate, PowerPoint, Visual Studio, Iso 9000, C, Integration, XML, Software Documentation, Testing, Project Planning, Online Help, Databases, Technical Documentation, Manuals, Technical Communication, RoboHelp, Single Sourcing, Visio, SnagIt, SharePoint, Technical Writing, Medical Devices, Defect Tracking, Change Orders, PDM, Configuration Management, Product Definition, Online Help Development, Content Management, HP Quality Center, Hands-on Training, End User Training, Software Quality..., Instructor-led Training, Scrum, Quality Assurance
Education
Middlesex Community College 1989 — 1990
Technical Writing Certificate, Technical Writing
ATI 1987 — 1988
Electronics Certificate, Electronics
New England School of Law 1975 — 1978
JD, Law
Tufts University 1970 — 1974
BFA, Fine/Studio Arts, General
Various
Jack Hsieh Jack Hsieh's Cadence Design Systems Experience February 2014 - Present
Job Staff Application Engineer at Cadence Design Systems
Industry Electrical/Electronic Manufacturing
Experience
Cadence Design Systems February 2014 - Present
Transwitch October 2010 - Present
Analogix Semi. May 2006 - August 2009
T-Square Design, Inc. /ALi March 2002 - October 2005
DigiBits Interactive, Inc. January 2000 - January 2002
Tvia January 1997 - December 1999
Avance Logic, Inc. October 1991 - December 1996
Skills
SoC, FPGA, Firmware, Debugging, HDMI, System Architecture, IC, Digital TV, ASIC, Mixed Signal, Embedded Systems, Embedded Software, Embedded Linux, Analog, USB, Semiconductors, Product Management, Wireless, Consumer Electronics, Digital Signal..., System Design, SERDES, ARM, RF, I2C, Microcontrollers, RTOS, MPEG, Integrated Circuit..., EDA, Hardware, Semiconductor Industry, Device Drivers, Electronics, Verilog, Hardware Architecture, H.264, Analog Circuit Design, Circuit Design, WiFi, Processors, MPEG2, PCB design, Systems Design, PCB Design
Education
National Taipei University of Technology 1975 — 1979
BS, Electrical Engineering
Cadence Design Systems February 2014 - Present
Transwitch October 2010 - Present
Analogix Semi. May 2006 - August 2009
T-Square Design, Inc. /ALi March 2002 - October 2005
DigiBits Interactive, Inc. January 2000 - January 2002
Tvia January 1997 - December 1999
Avance Logic, Inc. October 1991 - December 1996
Skills
SoC, FPGA, Firmware, Debugging, HDMI, System Architecture, IC, Digital TV, ASIC, Mixed Signal, Embedded Systems, Embedded Software, Embedded Linux, Analog, USB, Semiconductors, Product Management, Wireless, Consumer Electronics, Digital Signal..., System Design, SERDES, ARM, RF, I2C, Microcontrollers, RTOS, MPEG, Integrated Circuit..., EDA, Hardware, Semiconductor Industry, Device Drivers, Electronics, Verilog, Hardware Architecture, H.264, Analog Circuit Design, Circuit Design, WiFi, Processors, MPEG2, PCB design, Systems Design, PCB Design
Education
National Taipei University of Technology 1975 — 1979
BS, Electrical Engineering
Pawan Kushreshtha Pawan Kushreshtha's Cadence Design Systems Experience 2006 - Present
Job Engineering Director at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems 2006 - Present
Cadence Design Systems 2006 - 2006
Cadence Design Systems 2003 - 2006
Cadence Design Systems 1997 - 2003
Compass Design Automation 1995 - 1997
Skills
People Management, Multi-Site Project..., EDA, Static Timing Analysis, Statistical timing..., Timing Closure, Power Analysis, Simulations, High Level Synthesis, VHDL, Verilog, C, C++, Linux, Data Structures, Algorithms, Performance Improvement, Parallel Processing, Multithreading
Education
National Institute of Technology Warangal
B.Tech, Electronic & Communication Engineering
Cadence Design Systems 2006 - Present
Cadence Design Systems 2006 - 2006
Cadence Design Systems 2003 - 2006
Cadence Design Systems 1997 - 2003
Compass Design Automation 1995 - 1997
Skills
People Management, Multi-Site Project..., EDA, Static Timing Analysis, Statistical timing..., Timing Closure, Power Analysis, Simulations, High Level Synthesis, VHDL, Verilog, C, C++, Linux, Data Structures, Algorithms, Performance Improvement, Parallel Processing, Multithreading
Education
National Institute of Technology Warangal
B.Tech, Electronic & Communication Engineering
Andy Lin Andy Lin's Cadence Design Systems Experience August 2010 - January 2014
Job President & CEO at VisualOn, Inc.
Industry Computer Software
Experience
VisualOn, Inc. January 2014 - Present
Cadence Design Systems August 2010 - January 2014
Cadence Design Systems August 2003 - August 2010
Verplex Design Systems 2001 - 2003
Verplex Design Systems 1997 - 2001
Skills
EDA, VLSI, Algorithms, Formal Verification, Distributed Systems, Low-power Design, Semiconductors, Software Engineering, Embedded Systems, ASIC, Perl, Object Oriented Design, Simulations, System Architecture, Software Development
Education
University of California, Santa Barbara 1992 — 1996
Ph.D, ECE
University of California, Santa Barbara 1989 — 1991
M.S., Computer Science
National Taiwan University 1983 — 1987
B.S., Computer Science
VisualOn, Inc. January 2014 - Present
Cadence Design Systems August 2010 - January 2014
Cadence Design Systems August 2003 - August 2010
Verplex Design Systems 2001 - 2003
Verplex Design Systems 1997 - 2001
Skills
EDA, VLSI, Algorithms, Formal Verification, Distributed Systems, Low-power Design, Semiconductors, Software Engineering, Embedded Systems, ASIC, Perl, Object Oriented Design, Simulations, System Architecture, Software Development
Education
University of California, Santa Barbara 1992 — 1996
Ph.D, ECE
University of California, Santa Barbara 1989 — 1991
M.S., Computer Science
National Taiwan University 1983 — 1987
B.S., Computer Science
Robyn Im Robyn Im's Cadence Design Systems Experience October 2002 - July 2007
Job Program Manager at Google
Industry Internet
Experience
Google October 2013 - Present
Google December 2012 - October 2013
Domicella.com June 2008 - December 2012
Pacific Rim Partners August 2007 - September 2007
Pacific Rim Partners July 2007 - August 2007
Cadence Design Systems October 2002 - July 2007
Skills
Product Management, E-commerce, Competitive Analysis, Product Marketing, User Experience, Financial Modeling, Start-ups, Cross-functional Team..., Entrepreneurship, Go-to-market Strategy, Product Requirements, Analytics, Capital Markets, Financial Reporting, Web Analytics, Cloud Computing, Strategic Partnerships, Management
Education
New York University
B.F.A., Film
University of California, Berkeley - Walter A. Haas School of Business
MBA
Google October 2013 - Present
Google December 2012 - October 2013
Domicella.com June 2008 - December 2012
Pacific Rim Partners August 2007 - September 2007
Pacific Rim Partners July 2007 - August 2007
Cadence Design Systems October 2002 - July 2007
Skills
Product Management, E-commerce, Competitive Analysis, Product Marketing, User Experience, Financial Modeling, Start-ups, Cross-functional Team..., Entrepreneurship, Go-to-market Strategy, Product Requirements, Analytics, Capital Markets, Financial Reporting, Web Analytics, Cloud Computing, Strategic Partnerships, Management
Education
New York University
B.F.A., Film
University of California, Berkeley - Walter A. Haas School of Business
MBA
Jhih-Rong Gao Jhih-Rong Gao's Cadence Design Systems Experience July 2014 - Present
Job Lead Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2014 - Present
The University of Texas at Austin September 2012 - May 2014
Intel Corporation May 2012 - August 2012
University of Texas at Austin September 2009 - May 2012
Synopsys May 2011 - August 2011
Synopsys September 2007 - June 2009
National Tsing Hua University August 2003 - January 2007
Skills
C/C++, Tcl/SKILL, Qt, Perl, TCL, C++, VLSI, Algorithms, Unix, Physical Design, Data Structures, Verilog, C, Python, EDA
Education
The University of Texas at Austin 2009 — 2014
Doctor of Philosophy (PhD), Electrical and Computer Engineering
National Tsing Hua University 2005 — 2007
MS, Computer Science
National Tsing Hua University 2001 — 2005
BS, Computer Science
Cadence Design Systems July 2014 - Present
The University of Texas at Austin September 2012 - May 2014
Intel Corporation May 2012 - August 2012
University of Texas at Austin September 2009 - May 2012
Synopsys May 2011 - August 2011
Synopsys September 2007 - June 2009
National Tsing Hua University August 2003 - January 2007
Skills
C/C++, Tcl/SKILL, Qt, Perl, TCL, C++, VLSI, Algorithms, Unix, Physical Design, Data Structures, Verilog, C, Python, EDA
Education
The University of Texas at Austin 2009 — 2014
Doctor of Philosophy (PhD), Electrical and Computer Engineering
National Tsing Hua University 2005 — 2007
MS, Computer Science
National Tsing Hua University 2001 — 2005
BS, Computer Science
Deepak Tomar Deepak Tomar's Cadence Design Systems Experience March 2003 - April 2007
Job Founder and CTO
Industry Information Technology and Services
Experience
Clavax Technologies LLC May 2011 - Present
Cadence Design Systems March 2003 - April 2007
Skills
Project Management, Web Development, Team Leadership, Business Analysis, Product Development, Loyalty Programs, Real Estate, E-commerce, Architecture, Software Development, PHP, Web Services, Defect Tracking, QTP, Functional Testing, Selenium, US Healthcare, Strategy, Leadership, Social Media, JavaScript, HTML, ASP.NET, .NET, Business Intelligence, HTML 5, Databases, HTML5, AJAX, MySQL, Architectures
Education
KKR University 1998 — 2002
B Tech, Computer Science
National Institute of Technology Kurukshetra 1998 — 2002
Bachelor Of Technology, Computer Science
Clavax Technologies LLC May 2011 - Present
Cadence Design Systems March 2003 - April 2007
Skills
Project Management, Web Development, Team Leadership, Business Analysis, Product Development, Loyalty Programs, Real Estate, E-commerce, Architecture, Software Development, PHP, Web Services, Defect Tracking, QTP, Functional Testing, Selenium, US Healthcare, Strategy, Leadership, Social Media, JavaScript, HTML, ASP.NET, .NET, Business Intelligence, HTML 5, Databases, HTML5, AJAX, MySQL, Architectures
Education
KKR University 1998 — 2002
B Tech, Computer Science
National Institute of Technology Kurukshetra 1998 — 2002
Bachelor Of Technology, Computer Science
Rossana Liu Rossana Liu's Cadence Design Systems Experience July 2014 - Present
Job Staff Customer Engagement Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2014 - Present
Cadence Design Systems 2011 - June 2014
Silicon Integrated Systems. July 2009 - April 2011
Magma Design Automation March 2004 - April 2007
Faraday March 2002 - March 2004
Synopsys January 2000 - February 2002
Skills
Microsoft Excel, PowerPoint, Microsoft Office, Customer Service, Microsoft Word
Education
University of Southern California 1998 — 1999
Master of Science (M.S.), Electrical Engineering
National Cheng Kung University 1993 — 1997
Bachelor of Science (BS), Electrical and Electronics Engineering
Cadence Design Systems July 2014 - Present
Cadence Design Systems 2011 - June 2014
Silicon Integrated Systems. July 2009 - April 2011
Magma Design Automation March 2004 - April 2007
Faraday March 2002 - March 2004
Synopsys January 2000 - February 2002
Skills
Microsoft Excel, PowerPoint, Microsoft Office, Customer Service, Microsoft Word
Education
University of Southern California 1998 — 1999
Master of Science (M.S.), Electrical Engineering
National Cheng Kung University 1993 — 1997
Bachelor of Science (BS), Electrical and Electronics Engineering
Scott Seabaugh Scott Seabaugh's Cadence Design Systems Experience 1985 - 1992
Job Partner at Craig Miller Associates: Software, Aviation/Aerospace, BioMed/Medical Device
Industry Staffing and Recruiting
Experience
Craig Miller Associates August 1994 - Present
Craig Miller Associates August 1994 - July 2010
Toshiba 1992 - 1994
Cadence Design Systems 1985 - 1992
Education
National University 1983 — 1986
MBA, Finance
University of California, Irvine 1976 — 1978
BSEE, Electrical Engineering
Craig Miller Associates August 1994 - Present
Craig Miller Associates August 1994 - July 2010
Toshiba 1992 - 1994
Cadence Design Systems 1985 - 1992
Education
National University 1983 — 1986
MBA, Finance
University of California, Irvine 1976 — 1978
BSEE, Electrical Engineering
Vikrant Garg Vikrant Garg's Cadence Design Systems Experience April 2013 - August 2014
Job Graduate Student at NC State
Industry Semiconductors
Experience
Apple May 2015 - August 2015
Cadence Design Systems April 2013 - August 2014
Qualcomm January 2011 - April 2013
Skills
CAD, Physical Design, Static Timing Analysis, Perl, Synopsys Primetime, First Encounter, SPICE, TCL, VLSI, ASIC, Methodology, Embedded Systems, C++, C, VHDL, Ruby, HSPICE
Education
North Carolina State University 2014 — 2016
Master's degree, Computer Engineering, 4.0/4.0
Netaji Subhas Institute of Technology 2006 — 2010
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
The Air Force School, Delhi
Apple May 2015 - August 2015
Cadence Design Systems April 2013 - August 2014
Qualcomm January 2011 - April 2013
Skills
CAD, Physical Design, Static Timing Analysis, Perl, Synopsys Primetime, First Encounter, SPICE, TCL, VLSI, ASIC, Methodology, Embedded Systems, C++, C, VHDL, Ruby, HSPICE
Education
North Carolina State University 2014 — 2016
Master's degree, Computer Engineering, 4.0/4.0
Netaji Subhas Institute of Technology 2006 — 2010
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
The Air Force School, Delhi
Loren Reiss Loren Reiss's Cadence Design Systems Experience January 2004 - Present
Job Staff Design Engineer and Product Line Architect at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems January 2004 - Present
Intellon Corporation 2002 - 2003
VLSI Technology 1997 - 2002
IBM 1991 - 1997
Skills
ASIC, RTL design, Functional Verification, SoC, System Architecture, Technical Writing, Team Leadership, FPGA, Logic Design, Digital Electronics, Verilog, Hardware Architecture
Education
North Carolina State University 1991 — 1996
Master of Engineering (MEng), Computer Engineering
Virginia Polytechnic Institute and State University 1986 — 1991
Bachelor's degree, Computer Engineering
Cadence Design Systems January 2004 - Present
Intellon Corporation 2002 - 2003
VLSI Technology 1997 - 2002
IBM 1991 - 1997
Skills
ASIC, RTL design, Functional Verification, SoC, System Architecture, Technical Writing, Team Leadership, FPGA, Logic Design, Digital Electronics, Verilog, Hardware Architecture
Education
North Carolina State University 1991 — 1996
Master of Engineering (MEng), Computer Engineering
Virginia Polytechnic Institute and State University 1986 — 1991
Bachelor's degree, Computer Engineering
Niket K Choudhary's Cadence Design Systems Experience January 2005 - May 2005
Job CPU Performance Modeling
Industry Computer Hardware
Experience
Qualcomm May 2012 - Present
North Carolina State University September 2007 - May 2012
Microsoft May 2011 - August 2011
Intel Corporation May 2010 - August 2010
ARM August 2005 - July 2007
Cadence Design Systems January 2005 - May 2005
Skills
Computer Architecture, Processor..., Performance Modeling, Power Modeling, C/C++, Verilog RTL, Microarchitecture, Verilog, Performance Engineering, ASIC
Education
North Carolina State University 2009 — 2012
Ph.D., Computer Engineering
North Carolina State University 2007 — 2009
MS, Computer Engineering
Dhirubhai Ambani Institute of Information and Communication Technology 2001 — 2005
Bachelor, Engineering
Qualcomm May 2012 - Present
North Carolina State University September 2007 - May 2012
Microsoft May 2011 - August 2011
Intel Corporation May 2010 - August 2010
ARM August 2005 - July 2007
Cadence Design Systems January 2005 - May 2005
Skills
Computer Architecture, Processor..., Performance Modeling, Power Modeling, C/C++, Verilog RTL, Microarchitecture, Verilog, Performance Engineering, ASIC
Education
North Carolina State University 2009 — 2012
Ph.D., Computer Engineering
North Carolina State University 2007 — 2009
MS, Computer Engineering
Dhirubhai Ambani Institute of Information and Communication Technology 2001 — 2005
Bachelor, Engineering
Joseph Jiang Joseph Jiang's Cadence Design Systems Experience 1989 - 1994
Job Marketing and Business Development Executive Seeking next adventure
Industry Semiconductors
Experience
Fortemedia November 2012 - August 2015
InvenSense, Inc. November 2011 - October 2012
InvenSense June 2007 - November 2011
Mobilic Technology December 2003 - April 2007
IC Media June 1999 - November 2003
Applied Materials, Taiwan 1994 - 1995
Cadence Design Systems 1989 - 1994
Skills
Semiconductors, IC, Product Marketing, Sensors, Smartphones, Video, Business Development, Ecosystem Management, MEMS, Consumer Electronics, Analog, ASIC, SoC, CMOS, Mixed Signal, Wireless, Electronics, Semiconductor Industry, EDA, Mobile Devices, Product Management, Embedded Systems
Education
San Jose State University 1987 — 1988
MSEE, Electrincal Engineering
National Chiao Tung University 1978 — 1982
BSEE, Electronics Engineering
High School of Taiwan Normal University
Fortemedia November 2012 - August 2015
InvenSense, Inc. November 2011 - October 2012
InvenSense June 2007 - November 2011
Mobilic Technology December 2003 - April 2007
IC Media June 1999 - November 2003
Applied Materials, Taiwan 1994 - 1995
Cadence Design Systems 1989 - 1994
Skills
Semiconductors, IC, Product Marketing, Sensors, Smartphones, Video, Business Development, Ecosystem Management, MEMS, Consumer Electronics, Analog, ASIC, SoC, CMOS, Mixed Signal, Wireless, Electronics, Semiconductor Industry, EDA, Mobile Devices, Product Management, Embedded Systems
Education
San Jose State University 1987 — 1988
MSEE, Electrincal Engineering
National Chiao Tung University 1978 — 1982
BSEE, Electronics Engineering
High School of Taiwan Normal University
Tony Heib Tony Heib's Cadence Design Systems Experience July 1992 - Present
Job Staff Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 1992 - Present
S-MOS Systems (Seiko Epson) January 1990 - July 1992
GE Microelectronics January 1986 - December 1989
Memorex Telex December 1986 - December 1987
US Army October 1976 - March 1985
Skills
EDA, Low-power Design
Education
North Carolina State University 1982 — 1985
BSEE, Electrical Engineering
US Army Warrant Officer Flight School 1976 — 1977
Cadence Design Systems July 1992 - Present
S-MOS Systems (Seiko Epson) January 1990 - July 1992
GE Microelectronics January 1986 - December 1989
Memorex Telex December 1986 - December 1987
US Army October 1976 - March 1985
Skills
EDA, Low-power Design
Education
North Carolina State University 1982 — 1985
BSEE, Electrical Engineering
US Army Warrant Officer Flight School 1976 — 1977
徐亨福Hengfu Hsu 徐亨福Hengfu Hsu's Cadence Design Systems Experience July 2002 - November 2006
Job Protect wealth in bear markets and maximize growth in bull markets.
Industry Investment Management
Experience
Analytic Investment Management LLC October 2007 - Present
Wealthmax Capital LLC May 2012 - December 2013
Sun Microsystems November 2006 - October 2007
Cadence Design Systems July 2002 - November 2006
Simplex Solutions (Acquired by Cadence) August 1998 - July 2002
Aspec Technology, Inc. May 1993 - August 1998
Skills
Asset Management, Portfolio Management, Financial Modeling, Investments, Trading, Equity Research, Equities, Financial Analysis, C++, Ruby, VBA, Venture Capital, Private Equity, Hedge Funds, Algorithms
Education
Stanford University 2002 — 2002
Professional Development in Linear and Nonlinear Optimization
UCSC Silicon Valley Extension 1995 — 1998
Certificate in VLSI Design Engineering
UCSC Silicon Valley Extension 1995 — 1997
Professional Sequence Award in Microsoft Windows Programming
University of Southern California 1991 — 1992
Master, Computer Engineering
National Tsing Hua University 1986 — 1990
BS, Electrical Engineering
National Tsing Hua University 1986 — 1990
BS, Power Mechanical Engineering
Taipei Municipal Jianguo High School 1983 — 1986
Analytic Investment Management LLC October 2007 - Present
Wealthmax Capital LLC May 2012 - December 2013
Sun Microsystems November 2006 - October 2007
Cadence Design Systems July 2002 - November 2006
Simplex Solutions (Acquired by Cadence) August 1998 - July 2002
Aspec Technology, Inc. May 1993 - August 1998
Skills
Asset Management, Portfolio Management, Financial Modeling, Investments, Trading, Equity Research, Equities, Financial Analysis, C++, Ruby, VBA, Venture Capital, Private Equity, Hedge Funds, Algorithms
Education
Stanford University 2002 — 2002
Professional Development in Linear and Nonlinear Optimization
UCSC Silicon Valley Extension 1995 — 1998
Certificate in VLSI Design Engineering
UCSC Silicon Valley Extension 1995 — 1997
Professional Sequence Award in Microsoft Windows Programming
University of Southern California 1991 — 1992
Master, Computer Engineering
National Tsing Hua University 1986 — 1990
BS, Electrical Engineering
National Tsing Hua University 1986 — 1990
BS, Power Mechanical Engineering
Taipei Municipal Jianguo High School 1983 — 1986
Teng-Kiat Lee Teng-Kiat Lee's Cadence Design Systems Experience November 2011 - Present
Job Product Engineering Director at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems November 2011 - Present
Cadence Design Systems October 2007 - Present
Cadence Design Systems March 2001 - October 2007
Agilent Technologies 1998 - 2001
Hewlett-Packard 1997 - 2001
Hewlett-Packard May 1994 - 1997
Skills
EDA, IC, Mixed Signal, Usability, Semiconductors, Analog, Integrated Circuit..., Product Engineering, R&D, Unix, Analog Circuit Design, ASIC, Simulations, Verilog, CMOS, SoC, Debugging, Functional Verification, VLSI, Virtualization, Project Management, Chinese, Cadence Virtuoso, Optoelectronics, Semiconductor Industry, Physical Design, Fiber Optics, SystemVerilog, TCL, Product Management, Perl, Electronics, Cadence, NFS, Linux System..., JavaScript, HTML, Virtual Desktop..., Data Management, BiCMOS, BJT, Semiconductor Packaging, Semiconductor Failure..., Optical Communications, Isolators, Relational Databases, Human Computer..., Compound Semiconductors
Education
Stanford University 2006 — 2009
Stanford Certified Project Manager
National University of Singapore 1991 — 1994
Master of Engineering (MEng)
National University of Singapore 1987 — 1991
Bachelor of Engineering (BEng)
Cadence Design Systems November 2011 - Present
Cadence Design Systems October 2007 - Present
Cadence Design Systems March 2001 - October 2007
Agilent Technologies 1998 - 2001
Hewlett-Packard 1997 - 2001
Hewlett-Packard May 1994 - 1997
Skills
EDA, IC, Mixed Signal, Usability, Semiconductors, Analog, Integrated Circuit..., Product Engineering, R&D, Unix, Analog Circuit Design, ASIC, Simulations, Verilog, CMOS, SoC, Debugging, Functional Verification, VLSI, Virtualization, Project Management, Chinese, Cadence Virtuoso, Optoelectronics, Semiconductor Industry, Physical Design, Fiber Optics, SystemVerilog, TCL, Product Management, Perl, Electronics, Cadence, NFS, Linux System..., JavaScript, HTML, Virtual Desktop..., Data Management, BiCMOS, BJT, Semiconductor Packaging, Semiconductor Failure..., Optical Communications, Isolators, Relational Databases, Human Computer..., Compound Semiconductors
Education
Stanford University 2006 — 2009
Stanford Certified Project Manager
National University of Singapore 1991 — 1994
Master of Engineering (MEng)
National University of Singapore 1987 — 1991
Bachelor of Engineering (BEng)
Karamveer Yadav Karamveer Yadav's Cadence Design Systems Experience June 2014 - Present
Job Principal Engineer , IP solution at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems June 2014 - Present
INEDA SYSTEMS December 2010 - May 2014
AMD May 2007 - December 2010
Freescale Semiconductor March 2005 - April 2007
DCM Technologies 2003 - 2005
Skills
SystemVerilog, ASIC, Verilog, SoC, Functional Verification, VLSI, RTL design, Static Timing Analysis, AMBA AHB, Formal Verification, EDA, RTL coding, UVM, Architecture, NCSim, SATA, FPGA, Open Verification..., Logic Synthesis, TCL, Debugging, ModelSim, Integrated Circuit..., Timing Closure, Logic Design, Physical Design, ARM, Low-power Design, PCIe, Primetime, I/O Virtualization, VHDL, Microprocessors, USB, RTL Design, RTL Coding
Education
National Institute of Technology Kurukshetra 1999 — 2003
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
SDAV
Cadence Design Systems June 2014 - Present
INEDA SYSTEMS December 2010 - May 2014
AMD May 2007 - December 2010
Freescale Semiconductor March 2005 - April 2007
DCM Technologies 2003 - 2005
Skills
SystemVerilog, ASIC, Verilog, SoC, Functional Verification, VLSI, RTL design, Static Timing Analysis, AMBA AHB, Formal Verification, EDA, RTL coding, UVM, Architecture, NCSim, SATA, FPGA, Open Verification..., Logic Synthesis, TCL, Debugging, ModelSim, Integrated Circuit..., Timing Closure, Logic Design, Physical Design, ARM, Low-power Design, PCIe, Primetime, I/O Virtualization, VHDL, Microprocessors, USB, RTL Design, RTL Coding
Education
National Institute of Technology Kurukshetra 1999 — 2003
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
SDAV
Oleg Kulikov Oleg Kulikov's Cadence Design Systems Experience May 2004 - March 2006
Job Hardware and Software Engineer at Oracle
Industry Computer Software
Experience
Oracle October 2012 - Present
Nangate April 2006 - September 2012
Cadence Design Systems May 2004 - March 2006
Geolink Consulting June 2003 - May 2004
EDAMS January 2002 - April 2003
Skills
EDA, Perl, C++, C, Qt, SPICE, VLSI, Linux, Semiconductors, R&D, Cadence Virtuoso, IC, Algorithms, Integrated Circuit..., Unix, Software Development, ASIC, Programming, TCL, Verilog
Education
National Research University of Electronic Technology (MIET) 1992 — 1999
Ph.D., Computer Science
Oracle October 2012 - Present
Nangate April 2006 - September 2012
Cadence Design Systems May 2004 - March 2006
Geolink Consulting June 2003 - May 2004
EDAMS January 2002 - April 2003
Skills
EDA, Perl, C++, C, Qt, SPICE, VLSI, Linux, Semiconductors, R&D, Cadence Virtuoso, IC, Algorithms, Integrated Circuit..., Unix, Software Development, ASIC, Programming, TCL, Verilog
Education
National Research University of Electronic Technology (MIET) 1992 — 1999
Ph.D., Computer Science
Paul Schnitzler Paul Schnitzler's Cadence Design Systems Experience 1997 - 1998
Job Successful Change Management—Key to business success
Industry Management Consulting
Experience
USF Department of Industrial and Management Systems Engineering August 2005 - Present
MovePeopletoAction 2011 - Present
P S & A April 2001 - Present
One-to-One Networks 2001 - 2004
ZMedia 2000 - 2001
Coastcom 1999 - 2000
Cadence Design Systems 1997 - 1998
Time Inc Magazine Company 1989 - 1991
RCA Laboratories 1979 - 1985
Bell Laboratories 1972 - 1979
Skills
Cross-functional Team..., Change Management, Program Management, Project Management, Management Consulting, Engineering, Strategic Planning, Six Sigma, Matlab, Start-ups, Business Strategy, Entrepreneurship, Leadership, Public Speaking, Business Development, Marketing, Organizational..., Statistics, Coaching, Business Planning, Simulations, Data Analysis, Market Research, New Business Development, Management, Process Engineering, Operations Research, Research, Product Development, Electronics, Engineering Management, Mergers & Acquisitions, Project Planning, Leadership Development, Strategy, Pspice, Team Building, Wireless, Energy, Executive Management, Process Improvement, Manufacturing, Integration, Analysis, Business Process..., Sales, Telecommunications, Proposal Writing, Team Leadership, Consulting
Education
Polytechnic Institute of NYU
Ph.D. (E.E.)
New York University
BSEE, MSEE
USF Department of Industrial and Management Systems Engineering August 2005 - Present
MovePeopletoAction 2011 - Present
P S & A April 2001 - Present
One-to-One Networks 2001 - 2004
ZMedia 2000 - 2001
Coastcom 1999 - 2000
Cadence Design Systems 1997 - 1998
Time Inc Magazine Company 1989 - 1991
RCA Laboratories 1979 - 1985
Bell Laboratories 1972 - 1979
Skills
Cross-functional Team..., Change Management, Program Management, Project Management, Management Consulting, Engineering, Strategic Planning, Six Sigma, Matlab, Start-ups, Business Strategy, Entrepreneurship, Leadership, Public Speaking, Business Development, Marketing, Organizational..., Statistics, Coaching, Business Planning, Simulations, Data Analysis, Market Research, New Business Development, Management, Process Engineering, Operations Research, Research, Product Development, Electronics, Engineering Management, Mergers & Acquisitions, Project Planning, Leadership Development, Strategy, Pspice, Team Building, Wireless, Energy, Executive Management, Process Improvement, Manufacturing, Integration, Analysis, Business Process..., Sales, Telecommunications, Proposal Writing, Team Leadership, Consulting
Education
Polytechnic Institute of NYU
Ph.D. (E.E.)
New York University
BSEE, MSEE
Noah Sennert's Cadence Design Systems Experience December 2013 - May 2014
Job Associate Engineer at ONUG Communications, Inc.
Industry Computer Hardware
Experience
ONUG Communications, Inc. July 2015 - Present
EMC December 2014 - December 2014
Cadence Design Systems December 2013 - May 2014
Cree October 2013 - December 2013
Skills
ASIC, Computer Hardware, Printers, Windows XP, Operating Systems, Hardware, Windows
Education
North Carolina State University 2009 — 2013
Bachelor's Degree, Electrical and Electronics Engineering
ONUG Communications, Inc. July 2015 - Present
EMC December 2014 - December 2014
Cadence Design Systems December 2013 - May 2014
Cree October 2013 - December 2013
Skills
ASIC, Computer Hardware, Printers, Windows XP, Operating Systems, Hardware, Windows
Education
North Carolina State University 2009 — 2013
Bachelor's Degree, Electrical and Electronics Engineering
Hsiao-Ping Tseng's Cadence Design Systems Experience January 1998 - April 1998
Job Staff Engineer at Linkedin Relevance Science
Industry Internet
Experience
LinkedIn May 2014 - Present
Reflektion August 2012 - May 2014
Synopsys April 2012 - August 2012
Magma Design Automation May 1998 - April 2012
Cadence Design Systems January 1998 - April 1998
Skills
Machine Learning, Data Mining, Recommender Systems, Predictive Analytics, Predictive Modeling, Scalability, Statistical Modeling, Big Data, Big Data Analytics, Information Retrieval, Apache Pig, Hadoop, Algorithms, Python, MongoDB, Java, C++, Optimization, MovieMaker, Distributed Systems
Education
University of Washington 1993 — 1997
Ph.D., Electrical Engineering
National Taiwan University 1987 — 1991
B.S., Physics
Taipei Jianguo High School 1984 — 1987
Taipei Jianguo High School
LinkedIn May 2014 - Present
Reflektion August 2012 - May 2014
Synopsys April 2012 - August 2012
Magma Design Automation May 1998 - April 2012
Cadence Design Systems January 1998 - April 1998
Skills
Machine Learning, Data Mining, Recommender Systems, Predictive Analytics, Predictive Modeling, Scalability, Statistical Modeling, Big Data, Big Data Analytics, Information Retrieval, Apache Pig, Hadoop, Algorithms, Python, MongoDB, Java, C++, Optimization, MovieMaker, Distributed Systems
Education
University of Washington 1993 — 1997
Ph.D., Electrical Engineering
National Taiwan University 1987 — 1991
B.S., Physics
Taipei Jianguo High School 1984 — 1987
Taipei Jianguo High School
Anshul Mittal Anshul Mittal's Cadence Design Systems Experience July 2010 - December 2012
Job Project Leader, Applications Development at Oracle
Industry Information Technology and Services
Experience
Oracle May 2015 - Present
Oracle December 2012 - Present
Cadence Design Systems July 2010 - December 2012
Columbia University March 2010 - July 2010
University of Florida August 2008 - December 2009
Barclays Capital June 2009 - August 2009
CHREC lab, University of Florida August 2008 - April 2009
Hughes Systique Corporation June 2007 - July 2008
National Physical Laboratory December 2006 - June 2007
Allen-Bradley May 2005 - July 2005
Skills
Verilog, C, VHDL, Perl, Algorithms
Education
University of Florida 2008 — 2009
MS, Electrical and Computer Engineering
Netaji Subhas Institute of Technology 2003 — 2007
BE, Electronics and Communication Engineering
Sardar Patel Vidyalaya 1994 — 2003
High School
Oracle May 2015 - Present
Oracle December 2012 - Present
Cadence Design Systems July 2010 - December 2012
Columbia University March 2010 - July 2010
University of Florida August 2008 - December 2009
Barclays Capital June 2009 - August 2009
CHREC lab, University of Florida August 2008 - April 2009
Hughes Systique Corporation June 2007 - July 2008
National Physical Laboratory December 2006 - June 2007
Allen-Bradley May 2005 - July 2005
Skills
Verilog, C, VHDL, Perl, Algorithms
Education
University of Florida 2008 — 2009
MS, Electrical and Computer Engineering
Netaji Subhas Institute of Technology 2003 — 2007
BE, Electronics and Communication Engineering
Sardar Patel Vidyalaya 1994 — 2003
High School
suprio bhattacharya suprio bhattacharya's Cadence Design Systems Experience May 2011 - August 2013
Job Graphics Hardware Engineer at Intel Corporation
Industry Semiconductors
Experience
North Carolina State University August 2013 - July 2015
Intel Corporation May 2014 - December 2014
Cadence Design Systems May 2011 - August 2013
Wipro Technologies June 2010 - May 2011
Manav Rachna College of Engineering 2009 - 2010
Freescale Semiconductor May 2007 - March 2009
HCL Technologies March 2006 - April 2007
Skills
Scripting, Digital Signal..., Static Timing Analysis, Integrated Circuit..., VLSI, SoC, Logic Synthesis, EDA, RTL Design, Verilog, ASIC, TCL, VHDL, Perl
Education
North Carolina State University 2013 — 2015
Master of Science (MS), Electrical and Electronics Engineering
Semiconductor Complex Limited - VEDANT, Gurgaon 2005 — 2006
PG Diploma, VLSI Design
University of Pune 2001 — 2005
B.E., Electronics & Telecom
North Carolina State University August 2013 - July 2015
Intel Corporation May 2014 - December 2014
Cadence Design Systems May 2011 - August 2013
Wipro Technologies June 2010 - May 2011
Manav Rachna College of Engineering 2009 - 2010
Freescale Semiconductor May 2007 - March 2009
HCL Technologies March 2006 - April 2007
Skills
Scripting, Digital Signal..., Static Timing Analysis, Integrated Circuit..., VLSI, SoC, Logic Synthesis, EDA, RTL Design, Verilog, ASIC, TCL, VHDL, Perl
Education
North Carolina State University 2013 — 2015
Master of Science (MS), Electrical and Electronics Engineering
Semiconductor Complex Limited - VEDANT, Gurgaon 2005 — 2006
PG Diploma, VLSI Design
University of Pune 2001 — 2005
B.E., Electronics & Telecom
Ching-Cheng Chai Ching-Cheng Chai's Cadence Design Systems Experience 1990 - 1992
Job Marketing & Business Development Professional
Industry Semiconductors
Experience
United Microelectronics Corporation (UMC Group, USA) 2012 - Present
TSMC 2005 - 2011
TSMC 2004 - 2005
Xilinx 1994 - 2000
Cadence Design Systems 1990 - 1992
DIgital Equipment Corporation 1985 - 1988
Skills
Engineering management, Program Management, Silicon IP Marketing, Engineering Management, Business Development, Semiconductors
Education
National Taiwan University
BS, EE
SUNY Stony Brook
MS, Computer Science
United Microelectronics Corporation (UMC Group, USA) 2012 - Present
TSMC 2005 - 2011
TSMC 2004 - 2005
Xilinx 1994 - 2000
Cadence Design Systems 1990 - 1992
DIgital Equipment Corporation 1985 - 1988
Skills
Engineering management, Program Management, Silicon IP Marketing, Engineering Management, Business Development, Semiconductors
Education
National Taiwan University
BS, EE
SUNY Stony Brook
MS, Computer Science
Casey Thé Casey Thé's Cadence Design Systems Experience January 2002 - March 2006
Job
Industry Semiconductors
Experience
Synopsys November 2013 - Present
Synapse Design May 2011 - November 2013
Silverline Design January 2009 - May 2011
elMobile Inc. October 2008 - December 2010
Magma Design Automation September 2007 - September 2008
Rio Design Automation May 2006 - September 2007
Cadence Design Systems January 2002 - March 2006
Silicon Perspective Corp March 2000 - December 2001
Synopsys September 1997 - March 2000
Avant! September 1994 - September 1997
Skills
EDA, TCL, Algorithms, Java, Python, MySQL, Perl, C, C++, Unix, ASIC, PHP, Programming, Enterprise Software, Software Development, SoC, Verilog
Education
UCSC Extension 2010 — 2010
Certificate With Honors
The University of Texas at Austin 1987 — 1991
Ph.D.
National Taiwan University 1978 — 1982
BSE
Synopsys November 2013 - Present
Synapse Design May 2011 - November 2013
Silverline Design January 2009 - May 2011
elMobile Inc. October 2008 - December 2010
Magma Design Automation September 2007 - September 2008
Rio Design Automation May 2006 - September 2007
Cadence Design Systems January 2002 - March 2006
Silicon Perspective Corp March 2000 - December 2001
Synopsys September 1997 - March 2000
Avant! September 1994 - September 1997
Skills
EDA, TCL, Algorithms, Java, Python, MySQL, Perl, C, C++, Unix, ASIC, PHP, Programming, Enterprise Software, Software Development, SoC, Verilog
Education
UCSC Extension 2010 — 2010
Certificate With Honors
The University of Texas at Austin 1987 — 1991
Ph.D.
National Taiwan University 1978 — 1982
BSE
Ambrish Varma Ambrish Varma's Cadence Design Systems Experience July 2010 - Present
Job Member of Consulting Staff at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2010 - Present
Cadence Design Systems January 2007 - July 2010
Cadence Design Systems May 2005 - August 2005
Alcatel February 2001 - April 2002
IBM May 2000 - August 2000
Skills
Signal Integrity, EDA, SERDES, Debugging, AMI, Simulations, SystemVerilog, Functional Verification, FPGA, Physical Design, ModelSim, IBIS, SPICE, ASIC, Verilog, Perl, SoC, Semiconductors, C, IC, VHDL, Hardware Architecture, Embedded Systems
Education
North Carolina State University 2002 — 2006
PhD, Computer Engineering
North Carolina State University 2000 — 2001
MS, Computer Engineering
University of Louisiana at Lafayette 1999 — 1999
MS, Comp. Engg
St. Joseph's College, Allahabad 1980 — 1992
Cadence Design Systems July 2010 - Present
Cadence Design Systems January 2007 - July 2010
Cadence Design Systems May 2005 - August 2005
Alcatel February 2001 - April 2002
IBM May 2000 - August 2000
Skills
Signal Integrity, EDA, SERDES, Debugging, AMI, Simulations, SystemVerilog, Functional Verification, FPGA, Physical Design, ModelSim, IBIS, SPICE, ASIC, Verilog, Perl, SoC, Semiconductors, C, IC, VHDL, Hardware Architecture, Embedded Systems
Education
North Carolina State University 2002 — 2006
PhD, Computer Engineering
North Carolina State University 2000 — 2001
MS, Computer Engineering
University of Louisiana at Lafayette 1999 — 1999
MS, Comp. Engg
St. Joseph's College, Allahabad 1980 — 1992
Jim Pfeifer Jim Pfeifer's Cadence Design Systems Experience 1994 - 1999
Job Solutions Architect at meltmedia
Industry Computer Software
Experience
meltmedia July 2015 - Present
Packet Video 2005 - June 2015
Zoran 2004 - 2005
PacketVideo 2000 - 2004
Aptix 1998 - 1999
Cadence Design Systems 1994 - 1999
TRW - Aerospace 1987 - 1994
Skills
Embedded Systems, Mobile Devices, Mobile Applications, Wireless, Semiconductors, DRM, Product Management, Streaming Media, Embedded Software, Mobile Communications, Mobile Technology, Product Marketing, FPGA, Android, Strategic Partnerships, ASIC, Product Development, Verilog, VHDL, Signal Processing, Team Leadership, Pre-sales, Go-to-market Strategy, Simulations, System Architecture, Digital Signal..., Debugging, Music, Music Production
Education
University of Southern California 1987 — 1989
MSEE, Electrical Engineering
New Mexico State University 1981 — 1987
BSEE, Electrical Engineering
meltmedia July 2015 - Present
Packet Video 2005 - June 2015
Zoran 2004 - 2005
PacketVideo 2000 - 2004
Aptix 1998 - 1999
Cadence Design Systems 1994 - 1999
TRW - Aerospace 1987 - 1994
Skills
Embedded Systems, Mobile Devices, Mobile Applications, Wireless, Semiconductors, DRM, Product Management, Streaming Media, Embedded Software, Mobile Communications, Mobile Technology, Product Marketing, FPGA, Android, Strategic Partnerships, ASIC, Product Development, Verilog, VHDL, Signal Processing, Team Leadership, Pre-sales, Go-to-market Strategy, Simulations, System Architecture, Digital Signal..., Debugging, Music, Music Production
Education
University of Southern California 1987 — 1989
MSEE, Electrical Engineering
New Mexico State University 1981 — 1987
BSEE, Electrical Engineering
Kyle Medero Kyle Medero's Cadence Design Systems Experience January 2013 - Present
Job Design Engineer, SoC Implementation Services at Cadence Design Systems
Industry Computer Hardware
Experience
Cadence Design Systems January 2013 - Present
Schneider Electric January 2012 - November 2012
Skills
Electrical Engineering, Modbus, Engineering, Electronics
Education
North Carolina State University 2008 — 2011
BSEE, Electrical Engineering
Cadence Design Systems January 2013 - Present
Schneider Electric January 2012 - November 2012
Skills
Electrical Engineering, Modbus, Engineering, Electronics
Education
North Carolina State University 2008 — 2011
BSEE, Electrical Engineering
Saghir Shaikh Saghir Shaikh's Cadence Design Systems Experience January 2007 - November 2008
Job Senior Principal IC Design Scientist at Broadcom
Industry Semiconductors
Experience
Broadcom July 2009 - Present
IEEE TTTC 2001 - 2011
Xicret Services, Inc. December 2008 - January 2009
Cadence Design Systems January 2007 - November 2008
Sun Microsystems January 2005 - January 2007
Intel July 2000 - January 2005
level one January 1997 - June 2000
Skills
C++, Design for Manufacturing, Test Automation, Debugging, Mixed Signal, Analog Design, DFT, Testing, SoC, Analog, Computer Architecture, Integrated Circuit..., Analog Circuit Design, Cadence, ASIC, FPGA, Perl, VLSI, Verilog, Low-power Design, RTL coding, Embedded Systems, Simulations, EDA, Semiconductors, Logic Synthesis, IC, Digital Signal..., VHDL, C, JTAG
Education
The University of Texas at Austin 1992 — 1996
Ph.D., Computer Engineering
University of California, San Diego 2009 — 2010
Specialized Certificate, RF Engineering
The University of Texas at Austin 1990 — 1991
MSEE, Electrical Engineering/Biomedical
NED University of Engineering and Technology 1983 — 1989
BE, Computer Engineering
Broadcom July 2009 - Present
IEEE TTTC 2001 - 2011
Xicret Services, Inc. December 2008 - January 2009
Cadence Design Systems January 2007 - November 2008
Sun Microsystems January 2005 - January 2007
Intel July 2000 - January 2005
level one January 1997 - June 2000
Skills
C++, Design for Manufacturing, Test Automation, Debugging, Mixed Signal, Analog Design, DFT, Testing, SoC, Analog, Computer Architecture, Integrated Circuit..., Analog Circuit Design, Cadence, ASIC, FPGA, Perl, VLSI, Verilog, Low-power Design, RTL coding, Embedded Systems, Simulations, EDA, Semiconductors, Logic Synthesis, IC, Digital Signal..., VHDL, C, JTAG
Education
The University of Texas at Austin 1992 — 1996
Ph.D., Computer Engineering
University of California, San Diego 2009 — 2010
Specialized Certificate, RF Engineering
The University of Texas at Austin 1990 — 1991
MSEE, Electrical Engineering/Biomedical
NED University of Engineering and Technology 1983 — 1989
BE, Computer Engineering
Ed Harcourt Ed Harcourt's Cadence Design Systems Experience February 1996 - June 2003
Job Associate Professor at St.Lawrence University
Industry Computer Software
Experience
St.Lawrence University August 2003 - Present
NexID Biometrics December 2012 - Present
Cadence Design Systems February 1996 - June 2003
Chalmers University of Technology August 1994 - December 1995
Skills
Embedded Systems, ARM Cortex-M, C, EDA, Python, LaTeX, Java, Linux, Perl, C++, MySQL, PHP, JavaScript, Distributed Systems, Eclipse, Programming, HTML, Tensilica
Education
North Carolina State University 1986 — 1994
Ph.D., Computer Science
North Carolina State University 1986 — 1994
M.S., Computer Engineering
State University of New York College at Plattsburgh 1982 — 1986
B.S., Computer Science
St.Lawrence University August 2003 - Present
NexID Biometrics December 2012 - Present
Cadence Design Systems February 1996 - June 2003
Chalmers University of Technology August 1994 - December 1995
Skills
Embedded Systems, ARM Cortex-M, C, EDA, Python, LaTeX, Java, Linux, Perl, C++, MySQL, PHP, JavaScript, Distributed Systems, Eclipse, Programming, HTML, Tensilica
Education
North Carolina State University 1986 — 1994
Ph.D., Computer Science
North Carolina State University 1986 — 1994
M.S., Computer Engineering
State University of New York College at Plattsburgh 1982 — 1986
B.S., Computer Science
Rupal Mehta Rupal Mehta's Cadence Design Systems Experience 2003 - 2005
Job Information Services at County of San Mateo
Industry Government Administration
Experience
County of San Mateo April 2014 - Present
County of Santa Clara January 2013 - April 2014
City and County of San Francisco January 2011 - January 2013
Zume Life, Inc. 2007 - 2009
Cadence Design Systems 2003 - 2005
eBay 2001 - 2003
Synopsys 1998 - 2000
Apple Inc. 1990 - 1997
Tandem Computers 1986 - 1989
Electronic Support Systems 1983 - 1986
Skills
Cross-functional Team..., Start-ups, Project Management, Analysis, Program Management, Strategic Planning, Vendor Management, Integration, Management, Strategic Partnerships, Training
Education
National University
Master's Public Administration
Rutgers University-New Brunswick
BS, computer science
County of San Mateo April 2014 - Present
County of Santa Clara January 2013 - April 2014
City and County of San Francisco January 2011 - January 2013
Zume Life, Inc. 2007 - 2009
Cadence Design Systems 2003 - 2005
eBay 2001 - 2003
Synopsys 1998 - 2000
Apple Inc. 1990 - 1997
Tandem Computers 1986 - 1989
Electronic Support Systems 1983 - 1986
Skills
Cross-functional Team..., Start-ups, Project Management, Analysis, Program Management, Strategic Planning, Vendor Management, Integration, Management, Strategic Partnerships, Training
Education
National University
Master's Public Administration
Rutgers University-New Brunswick
BS, computer science
Chandrashekar Ramanna Chandrashekar Ramanna's Cadence Design Systems Experience 2008 - 2010
Job Senior Analog Engineer at Marvell Semiconductor
Industry Semiconductors
Experience
Marvell Semiconductor April 2011 - Present
Solarflare Communications December 2010 - April 2011
Cadence Design Systems 2008 - 2010
Ericsson May 2007 - August 2007
Defence Research and Development Organisation 2003 - 2004
Skills
Analog Circuit Design, Mixed Signal, Verilog, Cadence Virtuoso, EDA, VLSI, CMOS, Integrated Circuit..., Analog, Cadence, ASIC, PLL
Education
North Carolina State University 2006 — 2007
Masters, Electrical Engineering
National Institute of Technology Calicut 1999 — 2003
B.Tech, Electronics and Communication Engineering
Marvell Semiconductor April 2011 - Present
Solarflare Communications December 2010 - April 2011
Cadence Design Systems 2008 - 2010
Ericsson May 2007 - August 2007
Defence Research and Development Organisation 2003 - 2004
Skills
Analog Circuit Design, Mixed Signal, Verilog, Cadence Virtuoso, EDA, VLSI, CMOS, Integrated Circuit..., Analog, Cadence, ASIC, PLL
Education
North Carolina State University 2006 — 2007
Masters, Electrical Engineering
National Institute of Technology Calicut 1999 — 2003
B.Tech, Electronics and Communication Engineering
Sunil Thattarakkal Sunil Thattarakkal's Cadence Design Systems Experience May 2014 - Present
Job Application Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems May 2014 - Present
Atoptech March 2010 - April 2014
Symmid Semiconductor Technology October 2006 - May 2009
Information Technology Program, USC October 2004 - February 2006
I2 Technologies June 2003 - January 2004
Skills
Place & Route, Timing Closure, Floorplanning, Static Timing Analysis, Verilog, Physical Design, EDA, Primetime, ASIC, SoC, Logic Synthesis, LVS, DRC, Clock Tree Synthesis, Formal Verification, RTL coding, Timing, Cadence
Education
University of Southern California 2004 — 2005
MS, Electrical Engineering (VLSI Design)
National Institute of Technology Calicut 1998 — 2002
B.Tech, Electrical & Electronics Engineering
Cadence Design Systems May 2014 - Present
Atoptech March 2010 - April 2014
Symmid Semiconductor Technology October 2006 - May 2009
Information Technology Program, USC October 2004 - February 2006
I2 Technologies June 2003 - January 2004
Skills
Place & Route, Timing Closure, Floorplanning, Static Timing Analysis, Verilog, Physical Design, EDA, Primetime, ASIC, SoC, Logic Synthesis, LVS, DRC, Clock Tree Synthesis, Formal Verification, RTL coding, Timing, Cadence
Education
University of Southern California 2004 — 2005
MS, Electrical Engineering (VLSI Design)
National Institute of Technology Calicut 1998 — 2002
B.Tech, Electrical & Electronics Engineering
Pawel Chadzynski Pawel Chadzynski's Cadence Design Systems Experience 1992 - 1998
Job Senior Director, Product Management at Aras Corporation
Industry Computer Software
Experience
Aras Corporation 2013 - Present
Mobile iSolutions January 2012 - 2013
Pawel Z. Chadzynski January 2010 - March 2012
PTC (Parametric Technology Corporation) 2004 - October 2009
OHIO Design Automation Corp. 1998 - 2004
Cadence Design Systems 1992 - 1998
Automated Reasoning Corp. 1988 - 1992
Algorex Corp. 1984 - 1988
Photocircuits Corp. (a.k.a. Multiwire, PCK Technology, Kollmorgen) 1972 - 1984
Education
New York University - Polytechnic School of Engineering 1983 — 1987
MS - Technology Management
New York University - Polytechnic School of Engineering 1972 — 1979
BS/EE
Aras Corporation 2013 - Present
Mobile iSolutions January 2012 - 2013
Pawel Z. Chadzynski January 2010 - March 2012
PTC (Parametric Technology Corporation) 2004 - October 2009
OHIO Design Automation Corp. 1998 - 2004
Cadence Design Systems 1992 - 1998
Automated Reasoning Corp. 1988 - 1992
Algorex Corp. 1984 - 1988
Photocircuits Corp. (a.k.a. Multiwire, PCK Technology, Kollmorgen) 1972 - 1984
Education
New York University - Polytechnic School of Engineering 1983 — 1987
MS - Technology Management
New York University - Polytechnic School of Engineering 1972 — 1979
BS/EE
Sabahat Ashraf Sabahat Ashraf's Cadence Design Systems Experience April 2000 - October 2000
Job Communicator
Industry Public Relations and Communications
Experience
iFaqeer Communications April 2008 - Present
SA Relief August 2005 - Present
SystemGuru Inc. September 2003 - March 2012
Cavium Networks September 2004 - April 2009
Virage Logic Corporation July 2001 - October 2003
Cisco Systems October 2000 - July 2001
Cadence Design Systems April 2000 - October 2000
Mentor Graphics Corporation December 1996 - December 1999
Fitch Inc. June 1995 - December 1995
ITIM Associates (Pvt.) Ltd. February 1994 - July 1994
Skills
Technical Writing, Training, Editing, Visio, Unix, Technical Documentation, Product Management, Software, HTML, Online Help, Wikis, FrameMaker, Software Documentation, Technical Communication, Single Sourcing, Social Media, Adobe Acrobat, Manuals, Management, Content Management, Blogging, Content Development, Networking, Information Design, Web 2.0, SnagIt, Web Content, Information Architecture, New Media, CMS, Web Content Management, Content Strategy, Usability Testing, Knowledge Management, User Experience, Mobile Applications, RoboHelp, Dreamweaver
Education
Rensselaer Polytechnic Institute 1994 — 1996
MS, Technical Communication
NED University of Engineering and Technology 1988 — 1993
BE, Computer Systems Enginering
Adamjee Science College 1985 — 1987
High School Certificate, Pre-Engineering
Federal Government College, Sokoto
iFaqeer Communications April 2008 - Present
SA Relief August 2005 - Present
SystemGuru Inc. September 2003 - March 2012
Cavium Networks September 2004 - April 2009
Virage Logic Corporation July 2001 - October 2003
Cisco Systems October 2000 - July 2001
Cadence Design Systems April 2000 - October 2000
Mentor Graphics Corporation December 1996 - December 1999
Fitch Inc. June 1995 - December 1995
ITIM Associates (Pvt.) Ltd. February 1994 - July 1994
Skills
Technical Writing, Training, Editing, Visio, Unix, Technical Documentation, Product Management, Software, HTML, Online Help, Wikis, FrameMaker, Software Documentation, Technical Communication, Single Sourcing, Social Media, Adobe Acrobat, Manuals, Management, Content Management, Blogging, Content Development, Networking, Information Design, Web 2.0, SnagIt, Web Content, Information Architecture, New Media, CMS, Web Content Management, Content Strategy, Usability Testing, Knowledge Management, User Experience, Mobile Applications, RoboHelp, Dreamweaver
Education
Rensselaer Polytechnic Institute 1994 — 1996
MS, Technical Communication
NED University of Engineering and Technology 1988 — 1993
BE, Computer Systems Enginering
Adamjee Science College 1985 — 1987
High School Certificate, Pre-Engineering
Federal Government College, Sokoto
Chia-Cheng (Jeremy) Tso Chia-Cheng (Jeremy) Tso's Cadence Design Systems Experience July 2013 - September 2013
Job Student at Texas A&M University
Industry Computer Software
Experience
Cadence Design Systems July 2013 - September 2013
Cadence Design Systems September 2011 - July 2013
National Taiwan University February 2009 - August 2009
Skills
C++, C, Verilog, Linux, Algorithms, Python, Programming, Perl, Software Development, GCC, EDA, Vim, HTML, CSS, Software Engineering
Education
Texas A&M University 2015 — 2017
Master of Science (M.S.), Computer Science
National Taiwan University 2008 — 2010
Master of Science (M.S.), Electronic Engineering, 3.8/4.0
National Taiwan University 2004 — 2008
Bachelor of Science (B.S.), Electrical Engineering, 3.85/4.0
Cadence Design Systems July 2013 - September 2013
Cadence Design Systems September 2011 - July 2013
National Taiwan University February 2009 - August 2009
Skills
C++, C, Verilog, Linux, Algorithms, Python, Programming, Perl, Software Development, GCC, EDA, Vim, HTML, CSS, Software Engineering
Education
Texas A&M University 2015 — 2017
Master of Science (M.S.), Computer Science
National Taiwan University 2008 — 2010
Master of Science (M.S.), Electronic Engineering, 3.8/4.0
National Taiwan University 2004 — 2008
Bachelor of Science (B.S.), Electrical Engineering, 3.85/4.0
Poorna Volety Poorna Volety's Cadence Design Systems Experience February 2007 - July 2007
Job Principal Consultant SAP BI/HANA
Industry Information Technology and Services
Experience
Global Intelli Biz Inc June 2005 - Present
SAP GDC 2012 - 2012
Colorado Department of Transportation May 2009 - September 2011
PGP Corporation March 2009 - May 2009
eBay August 2008 - March 2009
AMAT 2007 - 2008
Applied Materials 2007 - 2008
Spansion 2007 - 2008
Cadence Design Systems February 2007 - July 2007
Pioneer Electronics September 2006 - January 2007
Skills
SAP ERP, SAP BI, SAP BW, Business Objects, ABAP, SAP R/3, SAP, SAP Netweaver, SD, SAP Implementation, Business Intelligence, ECC, ERP, SAP Portal, SAP BPC, Consulting, Business Analysis, BPCS, Master Data Management, Business Process, Data Migration
Education
Newport University 1992 — 1994
MBA, Finance
Osmania University 1989 — 1994
Bachelors
Global Intelli Biz Inc June 2005 - Present
SAP GDC 2012 - 2012
Colorado Department of Transportation May 2009 - September 2011
PGP Corporation March 2009 - May 2009
eBay August 2008 - March 2009
AMAT 2007 - 2008
Applied Materials 2007 - 2008
Spansion 2007 - 2008
Cadence Design Systems February 2007 - July 2007
Pioneer Electronics September 2006 - January 2007
Skills
SAP ERP, SAP BI, SAP BW, Business Objects, ABAP, SAP R/3, SAP, SAP Netweaver, SD, SAP Implementation, Business Intelligence, ECC, ERP, SAP Portal, SAP BPC, Consulting, Business Analysis, BPCS, Master Data Management, Business Process, Data Migration
Education
Newport University 1992 — 1994
MBA, Finance
Osmania University 1989 — 1994
Bachelors
Srikanth Vijayaraghavan's Cadence Design Systems Experience January 2011 - June 2011
Job
Industry Semiconductors
Experience
Hewlett-Packard April 2015 - Present
Dell July 2011 - March 2015
Cadence Design Systems January 2011 - June 2011
Synopsys June 2006 - December 2010
Synopsys Inc December 1997 - May 2006
Viewlogic corporation August 1997 - November 1997
Skills
Product Requirements, SaaS, Enterprise Software, Cloud Computing, Semiconductors, Product Management, Product Marketing, Product Lifecycle..., Go-to-market Strategy, Product Planning, EDA, Cross-functional Team..., Competitive Analysis, Messaging, Account Management, Business Strategy, Storage, Virtualization, Sales Enablement, Sales Process, Hardware, Strategy, Project Management, Pre-sales, SoC, Product Launch, Sales Operations, Product Development, Strategic Partnerships, Partner Management, Embedded Systems, Mobile Devices, Management, Business Alliances, Demand Generation, Start-ups, Technical Marketing, ASIC, Processors, IC, Professional Services, Strategic Alliances, Analytics, Positioning, Systems Management, Sales Engineering, Salesforce.com, Data Center, Solution Selling, Multi-channel Marketing
Education
The University of Texas at Austin - The Red McCombs School of Business 2007 — 2009
MBA, Focus on - Product Marketing, New Venture Creation and Customer Support
Northern Illinois University 1995 — 1997
M.S EE, ASIC/FPGA design and verification
National Institute of Technology Surat 1991 — 1995
B.E, Electronics and Communication
Hewlett-Packard April 2015 - Present
Dell July 2011 - March 2015
Cadence Design Systems January 2011 - June 2011
Synopsys June 2006 - December 2010
Synopsys Inc December 1997 - May 2006
Viewlogic corporation August 1997 - November 1997
Skills
Product Requirements, SaaS, Enterprise Software, Cloud Computing, Semiconductors, Product Management, Product Marketing, Product Lifecycle..., Go-to-market Strategy, Product Planning, EDA, Cross-functional Team..., Competitive Analysis, Messaging, Account Management, Business Strategy, Storage, Virtualization, Sales Enablement, Sales Process, Hardware, Strategy, Project Management, Pre-sales, SoC, Product Launch, Sales Operations, Product Development, Strategic Partnerships, Partner Management, Embedded Systems, Mobile Devices, Management, Business Alliances, Demand Generation, Start-ups, Technical Marketing, ASIC, Processors, IC, Professional Services, Strategic Alliances, Analytics, Positioning, Systems Management, Sales Engineering, Salesforce.com, Data Center, Solution Selling, Multi-channel Marketing
Education
The University of Texas at Austin - The Red McCombs School of Business 2007 — 2009
MBA, Focus on - Product Marketing, New Venture Creation and Customer Support
Northern Illinois University 1995 — 1997
M.S EE, ASIC/FPGA design and verification
National Institute of Technology Surat 1991 — 1995
B.E, Electronics and Communication
Chung-Do Yang Chung-Do Yang's Cadence Design Systems Experience September 2009 - Present
Job Senior Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems September 2009 - Present
SpringSoft USA Inc. November 2007 - September 2009
Nanovata Inc. January 2005 - November 2007
Mentor Graphics November 2002 - November 2004
Synopsys February 2002 - November 2002
Avanti January 1995 - February 2002
IBM February 1992 - January 1995
Education
Northwestern University 1987 — 1992
MS and Ph.D., EECS
National Chiao Tung University 1981 — 1985
BA, CS
Cadence Design Systems September 2009 - Present
SpringSoft USA Inc. November 2007 - September 2009
Nanovata Inc. January 2005 - November 2007
Mentor Graphics November 2002 - November 2004
Synopsys February 2002 - November 2002
Avanti January 1995 - February 2002
IBM February 1992 - January 1995
Education
Northwestern University 1987 — 1992
MS and Ph.D., EECS
National Chiao Tung University 1981 — 1985
BA, CS
Terry Perkinson Terry Perkinson's Cadence Design Systems Experience 2002 - 2004
Job Senior Technical Manager
Industry Computer Networking
Experience
IDT November 2011 - June 2015
Nethra Imaging July 2010 - November 2011
ARM 2004 - June 2010
Cadence Design Systems 2002 - 2004
Cadence Design Systems 2000 - 2002
IBM 1998 - 2000
Motorola 1995 - 1998
Skills
SERDES, Python, CYTHON, Semiconductors, Analog, ARM, IC, EDA, Software Development, ASIC, Hardware Architecture, Mixed Signal, Management, Product Management, Cadence, Embedded Systems, SoC, Debugging, Test Lab Management, Test Automation, Discrete Event..., Activity Based Costing, Monte Carlo Business..., Testing, Cross-functional Team..., Semiconductor Industry
Education
North Carolina State University 1991 — 1995
PhD, EE, 3.91
North Carolina State University 1987 — 1991
Bachelor’s Degree, BS Electrical Engineering, 4.00
IDT November 2011 - June 2015
Nethra Imaging July 2010 - November 2011
ARM 2004 - June 2010
Cadence Design Systems 2002 - 2004
Cadence Design Systems 2000 - 2002
IBM 1998 - 2000
Motorola 1995 - 1998
Skills
SERDES, Python, CYTHON, Semiconductors, Analog, ARM, IC, EDA, Software Development, ASIC, Hardware Architecture, Mixed Signal, Management, Product Management, Cadence, Embedded Systems, SoC, Debugging, Test Lab Management, Test Automation, Discrete Event..., Activity Based Costing, Monte Carlo Business..., Testing, Cross-functional Team..., Semiconductor Industry
Education
North Carolina State University 1991 — 1995
PhD, EE, 3.91
North Carolina State University 1987 — 1991
Bachelor’s Degree, BS Electrical Engineering, 4.00
Yi-Wei Lin Yi-Wei Lin's Cadence Design Systems Experience June 2015 - Present
Job Principal Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems June 2015 - Present
Apache Design Solutions November 2010 - May 2015
University of California, Santa Barbara April 2006 - September 2010
Synopsys July 2007 - September 2007
Giantplus Technology June 1999 - September 1999
Startek Engineering June 1997 - September 1997
Skills
VLSI, Verilog, EDA, Circuit Design, Algorithms, ASIC, IC, Computer Architecture, FPGA, Perl, Semiconductors, SoC, C++, Simulations, C, TCL
Education
University of California, Santa Barbara 2005 — 2010
Ph.D., Electrical and Computer Engineering
National Chiao Tung University 1997 — 2003
BS & MS, Electronics Engineering
NEHS
Cadence Design Systems June 2015 - Present
Apache Design Solutions November 2010 - May 2015
University of California, Santa Barbara April 2006 - September 2010
Synopsys July 2007 - September 2007
Giantplus Technology June 1999 - September 1999
Startek Engineering June 1997 - September 1997
Skills
VLSI, Verilog, EDA, Circuit Design, Algorithms, ASIC, IC, Computer Architecture, FPGA, Perl, Semiconductors, SoC, C++, Simulations, C, TCL
Education
University of California, Santa Barbara 2005 — 2010
Ph.D., Electrical and Computer Engineering
National Chiao Tung University 1997 — 2003
BS & MS, Electronics Engineering
NEHS
Jim House Jim House's Cadence Design Systems Experience May 2013 - Present
Job Principal Design/Verification Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems May 2013 - Present
Open-Silicon August 2010 - May 2013
Cisco November 2009 - July 2010
Qualcomm May 2009 - November 2009
ARM February 2009 - April 2009
ARM October 2006 - September 2008
AMCC 2001 - 2006
Nortel 1986 - 2001
Skills
ASIC, TCL, SystemVerilog, Cadence, Verilog
Education
North Carolina State University 1980 — 1986
Cadence Design Systems May 2013 - Present
Open-Silicon August 2010 - May 2013
Cisco November 2009 - July 2010
Qualcomm May 2009 - November 2009
ARM February 2009 - April 2009
ARM October 2006 - September 2008
AMCC 2001 - 2006
Nortel 1986 - 2001
Skills
ASIC, TCL, SystemVerilog, Cadence, Verilog
Education
North Carolina State University 1980 — 1986
Deepak Upadhyay Deepak Upadhyay's Cadence Design Systems Experience October 1999 - April 2007
Job Sr. Director IT, Engineering Systems and Support at Emulex
Industry Semiconductors
Experience
Emulex September 2012 - Present
Conexant October 2011 - September 2012
Conexant April 2007 - October 2011
Cadence Design Systems October 1999 - April 2007
Cadence Design Systems 1999 - 2007
EDS April 1999 - October 1999
Insight Solutions Inc. June 1997 - April 1999
Reuters India Pvt. Ltd. January 1997 - June 1997
Tata Consultancy Services December 1993 - December 1996
HCL Limited September 1990 - December 1993
Skills
Unix, Emerging Technologies, Cloud Computing, System Architecture, Virtualization, Enterprise Architecture, Architecture, Storage, Perl, Enterprise Software, Solaris, Integration, System Administration, Security, Oracle SQL, Troubleshooting, SAP R/3, Hardware, Infrastructure, Disaster Recovery, VMware, TCP/IP, Windows, Data Center, Information Technology, NAS, Operating Systems, Shell Scripting, Firewalls, DNS, SAN, IP, Switches, Testing, Servers, Technical Support
Education
IP3 CISSP Class 2011 — 2011
Narsee Monjee Institute of Management Studies 1993 — 1996
MMM
University of Mumbai 1993 — 1996
MMM, Marketing
University of Mumbai 1986 — 1990
BE, Electronics
St. Xavier's College 1985 — 1986
Emulex September 2012 - Present
Conexant October 2011 - September 2012
Conexant April 2007 - October 2011
Cadence Design Systems October 1999 - April 2007
Cadence Design Systems 1999 - 2007
EDS April 1999 - October 1999
Insight Solutions Inc. June 1997 - April 1999
Reuters India Pvt. Ltd. January 1997 - June 1997
Tata Consultancy Services December 1993 - December 1996
HCL Limited September 1990 - December 1993
Skills
Unix, Emerging Technologies, Cloud Computing, System Architecture, Virtualization, Enterprise Architecture, Architecture, Storage, Perl, Enterprise Software, Solaris, Integration, System Administration, Security, Oracle SQL, Troubleshooting, SAP R/3, Hardware, Infrastructure, Disaster Recovery, VMware, TCP/IP, Windows, Data Center, Information Technology, NAS, Operating Systems, Shell Scripting, Firewalls, DNS, SAN, IP, Switches, Testing, Servers, Technical Support
Education
IP3 CISSP Class 2011 — 2011
Narsee Monjee Institute of Management Studies 1993 — 1996
MMM
University of Mumbai 1993 — 1996
MMM, Marketing
University of Mumbai 1986 — 1990
BE, Electronics
St. Xavier's College 1985 — 1986
Daisy Chou, CISSP Daisy Chou, CISSP's Cadence Design Systems Experience October 1999 - November 2014
Job Lead Security Analyst at Ross Stores, Inc.
Industry Computer & Network Security
Experience
Cadence Design Systems October 1999 - November 2014
Fujitsu Systems and Business America October 1996 - October 1999
Galaxy Software Services Corporation February 1995 - March 1996
Information Builders June 1993 - February 1995
Skills
Information Security, Network Security, IPS, CISSP, Firewalls, Information Security..., Unix, Shell Scripting, Linux, Virtualization, VPN, Security, Computer Security, TCP/IP, Data Center, Solaris, Checkpoint, Disaster Recovery, Cloud Computing, Perl, Network Architecture, Data Security, Cisco Technologies, IT Operations, Enterprise Architecture, Networking, Integration, IT Service Management, IT Strategy, SaaS
Education
City University of New York-Queens College
Master's degree, Computer Science
National Taiwan University
Bachelor of Arts (B.A.), English Literature (British and Commonwealth)
Cadence Design Systems October 1999 - November 2014
Fujitsu Systems and Business America October 1996 - October 1999
Galaxy Software Services Corporation February 1995 - March 1996
Information Builders June 1993 - February 1995
Skills
Information Security, Network Security, IPS, CISSP, Firewalls, Information Security..., Unix, Shell Scripting, Linux, Virtualization, VPN, Security, Computer Security, TCP/IP, Data Center, Solaris, Checkpoint, Disaster Recovery, Cloud Computing, Perl, Network Architecture, Data Security, Cisco Technologies, IT Operations, Enterprise Architecture, Networking, Integration, IT Service Management, IT Strategy, SaaS
Education
City University of New York-Queens College
Master's degree, Computer Science
National Taiwan University
Bachelor of Arts (B.A.), English Literature (British and Commonwealth)
Chen Fang Chen Fang's Cadence Design Systems Experience May 2004 - April 2013
Job Senior Staff Engineer at Qualcomm
Industry Electrical/Electronic Manufacturing
Experience
Qualcomm April 2013 - Present
Cadence Design Systems May 2004 - April 2013
Cadence Design Systems May 2004 - April 2013
PDF Solutions 2002 - 2004
IBM 1999 - 2002
Skills
DFT, Logic Synthesis, Formal Verification, Test Automation, Timing Closure, Static Timing Analysis, Physical Design, System Verification, UVM, Design for Manufacturing, EDA, Semiconductor..., VLSI CAD, Perl, Debugging, ASIC, CMOS, Semiconductors, Microprocessors, SoC, IC
Education
New Jersey Institute of Technology 1997 — 2001
Ph.D. Candidate, Computer Engineering
Shaanxi Microelectronics Research Institute 1994 — 1997
Master of Science (MS), VLSI design
Xidian University 1990 — 1994
Bachelor of Science (BS), Computer engineering
Qualcomm April 2013 - Present
Cadence Design Systems May 2004 - April 2013
Cadence Design Systems May 2004 - April 2013
PDF Solutions 2002 - 2004
IBM 1999 - 2002
Skills
DFT, Logic Synthesis, Formal Verification, Test Automation, Timing Closure, Static Timing Analysis, Physical Design, System Verification, UVM, Design for Manufacturing, EDA, Semiconductor..., VLSI CAD, Perl, Debugging, ASIC, CMOS, Semiconductors, Microprocessors, SoC, IC
Education
New Jersey Institute of Technology 1997 — 2001
Ph.D. Candidate, Computer Engineering
Shaanxi Microelectronics Research Institute 1994 — 1997
Master of Science (MS), VLSI design
Xidian University 1990 — 1994
Bachelor of Science (BS), Computer engineering
Yu-Yun Dai's Cadence Design Systems Experience May 2014 - July 2014
Job Graduate Student Researcher/Ph.D. student at EECS UC Berkeley
Industry Research
Experience
EECS UC Berkeley August 2013 - Present
Google June 2015 - August 2015
Cadence Design Systems May 2014 - July 2014
SpringSoft July 2011 - September 2011
MediaTek July 2010 - August 2010
Skills
C++, EDA, FPGA, Formal Verification, SAT/SMT solvers, Electronic Design..., LaTeX, Verilog, C, Matlab, Python, Algorithms, Computer-Aided Design
Education
National Taiwan University 2011 — 2013
Master of Science (MS), Electronic Design Automation
National Taiwan University 2007 — 2011
Bachelor of Science (BS), Electrical Engineering
University of California, Berkeley
Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering
High school
EECS UC Berkeley August 2013 - Present
Google June 2015 - August 2015
Cadence Design Systems May 2014 - July 2014
SpringSoft July 2011 - September 2011
MediaTek July 2010 - August 2010
Skills
C++, EDA, FPGA, Formal Verification, SAT/SMT solvers, Electronic Design..., LaTeX, Verilog, C, Matlab, Python, Algorithms, Computer-Aided Design
Education
National Taiwan University 2011 — 2013
Master of Science (MS), Electronic Design Automation
National Taiwan University 2007 — 2011
Bachelor of Science (BS), Electrical Engineering
University of California, Berkeley
Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering
High school
J. Paul Kling J. Paul Kling's Cadence Design Systems Experience January 2006 - November 2008
Job Principle Systems Engineer at MITRE
Industry Semiconductors
Experience
MITRE March 2013 - Present
FAA February 1999 - Present
US Navy Reserves August 1995 - September 2014
Joint Tactical Networking Center (was JTRS) January 2012 - December 2012
US Navy February 2009 - January 2012
Cadence Design Systems January 2006 - November 2008
Office of Naval Research - Monterey 1998 - 2008
Xpedion June 2001 - November 2005
LSI Logic June 1997 - June 2001
Harris Semiconductors January 1997 - June 1997
Skills
Command, Aviation, Military, Aircraft, Electronics, RF, DoD, UAV, Wireless, Piloting, Security Clearance, Weapons, Navy, Systems Engineering, Defense, Program Management, C4ISR, Military Operations, Operational Planning, National Security, Top Secret, Aerospace, Simulations, Intelligence, Flights, Information Assurance, Government Contracting, Government, Intelligence Analysis, Organizational..., Military Experience
Education
Naval War College 2005 — 2011
University of California, Santa Cruz 1997 — 2000
Cert
Worcester Polytechnic Institute 1982 — 1986
BS w/Dist
MITRE March 2013 - Present
FAA February 1999 - Present
US Navy Reserves August 1995 - September 2014
Joint Tactical Networking Center (was JTRS) January 2012 - December 2012
US Navy February 2009 - January 2012
Cadence Design Systems January 2006 - November 2008
Office of Naval Research - Monterey 1998 - 2008
Xpedion June 2001 - November 2005
LSI Logic June 1997 - June 2001
Harris Semiconductors January 1997 - June 1997
Skills
Command, Aviation, Military, Aircraft, Electronics, RF, DoD, UAV, Wireless, Piloting, Security Clearance, Weapons, Navy, Systems Engineering, Defense, Program Management, C4ISR, Military Operations, Operational Planning, National Security, Top Secret, Aerospace, Simulations, Intelligence, Flights, Information Assurance, Government Contracting, Government, Intelligence Analysis, Organizational..., Military Experience
Education
Naval War College 2005 — 2011
University of California, Santa Cruz 1997 — 2000
Cert
Worcester Polytechnic Institute 1982 — 1986
BS w/Dist
Joe Medero Joe Medero's Cadence Design Systems Experience July 1998 - December 2014
Job Principal Engineer at XtremeEDA
Industry Computer Software
Experience
XtremeEDA December 2014 - Present
Cadence Design Systems July 1998 - December 2014
Capital Area Soccer League (CASL) 1995 - 2010
Digital Communications Technologies (ATMEL) February 1996 - June 1998
RTI International January 1995 - February 1996
IBM July 1985 - January 1995
Skills
Verilog, Analog Circuit Design, Digital Signal..., Analog, Electrical Engineering, SoC, Integrated Circuit..., Simulations, Microcontrollers, Physical Design, Low-power Design, Physical Verification, PCIe, ASIC, Mixed Signal, SystemVerilog, C, USB, Semiconductors
Education
North Carolina State University 1986 — 1990
MS, Electrical Engineering
University of Puerto Rico - Mayaguez 1981 — 1985
BS, Computer & Electrical Engineering
XtremeEDA December 2014 - Present
Cadence Design Systems July 1998 - December 2014
Capital Area Soccer League (CASL) 1995 - 2010
Digital Communications Technologies (ATMEL) February 1996 - June 1998
RTI International January 1995 - February 1996
IBM July 1985 - January 1995
Skills
Verilog, Analog Circuit Design, Digital Signal..., Analog, Electrical Engineering, SoC, Integrated Circuit..., Simulations, Microcontrollers, Physical Design, Low-power Design, Physical Verification, PCIe, ASIC, Mixed Signal, SystemVerilog, C, USB, Semiconductors
Education
North Carolina State University 1986 — 1990
MS, Electrical Engineering
University of Puerto Rico - Mayaguez 1981 — 1985
BS, Computer & Electrical Engineering
marwan alayli's Cadence Design Systems Experience January 2014 - June 2014
Job Computer Software Professional
Industry Computer Hardware
Experience
Cadence Design Systems January 2014 - June 2014
EMC January 2013 - December 2013
Skills
Analog, Physical Design, SERDES, Cadence Virtuoso, DRC, LVS, C, Java, Mixed Signal, Embedded C
Education
North Carolina State University 2009 — 2013
Bachelor’s Degree, Electrical and Computer Engineering
Cadence Design Systems January 2014 - June 2014
EMC January 2013 - December 2013
Skills
Analog, Physical Design, SERDES, Cadence Virtuoso, DRC, LVS, C, Java, Mixed Signal, Embedded C
Education
North Carolina State University 2009 — 2013
Bachelor’s Degree, Electrical and Computer Engineering
Vince Calandra's Cadence Design Systems Experience 1996 - 1999
Job NA Sales Executive, IoT Major Accounts at Wind River, Intel Corporation
Industry Computer Software
Experience
Intel Corporation, Wind River Systems February 2015 - Present
Synapse Design Automation Inc. May 2014 - January 2015
Berkeley Design Automation, Mentor Graphics June 2013 - February 2014
eSilicon January 2012 - May 2013
eSilicon Corp. September 2000 - April 2012
Cadence Design Systems 1996 - 1999
Zycad Corporation 1989 - 1998
Grumman Aerospace 1986 - 1988
Skills
Semiconductors, IC, ASIC, Business Development, EDA, Semiconductor Industry, SoC, Product Marketing, Sales Process, Product Management, Product Development, Sales Operations, Management, Start-ups, Cross-functional Team..., Strategic Partnerships, Selling, Sales Management, Sales, New Business Development, Electronics, Leadership, Embedded Systems, Mixed Signal, Analog, Go-to-market Strategy, Processors, International Sales, Negotiation, Digital Signal..., Wireless, Competitive Analysis, IP, Integration, RF, Solution Selling, Simulation, DSP, RTL design, Contract Negotiations, Business Planning, Business Strategy, Sales Support, Marketing Strategy, Electrical Engineering, Sales Process..., Major Account..., C-Level Presentations, Internet of Things, Embedded Software
Education
Polytechnic University 1982 — 1986
BS, EE
NYIT 1986 — 1988
MSCS, Computer Science
Intel Corporation, Wind River Systems February 2015 - Present
Synapse Design Automation Inc. May 2014 - January 2015
Berkeley Design Automation, Mentor Graphics June 2013 - February 2014
eSilicon January 2012 - May 2013
eSilicon Corp. September 2000 - April 2012
Cadence Design Systems 1996 - 1999
Zycad Corporation 1989 - 1998
Grumman Aerospace 1986 - 1988
Skills
Semiconductors, IC, ASIC, Business Development, EDA, Semiconductor Industry, SoC, Product Marketing, Sales Process, Product Management, Product Development, Sales Operations, Management, Start-ups, Cross-functional Team..., Strategic Partnerships, Selling, Sales Management, Sales, New Business Development, Electronics, Leadership, Embedded Systems, Mixed Signal, Analog, Go-to-market Strategy, Processors, International Sales, Negotiation, Digital Signal..., Wireless, Competitive Analysis, IP, Integration, RF, Solution Selling, Simulation, DSP, RTL design, Contract Negotiations, Business Planning, Business Strategy, Sales Support, Marketing Strategy, Electrical Engineering, Sales Process..., Major Account..., C-Level Presentations, Internet of Things, Embedded Software
Education
Polytechnic University 1982 — 1986
BS, EE
NYIT 1986 — 1988
MSCS, Computer Science
Jai Durgam's Cadence Design Systems Experience 1992 - 1993
Job Group Director at Synopsys
Industry Semiconductors
Experience
Synopsys February 2011 - Present
Synopsys, Inc 2005 - February 2011
Scintera Networks October 2003 - July 2005
Silicon Image 2001 - 2003
indusLive, Inc. 1999 - 2001
Neomagic 1999 - 2000
National Semiconductor Corporation August 1988 - March 1999
Cadence Design Systems 1992 - 1993
Skills
Product Engineering, EDA, ASIC, SoC, Semiconductors, IC, Verilog, VLSI, Mixed Signal, Physical Design, FPGA, Low-power Design, Embedded Systems, TCL, Analog, Debugging, Integrated Circuit..., CMOS, Processors, RTL design, Analog Circuit Design
Education
Oregon State University 1986 — 1988
M.S
National Institute of Technology Tiruchirappalli 1979 — 1984
B.E
Synopsys February 2011 - Present
Synopsys, Inc 2005 - February 2011
Scintera Networks October 2003 - July 2005
Silicon Image 2001 - 2003
indusLive, Inc. 1999 - 2001
Neomagic 1999 - 2000
National Semiconductor Corporation August 1988 - March 1999
Cadence Design Systems 1992 - 1993
Skills
Product Engineering, EDA, ASIC, SoC, Semiconductors, IC, Verilog, VLSI, Mixed Signal, Physical Design, FPGA, Low-power Design, Embedded Systems, TCL, Analog, Debugging, Integrated Circuit..., CMOS, Processors, RTL design, Analog Circuit Design
Education
Oregon State University 1986 — 1988
M.S
National Institute of Technology Tiruchirappalli 1979 — 1984
B.E
Chester Nowicki's Cadence Design Systems Experience 1999 - 2003
Job
Industry Semiconductors
Experience
Cadence Design Systems 1999 - 2003
Mentor Graphics 1994 - 1999
Star Semiconductor 1991 - 1994
DRS, Inc. 1986 - 1991
PA Technology 1981 - 1986
Naval Air Development Center 1969 - 1981
Ace Electric 1964 - 1966
Education
Rensselaer Polytechnic Institute 1970 — 1971
MS, SYSTEMS ENGINEERING
New York University 1964 — 1969
BE and BA, ELECTRONICS, MATH
Cadence Design Systems 1999 - 2003
Mentor Graphics 1994 - 1999
Star Semiconductor 1991 - 1994
DRS, Inc. 1986 - 1991
PA Technology 1981 - 1986
Naval Air Development Center 1969 - 1981
Ace Electric 1964 - 1966
Education
Rensselaer Polytechnic Institute 1970 — 1971
MS, SYSTEMS ENGINEERING
New York University 1964 — 1969
BE and BA, ELECTRONICS, MATH
Anil Lobo's Cadence Design Systems Experience July 2007 - Present
Job IT Solution Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2007 - Present
Aztecsoft April 2000 - June 2007
Align Technology 2007 - 2007
Agile Software Corporation July 2005 - July 2006
Tata Infotech August 1998 - March 2000
Skills
Salesforce.com..., salesforce force.com, Salesforce ServiceCloud, Apttus Contract..., RemedyForce, Java Enterprise Edition, Scrum, Agile Methodologies, Spring, Java, SOA, Weblogic, Servlets, LDAP, Perl, Software Engineering, Unix, Ant, Distributed Systems, Tivoli Access Manager, Spring Webflow, Architecture, JSP, XML, Enterprise Architecture, Apex Programming, Architectures, Salesforce.com, Visualforce Pages, Software Project...
Education
National Institute of Technology Karnataka 1994 — 1998
B.E., Electrical & Electronics Engineering
Cadence Design Systems July 2007 - Present
Aztecsoft April 2000 - June 2007
Align Technology 2007 - 2007
Agile Software Corporation July 2005 - July 2006
Tata Infotech August 1998 - March 2000
Skills
Salesforce.com..., salesforce force.com, Salesforce ServiceCloud, Apttus Contract..., RemedyForce, Java Enterprise Edition, Scrum, Agile Methodologies, Spring, Java, SOA, Weblogic, Servlets, LDAP, Perl, Software Engineering, Unix, Ant, Distributed Systems, Tivoli Access Manager, Spring Webflow, Architecture, JSP, XML, Enterprise Architecture, Apex Programming, Architectures, Salesforce.com, Visualforce Pages, Software Project...
Education
National Institute of Technology Karnataka 1994 — 1998
B.E., Electrical & Electronics Engineering
Punit Soni's Cadence Design Systems Experience July 2002 - May 2005
Job Chief Product Officer at Flipkart
Industry Internet
Experience
Flipkart March 2015 - Present
Various Technology Firms January 2015 - Present
Google October 2014 - February 2015
Motorola Mobility, a division of Google August 2012 - October 2014
Google September 2010 - August 2012
Google January 2010 - August 2011
Google July 2009 - December 2009
Google July 2007 - June 2009
Intel Capital April 2006 - August 2006
Cadence Design Systems July 2002 - May 2005
Skills
Product Management, Due Diligence, Sourcing, Financial Analysis, Entrepreneurship, Mobile, Social Games, Business Strategy, Project Execution, Internet Services, Executive Management, Organizational..., Visionary, Mobile Devices, Project Management, Cloud Computing, Product Development, Go-to-market Strategy, Strategy, Start-ups, Mobile Applications, Android, Management, Mobile Internet, Cross-functional Team..., Leadership, Strategic Partnerships, Product Marketing, SaaS, Competitive Analysis, Analytics
Education
University of Pennsylvania - The Wharton School 2005 — 2007
MBA, Venture Capital
University of Wyoming 1998 — 2000
MS, Electrical Engineering
National Institute of Technology Kurukshetra 1994 — 1998
B.Tech, Electronics and Communications Engineering
Flipkart March 2015 - Present
Various Technology Firms January 2015 - Present
Google October 2014 - February 2015
Motorola Mobility, a division of Google August 2012 - October 2014
Google September 2010 - August 2012
Google January 2010 - August 2011
Google July 2009 - December 2009
Google July 2007 - June 2009
Intel Capital April 2006 - August 2006
Cadence Design Systems July 2002 - May 2005
Skills
Product Management, Due Diligence, Sourcing, Financial Analysis, Entrepreneurship, Mobile, Social Games, Business Strategy, Project Execution, Internet Services, Executive Management, Organizational..., Visionary, Mobile Devices, Project Management, Cloud Computing, Product Development, Go-to-market Strategy, Strategy, Start-ups, Mobile Applications, Android, Management, Mobile Internet, Cross-functional Team..., Leadership, Strategic Partnerships, Product Marketing, SaaS, Competitive Analysis, Analytics
Education
University of Pennsylvania - The Wharton School 2005 — 2007
MBA, Venture Capital
University of Wyoming 1998 — 2000
MS, Electrical Engineering
National Institute of Technology Kurukshetra 1994 — 1998
B.Tech, Electronics and Communications Engineering
Jim Horn's Cadence Design Systems Experience 2001 - 2005
Job Director, Sales at GE Intelligent Platforms
Industry Industrial Automation
Experience
GE Intelligent Platforms 2012 - Present
PMC Sierra 2005 - 2012
Cadence Design Systems 2001 - 2005
Avnet 1988 - 2001
Skills
CRM, Account Management, New Business Development, Sales Management, P&L Management, Product Marketing, Semiconductors, Cross-functional Team..., Product Management, Sales, Go-to-market Strategy, Wireless, Leadership, Forecasting, Sales Operations, Project Management, Metrics, Staff Development, Global Leadership, Strategic Partnerships, ASIC, Solution Selling, Enterprise Software, Embedded Systems
Education
University of Virginia
BS, Systems Engineering
New Jersey Institute of Technology
MS Management, Executive MBA
GE Intelligent Platforms 2012 - Present
PMC Sierra 2005 - 2012
Cadence Design Systems 2001 - 2005
Avnet 1988 - 2001
Skills
CRM, Account Management, New Business Development, Sales Management, P&L Management, Product Marketing, Semiconductors, Cross-functional Team..., Product Management, Sales, Go-to-market Strategy, Wireless, Leadership, Forecasting, Sales Operations, Project Management, Metrics, Staff Development, Global Leadership, Strategic Partnerships, ASIC, Solution Selling, Enterprise Software, Embedded Systems
Education
University of Virginia
BS, Systems Engineering
New Jersey Institute of Technology
MS Management, Executive MBA
Ying Y. Tai's Cadence Design Systems Experience January 2010 - September 2011
Job
Industry Semiconductors
Experience
SanDisk October 2011 - Present
Cadence Design Systems January 2010 - September 2011
Boeing 2008 - 2010
Ikanos Communications 2006 - 2008
Academia Sinica / Advanced Micro Devices / Keyeye Communications 1997 - 2006
Education
University of California, Davis
Ph.D., Electrical and Computer Engineering
Stanford University
M.S., Statistics
Stanford University
M.S., Mechanical Engineering
National Sun Yat-Sen University
Bachelor's Degree
SanDisk October 2011 - Present
Cadence Design Systems January 2010 - September 2011
Boeing 2008 - 2010
Ikanos Communications 2006 - 2008
Academia Sinica / Advanced Micro Devices / Keyeye Communications 1997 - 2006
Education
University of California, Davis
Ph.D., Electrical and Computer Engineering
Stanford University
M.S., Statistics
Stanford University
M.S., Mechanical Engineering
National Sun Yat-Sen University
Bachelor's Degree
Aliya Abedi's Cadence Design Systems Experience February 2001 - December 2002
Job Technical Writer
Industry Writing and Editing
Experience
Pacific Gas and Electric Company March 2012 - Present
Self-Employed Freelance Technical Writer March 2011 - March 2012
Interactive Solutions Inc. April 2004 - January 2011
ClioSoft, Inc. March 2003 - July 2003
Cadence Design Systems February 2001 - December 2002
ITT Technical Institute June 1999 - January 2001
Sir Syed University of Engineering and Technology 1995 - 1999
Education
NED University of Engineering and Technology 1989 — 1994
BS in, Electrical Engineering
Pacific Gas and Electric Company March 2012 - Present
Self-Employed Freelance Technical Writer March 2011 - March 2012
Interactive Solutions Inc. April 2004 - January 2011
ClioSoft, Inc. March 2003 - July 2003
Cadence Design Systems February 2001 - December 2002
ITT Technical Institute June 1999 - January 2001
Sir Syed University of Engineering and Technology 1995 - 1999
Education
NED University of Engineering and Technology 1989 — 1994
BS in, Electrical Engineering
Yean-Yow Hwang's Cadence Design Systems Experience August 2013 - Present
Job Architect
Industry Semiconductors
Experience
Cadence Design Systems August 2013 - Present
Tabula January 2010 - July 2013
eASIC Inc. February 2007 - March 2010
Velogix Inc. August 2004 - January 2007
Leopard Logic Inc. August 2003 - August 2004
Altera Corp. July 2001 - July 2004
Skills
EDA, FPGA, Algorithms, VHDL, ASIC, C++, Debugging, Software Engineering, Logic Synthesis, Digital Signal..., TCL, Verilog, VLSI, SoC
Education
University of California, Los Angeles 1991 — 1998
Ph.D, CS / VLSI CAD
University of California, Riverside 1985 — 1987
MS, Computer Science
National Taiwan University 1976 — 1980
BS, Electrical Engineering
Cadence Design Systems August 2013 - Present
Tabula January 2010 - July 2013
eASIC Inc. February 2007 - March 2010
Velogix Inc. August 2004 - January 2007
Leopard Logic Inc. August 2003 - August 2004
Altera Corp. July 2001 - July 2004
Skills
EDA, FPGA, Algorithms, VHDL, ASIC, C++, Debugging, Software Engineering, Logic Synthesis, Digital Signal..., TCL, Verilog, VLSI, SoC
Education
University of California, Los Angeles 1991 — 1998
Ph.D, CS / VLSI CAD
University of California, Riverside 1985 — 1987
MS, Computer Science
National Taiwan University 1976 — 1980
BS, Electrical Engineering
Saurin Shroff's Cadence Design Systems Experience 1990 - 1995
Job Principal Engineer at Synopsys Inc.
Industry Computer Software
Experience
Synopsys Inc. Technical Director, CTOTransEDA Inc.2001 - 2005
DualSoft 1999 - 2000
Chrysalis Inc April 1995 - October 1999
Chrysalis Symbolic Design 1995 - 1999
Cadence Design Systems 1990 - 1995
CLSI Inc 1987 - 1990
Skills
Verilog, TCL, VLSI, EDA, Simulations, SoC, Formal Verification, ASIC, IC, SystemVerilog, RTL design, FPGA, Debugging, Semiconductors, Perl
Education
North Carolina State University 1985 — 1987
University of Mumbai 1980 — 1983
B.Sc, Physics
New Era School 1967 — 1977
Watumul Institute Of Electronic Engineering
Synopsys Inc. Technical Director, CTOTransEDA Inc.2001 - 2005
DualSoft 1999 - 2000
Chrysalis Inc April 1995 - October 1999
Chrysalis Symbolic Design 1995 - 1999
Cadence Design Systems 1990 - 1995
CLSI Inc 1987 - 1990
Skills
Verilog, TCL, VLSI, EDA, Simulations, SoC, Formal Verification, ASIC, IC, SystemVerilog, RTL design, FPGA, Debugging, Semiconductors, Perl
Education
North Carolina State University 1985 — 1987
University of Mumbai 1980 — 1983
B.Sc, Physics
New Era School 1967 — 1977
Watumul Institute Of Electronic Engineering
Hemanth Sampath's Cadence Design Systems Experience May 2003 - November 2004
Job Sr. Director of Strategy & Growth Initiatives at Assurant
Industry Insurance
Experience
Assurant October 2014 - Present
LexisNexis September 2011 - October 2014
LexisNexis August 2009 - September 2011
McKinsey & Company May 2008 - July 2008
Intel Corporation November 2004 - July 2007
Cadence Design Systems May 2003 - November 2004
Skills
Product Management, Strategy, Competitive Analysis, Analytics, Market Research, Go-to-market Strategy, Product Launch, Business Development, Management, Product Development, Cross-functional Team..., Team Leadership, Consulting, Marketing Strategy, Business Strategy, Strategic Planning
Education
University of Pennsylvania - The Wharton School 2007 — 2009
MBA, General Management
University of Cincinnati 2000 — 2003
MS, Computer Engineering
National Institute of Technology Tiruchirappalli 1996 — 2000
BE, Engineering
Assurant October 2014 - Present
LexisNexis September 2011 - October 2014
LexisNexis August 2009 - September 2011
McKinsey & Company May 2008 - July 2008
Intel Corporation November 2004 - July 2007
Cadence Design Systems May 2003 - November 2004
Skills
Product Management, Strategy, Competitive Analysis, Analytics, Market Research, Go-to-market Strategy, Product Launch, Business Development, Management, Product Development, Cross-functional Team..., Team Leadership, Consulting, Marketing Strategy, Business Strategy, Strategic Planning
Education
University of Pennsylvania - The Wharton School 2007 — 2009
MBA, General Management
University of Cincinnati 2000 — 2003
MS, Computer Engineering
National Institute of Technology Tiruchirappalli 1996 — 2000
BE, Engineering
Dennis Huang's Cadence Design Systems Experience January 2002 - Present
Job Engineering Director at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems January 2002 - Present
Silicon Perspective Corp April 1999 - December 2001
Avant! Corp June 1997 - April 1999
Synposys December 1996 - June 1997
Skills
EDA, Perl, C++, Debugging, Algorithms, Linux, Software Engineering, ASIC, TCL, C, Software Development, Distributed Systems, Embedded Systems
Education
University of California, Los Angeles 1991 — 1996
Ph. D., Computer Science
Stony Brook University 1989 — 1991
M.S., Computer Science
National Taiwan University 1983 — 1987
B.S., Computer Science & Information Engineering
High school
Cadence Design Systems January 2002 - Present
Silicon Perspective Corp April 1999 - December 2001
Avant! Corp June 1997 - April 1999
Synposys December 1996 - June 1997
Skills
EDA, Perl, C++, Debugging, Algorithms, Linux, Software Engineering, ASIC, TCL, C, Software Development, Distributed Systems, Embedded Systems
Education
University of California, Los Angeles 1991 — 1996
Ph. D., Computer Science
Stony Brook University 1989 — 1991
M.S., Computer Science
National Taiwan University 1983 — 1987
B.S., Computer Science & Information Engineering
High school
Augustine Weaver's Cadence Design Systems Experience 1996 - 2000
Job Physical Design Specialist at Synopsys
Industry Electrical/Electronic Manufacturing
Experience
Synopsys Inc 2001 - Present
Cadence Design Systems 1996 - 2000
Gul Technologies 1995 - 1996
Indian Telephone Industries 1990 - 1995
Indian Institute of Science 1989 - 1990
Education
National Institute of Technology Karnataka 1984 — 1988
BE, Electronics & Communication
Synopsys Inc 2001 - Present
Cadence Design Systems 1996 - 2000
Gul Technologies 1995 - 1996
Indian Telephone Industries 1990 - 1995
Indian Institute of Science 1989 - 1990
Education
National Institute of Technology Karnataka 1984 — 1988
BE, Electronics & Communication
Kuoching Lin's Cadence Design Systems Experience March 2015 - Present
Job Senior Software Architect at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems March 2015 - Present
Tabula August 2010 - February 2015
Tierlogic Technology November 2006 - August 2010
Mentor Graphics 1989 - 2006
Skills
C++, Debugging, Software Engineering
Education
The University of Texas at Austin 1987 — 1989
Master, Computer Engineering
National Tsing Hua University 1981 — 1985
Cadence Design Systems March 2015 - Present
Tabula August 2010 - February 2015
Tierlogic Technology November 2006 - August 2010
Mentor Graphics 1989 - 2006
Skills
C++, Debugging, Software Engineering
Education
The University of Texas at Austin 1987 — 1989
Master, Computer Engineering
National Tsing Hua University 1981 — 1985
Alpana Apte's Cadence Design Systems Experience January 2001 - Present
Job Sales Technical Leader at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems January 2001 - Present
Sardar Vallabhbhai National Institute of Technology 1994 - 1998
Education
San Jose State University 1999 — 2001
M.S, Electrical Engineering
National Institute of Technology Surat 1992 — 1994
B.E, Electronics
South Gujarat University 1992 — 1994
REC
Cadence Design Systems January 2001 - Present
Sardar Vallabhbhai National Institute of Technology 1994 - 1998
Education
San Jose State University 1999 — 2001
M.S, Electrical Engineering
National Institute of Technology Surat 1992 — 1994
B.E, Electronics
South Gujarat University 1992 — 1994
REC
Betty Sun's Cadence Design Systems Experience November 1989 - 1992
Job Data Architect/DBA at GlobalCapacity
Industry Computer Software
Experience
MegaPath Inc. September 2010 - Present
Covad Communications September 2001 - August 2010
Netscape/AOL 1995 - 2001
Cadence Design Systems November 1989 - 1992
Skills
Data Modeling, Agile Methodologies, Data Warehousing, Oracle, Unix, SQL, PL/SQL, Solaris, Enterprise Architecture, Architecture, Databases, Microsoft SQL Server
Education
New York University
MS, Computer Science
Queens College
BA, Computer Science
MegaPath Inc. September 2010 - Present
Covad Communications September 2001 - August 2010
Netscape/AOL 1995 - 2001
Cadence Design Systems November 1989 - 1992
Skills
Data Modeling, Agile Methodologies, Data Warehousing, Oracle, Unix, SQL, PL/SQL, Solaris, Enterprise Architecture, Architecture, Databases, Microsoft SQL Server
Education
New York University
MS, Computer Science
Queens College
BA, Computer Science
Subbu Ganesan's Cadence Design Systems Experience October 2009 - Present
Job Architect, HW Verification at Cadence Design Systems
Industry Computer Hardware
Experience
Cadence Design Systems October 2009 - Present
Mentor Graphics May 2009 - October 2009
Xilinx July 2007 - April 2009
Eve-USA January 2007 - June 2007
Tharas Systems August 1998 - December 2006
ZeitNet/Cabletron Systems February 1994 - August 1998
SynOptics Communications November 1992 - January 1994
Bytex Corporation October 1989 - October 1992
C-DOT 1984 - 1986
Skills
Simulation, Hardware Design, Hardware, Emulation, Verilog, System Design, Engineering Management, ASIC
Education
R.S Krishnan Higher Secondary school 1967 — 2011
High School
Rensselaer Polytechnic Institute 1985 — 1987
Master's degree, Electrical and Electronics Engineering
National Institute of Technology Tiruchirappalli 1980 — 1984
BE, ECE
Cadence Design Systems October 2009 - Present
Mentor Graphics May 2009 - October 2009
Xilinx July 2007 - April 2009
Eve-USA January 2007 - June 2007
Tharas Systems August 1998 - December 2006
ZeitNet/Cabletron Systems February 1994 - August 1998
SynOptics Communications November 1992 - January 1994
Bytex Corporation October 1989 - October 1992
C-DOT 1984 - 1986
Skills
Simulation, Hardware Design, Hardware, Emulation, Verilog, System Design, Engineering Management, ASIC
Education
R.S Krishnan Higher Secondary school 1967 — 2011
High School
Rensselaer Polytechnic Institute 1985 — 1987
Master's degree, Electrical and Electronics Engineering
National Institute of Technology Tiruchirappalli 1980 — 1984
BE, ECE
JP Weng's Cadence Design Systems Experience April 2006 - Present
Job Engineering Director at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems April 2006 - Present
Praesagus October 2005 - March 2006
Synopsys, Inc. February 2002 - September 2005
Skills
EDA, TCL, Semiconductors, ASIC, Static Timing Analysis, Physical Design, SoC
Education
University of Southern California
Doctor of Philosophy (PhD), Computer Engineering
University of Southern California
Master of Science (M.S.), Computer Engineering
National Taiwan University
Bachelor of Science (B.S.), Mechanical Engineering
Cadence Design Systems April 2006 - Present
Praesagus October 2005 - March 2006
Synopsys, Inc. February 2002 - September 2005
Skills
EDA, TCL, Semiconductors, ASIC, Static Timing Analysis, Physical Design, SoC
Education
University of Southern California
Doctor of Philosophy (PhD), Computer Engineering
University of Southern California
Master of Science (M.S.), Computer Engineering
National Taiwan University
Bachelor of Science (B.S.), Mechanical Engineering
Saurav Bhattarai's Cadence Design Systems Experience 2003 - 2005
Job Web Developer at CAaNES LLC
Industry Electrical/Electronic Manufacturing
Experience
CAaNES LLC May 2009 - Present
Cadence Design Systems 2003 - 2005
Education
New Mexico Institute of Mining and Technology 2005 — 2009
BS, Electrical Engineering
CAaNES LLC May 2009 - Present
Cadence Design Systems 2003 - 2005
Education
New Mexico Institute of Mining and Technology 2005 — 2009
BS, Electrical Engineering
Robert Yurman's Cadence Design Systems Experience MTSTRW1985 - 1992
Job Principal Applications Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems MTSTRW1985 - 1992
Skills
EDA, LVS, Physical Design, Analog, IC, Physical Verification, TCL, Parasitic Extraction, DRC, ASIC, Analog Circuit Design, Unix, Circuit Design, Cadence Virtuoso, Cadence, Low-power Design, Semiconductors, Timing Closure, VLSI, Mixed Signal, SoC
Education
New York University - Polytechnic School of Engineering 1981 — 1985
Cadence Design Systems MTSTRW1985 - 1992
Skills
EDA, LVS, Physical Design, Analog, IC, Physical Verification, TCL, Parasitic Extraction, DRC, ASIC, Analog Circuit Design, Unix, Circuit Design, Cadence Virtuoso, Cadence, Low-power Design, Semiconductors, Timing Closure, VLSI, Mixed Signal, SoC
Education
New York University - Polytechnic School of Engineering 1981 — 1985
Matthew Roha's Cadence Design Systems Experience June 1994 - December 1996
Job CPU Physical Design Manager at Intel Corp, Board of Directors, Folsom Tigersharks
Industry Semiconductors
Experience
Intel Corporation September 2005 - Present
Intel Corporation January 1997 - September 2005
Cadence Design Systems June 1994 - December 1996
Unisys June 1992 - June 1994
Skills
Physical Design, Processors, Semiconductors, SoC, Integrated Circuit..., Non-Profit Board Member, Training & Development, Swim Computer Operations, Planning, Technical Staff..., Global Resource...
Education
National University 1999 — 2001
BS, Computer Science
University of California, San Diego 1990 — 1995
Bachelor of Science (BS), Electrical and Electronics Engineering
Intel Corporation September 2005 - Present
Intel Corporation January 1997 - September 2005
Cadence Design Systems June 1994 - December 1996
Unisys June 1992 - June 1994
Skills
Physical Design, Processors, Semiconductors, SoC, Integrated Circuit..., Non-Profit Board Member, Training & Development, Swim Computer Operations, Planning, Technical Staff..., Global Resource...
Education
National University 1999 — 2001
BS, Computer Science
University of California, San Diego 1990 — 1995
Bachelor of Science (BS), Electrical and Electronics Engineering
Larry Rosenberg's Cadence Design Systems Experience May 1986 - December 1990
Job Principal at EDAS Systems
Industry Semiconductors
Experience
EDAS Systems 1995 - Present
VSI Alliance March 1996 - May 2004
Cadence Design Systems May 1986 - December 1990
SDA Systems June 1985 - May 1986
RCA Solid State Technology Center October 1970 - May 1985
RCA 1970 - 1985
Skills
IC, EDA, Simulations, Software Engineering, CAD, VLSI, Semiconductors, FPGA, Embedded Systems, Strategy, Marketing Strategy, Start-ups, Strategic Partnerships, Product Marketing, Integrated Circuit..., Algorithms, Physical Design, SoC, Perl, ASIC, Engineering, Analog, Software Development, Product Management, Executive Management, Wireless, Go-to-market Strategy, Physics, Electronics
Education
Princeton University 1964 — 1970
Ph.D., Electron Device Physics in EE Dept
New York University - Polytechnic School of Engineering 1960 — 1964
BSEE, Electrical Engineering, Summa Cum Laude
Stuyvesant High 1957 — 1960
Academic, Science Major
EDAS Systems 1995 - Present
VSI Alliance March 1996 - May 2004
Cadence Design Systems May 1986 - December 1990
SDA Systems June 1985 - May 1986
RCA Solid State Technology Center October 1970 - May 1985
RCA 1970 - 1985
Skills
IC, EDA, Simulations, Software Engineering, CAD, VLSI, Semiconductors, FPGA, Embedded Systems, Strategy, Marketing Strategy, Start-ups, Strategic Partnerships, Product Marketing, Integrated Circuit..., Algorithms, Physical Design, SoC, Perl, ASIC, Engineering, Analog, Software Development, Product Management, Executive Management, Wireless, Go-to-market Strategy, Physics, Electronics
Education
Princeton University 1964 — 1970
Ph.D., Electron Device Physics in EE Dept
New York University - Polytechnic School of Engineering 1960 — 1964
BSEE, Electrical Engineering, Summa Cum Laude
Stuyvesant High 1957 — 1960
Academic, Science Major
Yung-Te Lai's Cadence Design Systems Experience January 2007 - Present
Job Software Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems January 2007 - Present
Cadence Design Systems August 2004 - January 2007
Cadence Design Systems August 2003 - August 2004
Verplex Design Systems, Inc. September 2000 - August 2003
Verplex Design Systems, Inc. May 1998 - September 2000
Synopsys July 1997 - May 1998
Skills
Software Development, Architecture, Formal Verification, BDD, Logic Equivalence..., SAT solver, ECO, Conformal LEC, Software Engineering, Architectures, C++
Education
University of Southern California 1986 — 1993
Ph.D., Computer Engineering
San Diego State University-California State University 1980 — 1982
M.S., Computer Science
National Cheng Kung University 1973 — 1977
B.S., Urban Planning
Cadence Design Systems January 2007 - Present
Cadence Design Systems August 2004 - January 2007
Cadence Design Systems August 2003 - August 2004
Verplex Design Systems, Inc. September 2000 - August 2003
Verplex Design Systems, Inc. May 1998 - September 2000
Synopsys July 1997 - May 1998
Skills
Software Development, Architecture, Formal Verification, BDD, Logic Equivalence..., SAT solver, ECO, Conformal LEC, Software Engineering, Architectures, C++
Education
University of Southern California 1986 — 1993
Ph.D., Computer Engineering
San Diego State University-California State University 1980 — 1982
M.S., Computer Science
National Cheng Kung University 1973 — 1977
B.S., Urban Planning
Anthony Mandala's Cadence Design Systems Experience March 1993 - June 1998
Job Sales Management at Synopsys
Industry Computer Software
Experience
Synopsys June 2002 - Present
Avant! August 2000 - May 2002
ZLand June 1998 - April 2000
Cadence Design Systems March 1993 - June 1998
Zycad 1989 - 1993
Zycad/Protocol 1988 - 1990
Allied-Signal Aerospace August 1985 - 1988
Skills
Complex Sales, Sales Operations, Product Management, Enterprise Software, SaaS, Cross-functional Team..., Unix, Start-ups, Sales Management, Solution Selling, Cloud Computing, Product Marketing, Sales, Strategic Partnerships, Professional Services, Semiconductors
Education
New Jersey Institute of Technology 1982 — 1985
BSCS, Comp Science/EE
Roxbury HS 1979 — 1980
Synopsys June 2002 - Present
Avant! August 2000 - May 2002
ZLand June 1998 - April 2000
Cadence Design Systems March 1993 - June 1998
Zycad 1989 - 1993
Zycad/Protocol 1988 - 1990
Allied-Signal Aerospace August 1985 - 1988
Skills
Complex Sales, Sales Operations, Product Management, Enterprise Software, SaaS, Cross-functional Team..., Unix, Start-ups, Sales Management, Solution Selling, Cloud Computing, Product Marketing, Sales, Strategic Partnerships, Professional Services, Semiconductors
Education
New Jersey Institute of Technology 1982 — 1985
BSCS, Comp Science/EE
Roxbury HS 1979 — 1980
Erich C. Tzou's Cadence Design Systems Experience 2005 - Present
Job Counsel at Vista IP Law Group LLP
Industry Law Practice
Experience
Vista IP Law Group LLP August 2012 - Present
Shenzhen Mindray Bio-Medical Electronics Co., LTD. May 2008 - Present
Oracle USA 2005 - Present
Cadence Design Systems 2005 - Present
Vista IP Law Group LLP May 2008 - July 2012
Bingham McCutchen December 2005 - May 2008
Nano-Pixels, Inc. June 2003 - November 2005
Applied Materials July 1994 - May 2003
SKE Technology, Inc. 1993 - 1994
Skills
Intellectual Property, Litigation, Prosecution, Patent Prosecution, Trademarks, Patents, Legal Research, Civil Litigation, Patent Litigation, Unfair Competition, Trade Secrets, Trademark Infringement, Registered Patent..., Patentability, Copyright Law, Trade Dress, Cyberlaw, False Advertising, Copyright Infringement, Advertising Law
Education
Santa Clara University School of Law 2003 — 2006
Juris Doctor
National Taiwan University
B.S.
Stanford University
Ph.D. candidate, Numerical Simulation of Physical Problems
Stanford University
M.S., Applied Mechanics / Applied Mathematics
Vista IP Law Group LLP August 2012 - Present
Shenzhen Mindray Bio-Medical Electronics Co., LTD. May 2008 - Present
Oracle USA 2005 - Present
Cadence Design Systems 2005 - Present
Vista IP Law Group LLP May 2008 - July 2012
Bingham McCutchen December 2005 - May 2008
Nano-Pixels, Inc. June 2003 - November 2005
Applied Materials July 1994 - May 2003
SKE Technology, Inc. 1993 - 1994
Skills
Intellectual Property, Litigation, Prosecution, Patent Prosecution, Trademarks, Patents, Legal Research, Civil Litigation, Patent Litigation, Unfair Competition, Trade Secrets, Trademark Infringement, Registered Patent..., Patentability, Copyright Law, Trade Dress, Cyberlaw, False Advertising, Copyright Infringement, Advertising Law
Education
Santa Clara University School of Law 2003 — 2006
Juris Doctor
National Taiwan University
B.S.
Stanford University
Ph.D. candidate, Numerical Simulation of Physical Problems
Stanford University
M.S., Applied Mechanics / Applied Mathematics
Greg Scribner's Cadence Design Systems Experience 1998 - 2002
Job Lead Test Engineer/CoOwner
Industry Semiconductors
Experience
TestEdge, Inc. December 2002 - Present
Cadence/Tality June 1998 - December 2002
Cadence Design Systems 1998 - 2002
Cadence Design Systems/Tality LP 1998 - 2002
Education
San Diego State University-California State University 1996 — 1998
MSEE
New Mexico Institute of Mining and Technology 1990 — 1993
BSEE
TestEdge, Inc. December 2002 - Present
Cadence/Tality June 1998 - December 2002
Cadence Design Systems 1998 - 2002
Cadence Design Systems/Tality LP 1998 - 2002
Education
San Diego State University-California State University 1996 — 1998
MSEE
New Mexico Institute of Mining and Technology 1990 — 1993
BSEE
Manisha Narula's Cadence Design Systems Experience May 2010 - February 2011
Job Apple Inc
Industry Electrical/Electronic Manufacturing
Experience
Apple Inc. April 2011 - Present
Cadence Design Systems May 2010 - February 2011
Freescale Semiconductors, Austin TX April 2008 - April 2010
Freescale Semiconductor India Pvt Ltd July 2005 - October 2007
Education
Netaji Subhas Institute of Technology 2001 — 2005
BE, EE
Apple Inc. April 2011 - Present
Cadence Design Systems May 2010 - February 2011
Freescale Semiconductors, Austin TX April 2008 - April 2010
Freescale Semiconductor India Pvt Ltd July 2005 - October 2007
Education
Netaji Subhas Institute of Technology 2001 — 2005
BE, EE
Madan Pamula's Cadence Design Systems Experience July 1995 - Present
Job Senior Engg. Manager at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 1995 - Present
Bharat Electronics May 1988 - June 1995
Skills
TCL, ASIC, SoC, EDA, Semiconductors, Physical Design, IC, Perl, Debugging, Static Timing Analysis, Mixed Signal, FPGA, Verilog, VLSI
Education
Osmania University 1985 — 1987
MBA, Marketing Mgmt
National Institute of Technology Warangal 1980 — 1984
B. Tech, Electronics & Communications
All Saints High School
Cadence Design Systems July 1995 - Present
Bharat Electronics May 1988 - June 1995
Skills
TCL, ASIC, SoC, EDA, Semiconductors, Physical Design, IC, Perl, Debugging, Static Timing Analysis, Mixed Signal, FPGA, Verilog, VLSI
Education
Osmania University 1985 — 1987
MBA, Marketing Mgmt
National Institute of Technology Warangal 1980 — 1984
B. Tech, Electronics & Communications
All Saints High School
Suketu Desai's Cadence Design Systems Experience April 2002 - Present
Job Architect at Cadence Design Systems
Industry Computer Hardware
Experience
Cadence Design Systems April 2002 - Present
Simplex Solutions April 2001 - April 2002
Avant! January 2000 - March 2001
Skills
Signal Integrity, Extraction, Analysis
Education
University of Southern California 1998 — 2000
National Institute of Technology Surat 1994 — 1998
BS, Electronics
Cadence Design Systems April 2002 - Present
Simplex Solutions April 2001 - April 2002
Avant! January 2000 - March 2001
Skills
Signal Integrity, Extraction, Analysis
Education
University of Southern California 1998 — 2000
National Institute of Technology Surat 1994 — 1998
BS, Electronics
Tsair-Chin (T.C.) Lin's Cadence Design Systems Experience July 2014 - Present
Job VP R&D at Cadence Design Systems
Industry Electrical/Electronic Manufacturing
Experience
Cadence Design Systems July 2014 - Present
Cadence Design Systems July 2010 - June 2014
Skills
EDA, Verilog, ASIC, SoC, FPGA, RTL design, RTL Design, Perl, VLSI, Embedded Systems, IC, Semiconductors, Debugging, Simulations, TCL, Functional Verification
Education
National Taiwan University
Bachelor’s Degree, EE
University of Southern California
Doctor of Philosophy (Ph.D.), EE
Cadence Design Systems July 2014 - Present
Cadence Design Systems July 2010 - June 2014
Skills
EDA, Verilog, ASIC, SoC, FPGA, RTL design, RTL Design, Perl, VLSI, Embedded Systems, IC, Semiconductors, Debugging, Simulations, TCL, Functional Verification
Education
National Taiwan University
Bachelor’s Degree, EE
University of Southern California
Doctor of Philosophy (Ph.D.), EE
Odysseus Fang's Cadence Design Systems Experience July 2007 - August 2009
Job
Industry Computer Software
Experience
Atoptech February 2010 - Present
Cadence Design Systems July 2007 - August 2009
Synopsys August 2003 - July 2007
eWave System, Inc. June 2001 - July 2003
WavePlus Technology Co., Ltd. October 1999 - June 2001
Siemens Telecommunications System Limited June 1998 - September 1999
Skills
TCL, Verilog, Logic Analyzer, C++, VHDL, Perl, Java, Programming, Operating Systems, Csh, Spectrum Analyzer, Awk, IC, EDA, C, Debugging, FPGA, RTL design, VLSI, Assembly, ModelSim, ASIC, Static Timing Analysis, Linux, Unix, Shell Scripting, CVS, SoC, Testing, Microprocessors, Windows, HTML, CSS
Education
National Tsing Hua University 1994 — 1996
Master
National Tsing Hua University 1989 — 1994
Bachelor
Atoptech February 2010 - Present
Cadence Design Systems July 2007 - August 2009
Synopsys August 2003 - July 2007
eWave System, Inc. June 2001 - July 2003
WavePlus Technology Co., Ltd. October 1999 - June 2001
Siemens Telecommunications System Limited June 1998 - September 1999
Skills
TCL, Verilog, Logic Analyzer, C++, VHDL, Perl, Java, Programming, Operating Systems, Csh, Spectrum Analyzer, Awk, IC, EDA, C, Debugging, FPGA, RTL design, VLSI, Assembly, ModelSim, ASIC, Static Timing Analysis, Linux, Unix, Shell Scripting, CVS, SoC, Testing, Microprocessors, Windows, HTML, CSS
Education
National Tsing Hua University 1994 — 1996
Master
National Tsing Hua University 1989 — 1994
Bachelor
Eva Pang's Cadence Design Systems Experience January 1996 - February 1997
Job Computer Hardware Professional
Industry Computer Hardware
Experience
PMC-Sierra April 1997 - June 2007
Cadence Design Systems January 1996 - February 1997
Education
The Chinese University of Hong Kong 1992 — 1994
M. Phil., Electronic Engineering
National Taiwan University 1988 — 1992
B Sc
PMC-Sierra April 1997 - June 2007
Cadence Design Systems January 1996 - February 1997
Education
The Chinese University of Hong Kong 1992 — 1994
M. Phil., Electronic Engineering
National Taiwan University 1988 — 1992
B Sc
Pin-Yen Chen's Cadence Design Systems Experience February 2008 - April 2012
Job Sr. Developer at Tableau Software
Industry Computer Software
Experience
Tableau Software April 2012 - Present
Cadence Design Systems February 2008 - April 2012
National Instruments April 2004 - January 2008
Minerva Networks May 2001 - March 2004
Honeywell November 1996 - May 2001
Skills
C++, Linux, Qt, VxWorks, TCL, Labview, IPTV, Data Visualization, pSOS, JavaScript, C, Java, Graphics, Embedded Systems, GUI, HTML5, CSS3, MPEG, TCP/UDP
Education
University of California, Berkeley 1995 — 1996
MS, Mechical Engineering (Control)
National Chiao Tung University 1989 — 1993
BS, Mechical Engineering (Control)
Tableau Software April 2012 - Present
Cadence Design Systems February 2008 - April 2012
National Instruments April 2004 - January 2008
Minerva Networks May 2001 - March 2004
Honeywell November 1996 - May 2001
Skills
C++, Linux, Qt, VxWorks, TCL, Labview, IPTV, Data Visualization, pSOS, JavaScript, C, Java, Graphics, Embedded Systems, GUI, HTML5, CSS3, MPEG, TCP/UDP
Education
University of California, Berkeley 1995 — 1996
MS, Mechical Engineering (Control)
National Chiao Tung University 1989 — 1993
BS, Mechical Engineering (Control)
Herbert Rivera-Sanchez's Cadence Design Systems Experience June 2006 - September 2010
Job VIP Solutions Architect at Cadence
Industry Semiconductors
Experience
Cadence VIP Specialist NACadence Design SystemsMay 2011 - May 2012
Open-Silicon September 2010 - May 2011
Cadence Design Systems June 2006 - September 2010
AMCC 2001 - 2006
AMCC (formerly RTC) 2001 - 2006
Nortel Networks 1998 - 2001
Nortel 1999 - 2000
IBM 1985 - 1995
Skills
Functional Verification, Verilog, Open Verification..., Architecture, Integration, Specman, ASIC, Cadence, EDA, SoC, SystemVerilog, Architectures, Analysis
Education
North Carolina State University 1987 — 1990
Master of Science, Electrical and Computer Engineering
Cadence VIP Specialist NACadence Design SystemsMay 2011 - May 2012
Open-Silicon September 2010 - May 2011
Cadence Design Systems June 2006 - September 2010
AMCC 2001 - 2006
AMCC (formerly RTC) 2001 - 2006
Nortel Networks 1998 - 2001
Nortel 1999 - 2000
IBM 1985 - 1995
Skills
Functional Verification, Verilog, Open Verification..., Architecture, Integration, Specman, ASIC, Cadence, EDA, SoC, SystemVerilog, Architectures, Analysis
Education
North Carolina State University 1987 — 1990
Master of Science, Electrical and Computer Engineering
Asila Nahas's Cadence Design Systems Experience July 2014 - Present
Job Principal Software Engineer at Cadence Design Systems
Industry Computer Hardware
Experience
Cadence Design Systems July 2014 - Present
Intel Corporation 2009 - Present
Skills
Verilog, SystemVerilog, Computer Architecture, C++, VHDL, VLSI, ASIC, RTL design, Debugging, Perl, Unix Shell Scripting, Functional Verification, Specman, Microarchitecture
Education
University of Southern California 2007 — 2008
Master of Science (MS), Electrical Engineering
National Institute of Technology Calicut 2003 — 2007
Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering
Cadence Design Systems July 2014 - Present
Intel Corporation 2009 - Present
Skills
Verilog, SystemVerilog, Computer Architecture, C++, VHDL, VLSI, ASIC, RTL design, Debugging, Perl, Unix Shell Scripting, Functional Verification, Specman, Microarchitecture
Education
University of Southern California 2007 — 2008
Master of Science (MS), Electrical Engineering
National Institute of Technology Calicut 2003 — 2007
Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering
Alka Munjal's Cadence Design Systems Experience 2004 - 2004
Job Sr. Software Engineer In Test at Sony Computer Entertainment America
Industry Computer Software
Experience
Sony Computer Entertainment America June 2014 - Present
Sony Computer Entertainment America May 2011 - June 2014
Sony Computer Entertainment America September 2009 - May 2011
Cadence Design Systems 2004 - 2004
Lingaya's GVKS Institute of Management & Technology August 2001 - July 2003
Skills
Test Automation, Python, Testing, Software Quality..., C++, Java, Quality Assurance, Programming, Linux, Scripting, C, Jenkins
Education
Netaji Subhas Institute of Technology
M.Tech, Information Systems, A
Sony Computer Entertainment America June 2014 - Present
Sony Computer Entertainment America May 2011 - June 2014
Sony Computer Entertainment America September 2009 - May 2011
Cadence Design Systems 2004 - 2004
Lingaya's GVKS Institute of Management & Technology August 2001 - July 2003
Skills
Test Automation, Python, Testing, Software Quality..., C++, Java, Quality Assurance, Programming, Linux, Scripting, C, Jenkins
Education
Netaji Subhas Institute of Technology
M.Tech, Information Systems, A
Noushi Beyzavi Haeussler's Cadence Design Systems Experience January 1996 - May 1999
Job President at ExcelLase, Laser Center
Industry Health, Wellness and Fitness
Experience
ExcelLase, Laser Center February 2005 - Present
TechCon International April 1999 - February 2005
Cadence Design Systems January 1996 - May 1999
Synopsys July 1993 - January 1996
IBM September 1989 - July 1993
Skills
Laser, Leadership, Skin Resurfacing, Fraxel, Business Development, Tattoo Removal, Laser Hair Removal, Skin Care, Small Business, Acne, Team Building, Strategic Planning, Public Speaking
Education
Durham Community College 2013 — 2015
Registered Nurse, Nursing
Cool Sculpting University 2014 — 2014
Certification, Cool Sculpting Non Invasive Fat Removal
NC Certified Nurse's Assistant 2013 — 2013
CNA, Focused One on One Patient Care Training
North Carolina State University 1997 — 1999
Master of Science, Management (Managing Hi Tech and Entreprenuership), 3.9/4
Syracuse University 1990 — 1993
M.S., Electrical Engineering
University of Minnesota-Twin Cities 1984 — 1989
Bachelor of Science (B.S.), Electrical Engineering
Azad University 1981 — 1984
Bachelor of Science (B.S.), Physics, 3.95/4.0
ExcelLase, Laser Center February 2005 - Present
TechCon International April 1999 - February 2005
Cadence Design Systems January 1996 - May 1999
Synopsys July 1993 - January 1996
IBM September 1989 - July 1993
Skills
Laser, Leadership, Skin Resurfacing, Fraxel, Business Development, Tattoo Removal, Laser Hair Removal, Skin Care, Small Business, Acne, Team Building, Strategic Planning, Public Speaking
Education
Durham Community College 2013 — 2015
Registered Nurse, Nursing
Cool Sculpting University 2014 — 2014
Certification, Cool Sculpting Non Invasive Fat Removal
NC Certified Nurse's Assistant 2013 — 2013
CNA, Focused One on One Patient Care Training
North Carolina State University 1997 — 1999
Master of Science, Management (Managing Hi Tech and Entreprenuership), 3.9/4
Syracuse University 1990 — 1993
M.S., Electrical Engineering
University of Minnesota-Twin Cities 1984 — 1989
Bachelor of Science (B.S.), Electrical Engineering
Azad University 1981 — 1984
Bachelor of Science (B.S.), Physics, 3.95/4.0
Pei Yao's Cadence Design Systems Experience March 2000 - June 2007
Job Senior Staff Engineer at Xilinx
Industry Computer Software
Experience
Xilinx May 2014 - Present
GLOBALFOUNDRIES March 2010 - May 2014
Mentor Graphics June 2007 - February 2010
Cadence Design Systems March 2000 - June 2007
Chartered Semiconductor June 1997 - March 2000
Education
National University of Singapore
M. S., Electrical
Xi'an Jiaotong University
B. S., Electrical and Electronic
Xilinx May 2014 - Present
GLOBALFOUNDRIES March 2010 - May 2014
Mentor Graphics June 2007 - February 2010
Cadence Design Systems March 2000 - June 2007
Chartered Semiconductor June 1997 - March 2000
Education
National University of Singapore
M. S., Electrical
Xi'an Jiaotong University
B. S., Electrical and Electronic
Chuck Castrovinci's Cadence Design Systems Experience September 1988 - December 1998
Job Local Veteran Employment Representative (LVER),
Industry Government Administration
Experience
State of California Workforce Services April 2013 - Present
State of California Employment Development Department June 2009 - April 2013
Cadence 1999 - 2008
Cadence Design 1998 - 2008
Cadence Design Systems September 1988 - December 1998
Skills
Program Management, Management, Community Outreach, Organizational..., Training, Human Resources, Team Building, Employee Relations, Leadership, Project Management, Cross-functional Team..., Customer Service, Process Improvement, Microsoft Office, Leadership Development, Strategic Planning, Policy, Project Planning
Education
National University
BBA, Business Administration
State of California Workforce Services April 2013 - Present
State of California Employment Development Department June 2009 - April 2013
Cadence 1999 - 2008
Cadence Design 1998 - 2008
Cadence Design Systems September 1988 - December 1998
Skills
Program Management, Management, Community Outreach, Organizational..., Training, Human Resources, Team Building, Employee Relations, Leadership, Project Management, Cross-functional Team..., Customer Service, Process Improvement, Microsoft Office, Leadership Development, Strategic Planning, Policy, Project Planning
Education
National University
BBA, Business Administration
Bob Widman's Cadence Design Systems Experience July 2004 - January 2009
Job Customer Support & Documentation Specialist
Industry Computer Software
Experience
Breker Verification Systems March 2013 - Present
Oasys Design Systems February 2009 - January 2014
Cadence Design Systems July 2004 - January 2009
Verisity October 1996 - November 2003
Systems Science February 1996 - September 1996
Widman Associates September 1993 - February 1996
HDL Systems January 1992 - September 1993
Cadence Design Systems March 1991 - January 1992
Gateway Design September 1989 - March 1991
Gateway Design August 1988 - September 1989
Skills
EDA, FrameMaker, Online Help, Verilog, VHDL, Customer Support, Customer Product..., Employee Training, MySQL, RoboHelp, PowerPoint, Microsoft Excel, Dreamweaver, PHP, Microsoft Word, DITA, Photoshop, Lightroom, Layout, WebWorks, Logic Synthesis, Semiconductors, ASIC, Testing, Software Documentation, Technical Writing, Simulations, Start-ups, SoC, Product Management, Perl
Education
New Mexico Highlands University
MBA, Business
University of Nebraska-Lincoln
MS, Electrical Engineering
University of Nebraska-Lincoln
BS, Mathematics
Breker Verification Systems March 2013 - Present
Oasys Design Systems February 2009 - January 2014
Cadence Design Systems July 2004 - January 2009
Verisity October 1996 - November 2003
Systems Science February 1996 - September 1996
Widman Associates September 1993 - February 1996
HDL Systems January 1992 - September 1993
Cadence Design Systems March 1991 - January 1992
Gateway Design September 1989 - March 1991
Gateway Design August 1988 - September 1989
Skills
EDA, FrameMaker, Online Help, Verilog, VHDL, Customer Support, Customer Product..., Employee Training, MySQL, RoboHelp, PowerPoint, Microsoft Excel, Dreamweaver, PHP, Microsoft Word, DITA, Photoshop, Lightroom, Layout, WebWorks, Logic Synthesis, Semiconductors, ASIC, Testing, Software Documentation, Technical Writing, Simulations, Start-ups, SoC, Product Management, Perl
Education
New Mexico Highlands University
MBA, Business
University of Nebraska-Lincoln
MS, Electrical Engineering
University of Nebraska-Lincoln
BS, Mathematics
Michael Kernin, MBA's Cadence Design Systems Experience October 2012 - Present
Job Senior Business Systems Analyst at Cadence Design Systems
Industry Information Technology and Services
Experience
Cadence Design Systems October 2012 - Present
West Valley Staffing Group October 2009 - September 2012
Cadence Design Systems July 2001 - November 2008
EDS February 1999 - June 2001
MCI Systemhouse June 1997 - February 1999
Litton, Applied Technology Division August 1991 - June 1997
General Instrument Corporation - Dalmo Victor May 1991 - August 1991
Bell Aerospace Textron November 1990 - May 1991
Bell Aerospace Textron May 1985 - November 1990
NTS Data Services May 1980 - May 1985
Skills
ABAP, Interfaces, SQL, Requirements Analysis, Visio, ERP, Program Management, Vendor Management, Software Project..., MS Project, Business Analysis, PeopleSoft, Requirements Gathering, SAP R/3, Unix, SharePoint, Integration, Process Improvement, Analysis, Business Requirements, PMP, Change Management, HRIS, SAP, Business Process, Oracle, Human Resources, Databases, Project Management, Software Development, Payroll, Software Documentation, SAP ERP, Business Process..., SDLC, Cross-functional Team..., Business Intelligence, Leadership
Education
University of Rochester - Simon Business School 1978 — 1980
MBA, Finance and Accounting
Niagara University 1974 — 1978
BA, Mathematics
Cadence Design Systems October 2012 - Present
West Valley Staffing Group October 2009 - September 2012
Cadence Design Systems July 2001 - November 2008
EDS February 1999 - June 2001
MCI Systemhouse June 1997 - February 1999
Litton, Applied Technology Division August 1991 - June 1997
General Instrument Corporation - Dalmo Victor May 1991 - August 1991
Bell Aerospace Textron November 1990 - May 1991
Bell Aerospace Textron May 1985 - November 1990
NTS Data Services May 1980 - May 1985
Skills
ABAP, Interfaces, SQL, Requirements Analysis, Visio, ERP, Program Management, Vendor Management, Software Project..., MS Project, Business Analysis, PeopleSoft, Requirements Gathering, SAP R/3, Unix, SharePoint, Integration, Process Improvement, Analysis, Business Requirements, PMP, Change Management, HRIS, SAP, Business Process, Oracle, Human Resources, Databases, Project Management, Software Development, Payroll, Software Documentation, SAP ERP, Business Process..., SDLC, Cross-functional Team..., Business Intelligence, Leadership
Education
University of Rochester - Simon Business School 1978 — 1980
MBA, Finance and Accounting
Niagara University 1974 — 1978
BA, Mathematics
Dennis Ding's Cadence Design Systems Experience 1995 - 2005
Job R&D Director at Synopsys
Industry Computer Software
Chi-Yuan Lo's Cadence Design Systems Experience October 1998 - Present
Job Engineering Group Director at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems October 1998 - Present
Bell Labs Lucent Technologies August 1984 - September 1998
Bell Labs Lucent Technologies May 1980 - August 1984
Skills
Debugging, Software Engineering, EDA, Engineering, Embedded Systems, Software Development, Perl, Simulations, Algorithms, C, Embedded Software, RTOS, ASIC
Education
Rutgers University-New Brunswick 1984 — 1992
PhD, Computer Science
The University of Texas at Austin 1976 — 1978
MS, Electrical Engineering
National Taiwan University 1970 — 1974
BS, Electrical Engineering
National Hsinchu senior high school 1967 — 1970
Cadence Design Systems October 1998 - Present
Bell Labs Lucent Technologies August 1984 - September 1998
Bell Labs Lucent Technologies May 1980 - August 1984
Skills
Debugging, Software Engineering, EDA, Engineering, Embedded Systems, Software Development, Perl, Simulations, Algorithms, C, Embedded Software, RTOS, ASIC
Education
Rutgers University-New Brunswick 1984 — 1992
PhD, Computer Science
The University of Texas at Austin 1976 — 1978
MS, Electrical Engineering
National Taiwan University 1970 — 1974
BS, Electrical Engineering
National Hsinchu senior high school 1967 — 1970
Kirk Russell's Cadence Design Systems Experience January 1998 - December 1998
Job Analog Design Engineer at Silicon Intellectual
Industry Semiconductors
Experience
Silicon Intellectual February 2009 - Present
Celis Semiconductor December 2004 - January 2009
RadChips July 2004 - November 2004
Colorado MicroDisplay February 2000 - September 2001
Lockheed Martin Space Electronics & Communications January 1999 - January 2000
Cadence Design Systems January 1998 - December 1998
IBM May 1997 - January 1998
Skills
CMOS, ASIC, Circuit Design, Analog Circuit Design, VLSI, Analog Physical Deign, Simulations, Testing, Analog, LVS, Debugging, Low-power Design, DRC, Cadence, DAC, Floorplanning, SRAM, IC, Mixed Signal, Spectre, Cadence Virtuoso
Education
North Carolina State University 1996 — 1998
MS ECE, Eletrical Engineering
coursera
Silicon Intellectual February 2009 - Present
Celis Semiconductor December 2004 - January 2009
RadChips July 2004 - November 2004
Colorado MicroDisplay February 2000 - September 2001
Lockheed Martin Space Electronics & Communications January 1999 - January 2000
Cadence Design Systems January 1998 - December 1998
IBM May 1997 - January 1998
Skills
CMOS, ASIC, Circuit Design, Analog Circuit Design, VLSI, Analog Physical Deign, Simulations, Testing, Analog, LVS, Debugging, Low-power Design, DRC, Cadence, DAC, Floorplanning, SRAM, IC, Mixed Signal, Spectre, Cadence Virtuoso
Education
North Carolina State University 1996 — 1998
MS ECE, Eletrical Engineering
coursera
Masoud Manoo's Cadence Design Systems Experience 1997 - 1999
Job Firmware Engineer at Lenovo
Industry Computer Hardware
Experience
Lenovo October 2014 - Present
IBM April 2012 - Present
CTG/IBM April 2011 - April 2012
Avocent July 2009 - April 2011
IBM August 2005 - July 2008
IBM 2005 - 2008
Synopsys 1999 - 2002
Cadence Design Systems 1997 - 1999
Synopsys 1993 - 1997
Schlumberger 1991 - 1993
Skills
C++, Linux, Embedded Systems, C, Software Design, Programming, Scripting, Software Development, Assembly, Embedded Linux, Device Drivers, Firmware, Embedded Software, Shell Scripting, Gdb, Subversion, Bash, EDA, Debugging, Testing, GNU Debugger, Software Engineering, System Architecture, Manufacturing, Perl, Unix, TCP/IP, Object Oriented Design, Hardware Architecture, Eclipse, FPGA, VHDL, ClearCase, Python, Test Automation, Operating Systems, Computer Architecture, Hardware, Verilog, ARM, Linux Kernel, Microcontrollers, Distributed Systems, ASIC, TCL, RTOS, Microprocessors, X86, UNIX
Education
North Carolina State University 1976 — 1981
BS, EE
Lenovo October 2014 - Present
IBM April 2012 - Present
CTG/IBM April 2011 - April 2012
Avocent July 2009 - April 2011
IBM August 2005 - July 2008
IBM 2005 - 2008
Synopsys 1999 - 2002
Cadence Design Systems 1997 - 1999
Synopsys 1993 - 1997
Schlumberger 1991 - 1993
Skills
C++, Linux, Embedded Systems, C, Software Design, Programming, Scripting, Software Development, Assembly, Embedded Linux, Device Drivers, Firmware, Embedded Software, Shell Scripting, Gdb, Subversion, Bash, EDA, Debugging, Testing, GNU Debugger, Software Engineering, System Architecture, Manufacturing, Perl, Unix, TCP/IP, Object Oriented Design, Hardware Architecture, Eclipse, FPGA, VHDL, ClearCase, Python, Test Automation, Operating Systems, Computer Architecture, Hardware, Verilog, ARM, Linux Kernel, Microcontrollers, Distributed Systems, ASIC, TCL, RTOS, Microprocessors, X86, UNIX
Education
North Carolina State University 1976 — 1981
BS, EE
Karthik Subramanyam's Cadence Design Systems Experience September 2014 - February 2015
Job Image Sensor Characterization Engineer at Sony Electronics
Industry Research
Experience
Sony Electronics September 2015 - Present
Kaiser Permanente March 2015 - August 2015
Cadence Design Systems September 2014 - February 2015
Cadence Design Systems July 2013 - December 2013
NDS Limited August 2011 - August 2012
Skills
C, VHDL, Cadence Virtuoso, Mentor Graphics, MPI, Microcontrollers, Testing, Matlab, Verilog, Cisco IOS, SPICE, Pearl, ModelSim, VLSI, Cadence, Embedded Systems, Perl
Education
Rochester Institute of Technology 2012 — 2014
Master's degree, Digital systems
National Institute of Technology Surat 2007 — 2011
Bachelor of Technology (B.Tech.), Electrical Engineering
Sony Electronics September 2015 - Present
Kaiser Permanente March 2015 - August 2015
Cadence Design Systems September 2014 - February 2015
Cadence Design Systems July 2013 - December 2013
NDS Limited August 2011 - August 2012
Skills
C, VHDL, Cadence Virtuoso, Mentor Graphics, MPI, Microcontrollers, Testing, Matlab, Verilog, Cisco IOS, SPICE, Pearl, ModelSim, VLSI, Cadence, Embedded Systems, Perl
Education
Rochester Institute of Technology 2012 — 2014
Master's degree, Digital systems
National Institute of Technology Surat 2007 — 2011
Bachelor of Technology (B.Tech.), Electrical Engineering
Henry Pechar's Cadence Design Systems Experience Staff engineerMotorola1991 - 2000
Job AE Mgr at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems Staff engineerMotorola1991 - 2000
Standard Microsystems Corporation 1901 - 1991
Skills
ASIC, IC, Semiconductors, Verilog, Hardware Architecture, EDA, SoC, Electronics, Perl, Integrated Circuit..., VHDL, TCL, FPGA, Debugging, Analog, Mixed Signal, Processors
Education
New York Institute of Technology 1968 — 1972
bs, Electrical Engineering
Cadence Design Systems Staff engineerMotorola1991 - 2000
Standard Microsystems Corporation 1901 - 1991
Skills
ASIC, IC, Semiconductors, Verilog, Hardware Architecture, EDA, SoC, Electronics, Perl, Integrated Circuit..., VHDL, TCL, FPGA, Debugging, Analog, Mixed Signal, Processors
Education
New York Institute of Technology 1968 — 1972
bs, Electrical Engineering
Haipin Dai's Cadence Design Systems Experience October 1987 - December 1998
Job SR. Application Consultant Manager at Synopsys
Industry Semiconductors
Experience
Synopsys December 2001 - Present
RedSwitch Inc November 2000 - November 2001
Synopsys January 1999 - November 2000
Cadence Design Systems October 1987 - December 1998
Skills
Physical Design, EDA, IC, Physical Verification, ASIC, SoC, Integration, Verilog, Semiconductors, Static Timing Analysis, VLSI, Mixed Signal, CMOS, Timing Closure
Education
University of California, Berkeley 1978 — 1980
MS, Operations Research
National Chiao Tung University 1972 — 1976
BS, Applied Mathematics
Synopsys December 2001 - Present
RedSwitch Inc November 2000 - November 2001
Synopsys January 1999 - November 2000
Cadence Design Systems October 1987 - December 1998
Skills
Physical Design, EDA, IC, Physical Verification, ASIC, SoC, Integration, Verilog, Semiconductors, Static Timing Analysis, VLSI, Mixed Signal, CMOS, Timing Closure
Education
University of California, Berkeley 1978 — 1980
MS, Operations Research
National Chiao Tung University 1972 — 1976
BS, Applied Mathematics
Meg Hung's Cadence Design Systems Experience April 2014 - April 2015
Job Sr. Engineer Manager
Industry Computer Software
Experience
Cadence Design Systems April 2014 - April 2015
Cadence Design Systems January 2007 - April 2014
Synopsys Inc August 2006 - January 2007
Aprio Technologies August 2003 - June 2006
Synopsys Inc July 2001 - August 2003
Skills
R&D, Algorithms, Software Engineering, Perl, ASIC, C++, EDA, Linux, Software Development
Education
Stanford University 1999 — 2001
Master’s Degree
National Chiao Tung University 1993 — 1998
Bachelor’s Degree
National Chiao Tung University 1993 — 1998
Bachelor’s Degree
Cadence Design Systems April 2014 - April 2015
Cadence Design Systems January 2007 - April 2014
Synopsys Inc August 2006 - January 2007
Aprio Technologies August 2003 - June 2006
Synopsys Inc July 2001 - August 2003
Skills
R&D, Algorithms, Software Engineering, Perl, ASIC, C++, EDA, Linux, Software Development
Education
Stanford University 1999 — 2001
Master’s Degree
National Chiao Tung University 1993 — 1998
Bachelor’s Degree
National Chiao Tung University 1993 — 1998
Bachelor’s Degree
Mike Kang's Cadence Design Systems Experience July 2012 - Present
Job AE Director at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2012 - Present
Sigrity, Inc. September 2009 - July 2012
Apache Design Solutions May 2009 - September 2009
Ansoft Corporation May 2005 - May 2009
Skills
EDA, Signal Integrity, Simulation
Education
Purdue University 1998 — 2000
MSEE
National Chiao Tung University 1992 — 1996
Cadence Design Systems July 2012 - Present
Sigrity, Inc. September 2009 - July 2012
Apache Design Solutions May 2009 - September 2009
Ansoft Corporation May 2005 - May 2009
Skills
EDA, Signal Integrity, Simulation
Education
Purdue University 1998 — 2000
MSEE
National Chiao Tung University 1992 — 1996
Doug Stolarz's Cadence Design Systems Experience January 2001 - September 2003
Job Principal Systems Engineer at LinQuest
Industry Defense & Space
Experience
LinQuest May 2012 - Present
MITRE June 2004 - May 2012
Cadence Design Systems January 2001 - September 2003
AT&T May 1996 - December 2000
Boeing August 1989 - April 1995
Lockheed Electronics 1981 - 1989
Education
New Jersey Institute of Technology 1981 — 1987
MSEE, Electrical Engineering
Rutgers University-New Brunswick 1973 — 1977
BA, Physics
LinQuest May 2012 - Present
MITRE June 2004 - May 2012
Cadence Design Systems January 2001 - September 2003
AT&T May 1996 - December 2000
Boeing August 1989 - April 1995
Lockheed Electronics 1981 - 1989
Education
New Jersey Institute of Technology 1981 — 1987
MSEE, Electrical Engineering
Rutgers University-New Brunswick 1973 — 1977
BA, Physics
Peter Pleshko's Cadence Design Systems Experience April 2003 - January 2010
Job Retired at Home
Industry Computer Hardware
Yen-Yu Lee's Cadence Design Systems Experience July 2006 - August 2006
Job Software Development Engineer at Amazon
Industry Electrical/Electronic Manufacturing
Experience
Amazon July 2014 - Present
ALSTOM Grid July 2012 - July 2014
ERCOT May 2011 - August 2011
Pyxis Technology May 2008 - December 2008
Academia Sinica September 2006 - June 2007
Cadence Design Systems July 2006 - August 2006
Skills
Matlab, Power Systems, Optimization, Algorithms, C++, Software Development, Mathematical Modeling, Stochastic Optimization, Mathematical Programming, Data Structures, Electricity Markets, Testing
Education
The University of Texas at Austin 2007 — 2012
Ph.D, Electrical and Computer Engineering
National Taiwan University 2002 — 2006
B.S., Electrical Engineering
Amazon July 2014 - Present
ALSTOM Grid July 2012 - July 2014
ERCOT May 2011 - August 2011
Pyxis Technology May 2008 - December 2008
Academia Sinica September 2006 - June 2007
Cadence Design Systems July 2006 - August 2006
Skills
Matlab, Power Systems, Optimization, Algorithms, C++, Software Development, Mathematical Modeling, Stochastic Optimization, Mathematical Programming, Data Structures, Electricity Markets, Testing
Education
The University of Texas at Austin 2007 — 2012
Ph.D, Electrical and Computer Engineering
National Taiwan University 2002 — 2006
B.S., Electrical Engineering
Chin-Chih Chang's Cadence Design Systems Experience October 2006 - Present
Job Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems October 2006 - Present
Cadence Design Systems January 2004 - October 2006
Cadence Design Systems June 2002 - January 2004
Education
University of California, Los Angeles 1993 — 2002
Ph.D., Computer Science
Stony Brook University 1991 — 1993
M.S., Computer Science
National Taiwan University 1985 — 1989
B.S. in Engineering, Computer Science & Information Engineering
Cadence Design Systems October 2006 - Present
Cadence Design Systems January 2004 - October 2006
Cadence Design Systems June 2002 - January 2004
Education
University of California, Los Angeles 1993 — 2002
Ph.D., Computer Science
Stony Brook University 1991 — 1993
M.S., Computer Science
National Taiwan University 1985 — 1989
B.S. in Engineering, Computer Science & Information Engineering
John Patty's Cadence Design Systems Experience October 2013 - Present
Job Lead Design Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems October 2013 - Present
Open-Silicon August 2012 - October 2013
Atmel November 2006 - August 2012
IBM January 2004 - November 2006
Kidde Aerospace January 2003 - January 2004
Silicon Access Networks January 2001 - May 2002
Ericsson January 1997 - January 2001
Skills
Static Timing Analysis, ASIC, Verilog, RTL design, Functional Verification, EDA, Logic Design, SoC, TCL, ARM, Embedded Systems, IC, Hardware Architecture, Debugging, VHDL, FPGA, Semiconductors, Cadence, Perl, Microcontrollers, Xilinx, DFT, Scan Insertion, ATPG, AMBA AHB, AXI, Formal Verification, IP, HMC, Logic Synthesis, SERDES, SystemVerilog, Processors, Timing Closure, RTL coding, Microprocessors, Timing, Primetime, VLSI, NCSim
Education
North Carolina State University 1995 — 1997
MS, Computer Engineering
North Carolina State University 1990 — 1995
BS, Computer Engineering
Cadence Design Systems October 2013 - Present
Open-Silicon August 2012 - October 2013
Atmel November 2006 - August 2012
IBM January 2004 - November 2006
Kidde Aerospace January 2003 - January 2004
Silicon Access Networks January 2001 - May 2002
Ericsson January 1997 - January 2001
Skills
Static Timing Analysis, ASIC, Verilog, RTL design, Functional Verification, EDA, Logic Design, SoC, TCL, ARM, Embedded Systems, IC, Hardware Architecture, Debugging, VHDL, FPGA, Semiconductors, Cadence, Perl, Microcontrollers, Xilinx, DFT, Scan Insertion, ATPG, AMBA AHB, AXI, Formal Verification, IP, HMC, Logic Synthesis, SERDES, SystemVerilog, Processors, Timing Closure, RTL coding, Microprocessors, Timing, Primetime, VLSI, NCSim
Education
North Carolina State University 1995 — 1997
MS, Computer Engineering
North Carolina State University 1990 — 1995
BS, Computer Engineering
Jeffrey Hwang's Cadence Design Systems Experience September 2002 - June 2013
Job Expert User, Emulation, Design Verification and Prototyping
Industry Computer Software
Experience
Startup October 2013 - March 2014
Cadence Design Systems September 2002 - June 2013
Cadence Design Systems September 1998 - February 2002
Skills
EDA, Integrated Circuit..., ASIC, SoC, Verilog, Microwave, TCL, IC, Debugging, Semiconductors, Embedded Systems, FPGA, VLSI, Mixed Signal, Perl, Static Timing Analysis, SystemVerilog, emulation, Risk Management, Project Management, Configuration Management, Testing, Emulation, Simulations, Low-power Design, Cadence, UVM
Education
University of Michigan 1989 — 1990
Master
National Taiwan University 1984 — 1987
BS
Startup October 2013 - March 2014
Cadence Design Systems September 2002 - June 2013
Cadence Design Systems September 1998 - February 2002
Skills
EDA, Integrated Circuit..., ASIC, SoC, Verilog, Microwave, TCL, IC, Debugging, Semiconductors, Embedded Systems, FPGA, VLSI, Mixed Signal, Perl, Static Timing Analysis, SystemVerilog, emulation, Risk Management, Project Management, Configuration Management, Testing, Emulation, Simulations, Low-power Design, Cadence, UVM
Education
University of Michigan 1989 — 1990
Master
National Taiwan University 1984 — 1987
BS
Chunkuen Ho's Cadence Design Systems Experience 2000 - Present
Job Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems 2000 - Present
DSO National Laboratories September 1994 - July 1999
University of Chicago September 1989 - June 1994
Skills
Object Oriented Design, C++, C, Multithreading, Graph Theory, Software Engineering, EDA, Software Development, TCL, Distributed Systems, Python, Programming, Simulations, Software Design, Cloud Computing
Education
The University of Chicago 1989 — 1994
Ph.D., Computer Science
National University of Singapore 1985 — 1989
Bachelor of Science (BSc), Mathematics
Cadence Design Systems 2000 - Present
DSO National Laboratories September 1994 - July 1999
University of Chicago September 1989 - June 1994
Skills
Object Oriented Design, C++, C, Multithreading, Graph Theory, Software Engineering, EDA, Software Development, TCL, Distributed Systems, Python, Programming, Simulations, Software Design, Cloud Computing
Education
The University of Chicago 1989 — 1994
Ph.D., Computer Science
National University of Singapore 1985 — 1989
Bachelor of Science (BSc), Mathematics
Jiancheng Lin's Cadence Design Systems Experience March 2015 - Present
Job Principal Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems March 2015 - Present
Cadence Design Systems January 2011 - February 2015
Mobile App Development August 2010 - December 2010
SpringSoft September 2007 - July 2010
SpringSoft January 2006 - September 2007
Skills
C, EDA, Verilog, SystemVerilog, Debugging, C++, SystemC, Perl, Software Design Patterns, Software Project..., Formal Verification, OpenCL, Compilers, Semiconductors, ASIC, Integrated Circuit..., VLSI, Simulations, Logic Synthesis, SoC
Education
National Tsing Hua University 2003 — 2005
Master, Computer Science
National Chung Cheng University 2000 — 2003
Bachelor, Computer Science
Cadence Design Systems March 2015 - Present
Cadence Design Systems January 2011 - February 2015
Mobile App Development August 2010 - December 2010
SpringSoft September 2007 - July 2010
SpringSoft January 2006 - September 2007
Skills
C, EDA, Verilog, SystemVerilog, Debugging, C++, SystemC, Perl, Software Design Patterns, Software Project..., Formal Verification, OpenCL, Compilers, Semiconductors, ASIC, Integrated Circuit..., VLSI, Simulations, Logic Synthesis, SoC
Education
National Tsing Hua University 2003 — 2005
Master, Computer Science
National Chung Cheng University 2000 — 2003
Bachelor, Computer Science
Satheesh Chellappan's Cadence Design Systems Experience April 2010 - October 2011
Job Silicon Architecture Engineer at Intel Corporation
Industry Semiconductors
Experience
Intel Corporation October 2011 - Present
Cadence Design Systems April 2010 - October 2011
Gennum Corporation 2008 - May 2011
Synopsys 2000 - 2008
Tata Elxsi 1996 - 1996
Education
National University 2004 — 2005
MBA, Marketing
University of Madras 1992 — 1996
BE, Electronics
Intel Corporation October 2011 - Present
Cadence Design Systems April 2010 - October 2011
Gennum Corporation 2008 - May 2011
Synopsys 2000 - 2008
Tata Elxsi 1996 - 1996
Education
National University 2004 — 2005
MBA, Marketing
University of Madras 1992 — 1996
BE, Electronics
Leslie Lai's Cadence Design Systems Experience EngineerSynopsysAugust 1999 - September 2004
Job Sr. Principal Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems EngineerSynopsysAugust 1999 - September 2004
Education
The University of Texas at Austin 1992 — 1999
Ph.D., Electrical and Computer Engineering
National Chiao Tung University 1986 — 1990
BS, Control Engineering
Jianguo sr. high
Cadence Design Systems EngineerSynopsysAugust 1999 - September 2004
Education
The University of Texas at Austin 1992 — 1999
Ph.D., Electrical and Computer Engineering
National Chiao Tung University 1986 — 1990
BS, Control Engineering
Jianguo sr. high
Wenn Chen's Cadence Design Systems Experience December 2001 - February 2003
Job Semiconductors and VLSI Design Professional
Industry Semiconductors
Experience
Synopsys February 2003 - Present
Cadence Design Systems December 2001 - February 2003
Arcadia Design 1997 - 2000
Simplex Solution (Now Cadence) 1996 - 1997
Meta Software (now Synopsys) 1995 - 1996
VLSI Technology 1994 - 1995
Actel 1991 - 1994
National Semiconductor 1987 - 1991
Education
UC Santa Barbara 1986 — 1987
M.S.E.E., Solid State Physics
Univ of Florida 1984 — 1985
M.S. Ch.E., GaAs MOCVD
National Taiwan University 1979 — 1982
BS, Chemical Engineering
Synopsys February 2003 - Present
Cadence Design Systems December 2001 - February 2003
Arcadia Design 1997 - 2000
Simplex Solution (Now Cadence) 1996 - 1997
Meta Software (now Synopsys) 1995 - 1996
VLSI Technology 1994 - 1995
Actel 1991 - 1994
National Semiconductor 1987 - 1991
Education
UC Santa Barbara 1986 — 1987
M.S.E.E., Solid State Physics
Univ of Florida 1984 — 1985
M.S. Ch.E., GaAs MOCVD
National Taiwan University 1979 — 1982
BS, Chemical Engineering
Chung-Wen Albert Tsao's Cadence Design Systems Experience April 2002 - November 2013
Job Experienced Software Engineer
Industry Computer Software
Experience
W3 coding school, January 2014 - Present
Cadence Design Systems April 2002 - November 2013
Celestry Design Technologies October 1998 - April 2002
Cadence Design Systems October 1996 - October 1998
Skills
C++, EDA, Verilog, Embedded Systems, Floorplanning, VLSI, Debugging, Software Development, Perl, Place & Route, Unix, Software Engineering, Multithreading, Semiconductors, Algorithms, C, Semiconductor Industry, Linux, Clock Tree Synthesis, Digital Signal..., SoC, System Architecture
Education
University of California, Los Angeles 1990 — 1996
phd, computer scienc
National Taiwan University 1980 — 1984
Bachelor of Science (BS), Electrical and Electronics Engineering
W3 coding school, January 2014 - Present
Cadence Design Systems April 2002 - November 2013
Celestry Design Technologies October 1998 - April 2002
Cadence Design Systems October 1996 - October 1998
Skills
C++, EDA, Verilog, Embedded Systems, Floorplanning, VLSI, Debugging, Software Development, Perl, Place & Route, Unix, Software Engineering, Multithreading, Semiconductors, Algorithms, C, Semiconductor Industry, Linux, Clock Tree Synthesis, Digital Signal..., SoC, System Architecture
Education
University of California, Los Angeles 1990 — 1996
phd, computer scienc
National Taiwan University 1980 — 1984
Bachelor of Science (BS), Electrical and Electronics Engineering
B.M.Giridhar Nayak's Cadence Design Systems Experience July 2014 - July 2015
Job Graduate Student, University of California San Diego
Industry Semiconductors
Experience
Cadence Design Systems July 2014 - July 2015
Cadence Design Systems [IP Group, Cosmic R&D] July 2012 - June 2014
Siemens AG May 2010 - July 2010
Skills
Analog Circuit Design, VLSI, Verilog, Mixed Signal, CMOS, Cadence Virtuoso, Analog, ASIC, VHDL, Circuit Design, EDA, Spectre, Power Management, SoC, DRC, Team Management
Education
University of California, San Diego 2015 — 2017
Master’s Degree, Electrical Engineering
National Institute of Technology Karnataka 2008 — 2012
Bachelor of Technology, Electronics and Communication
St. Joseph's Boys' High School Bangalore 2000 — 2008
ISC, Physics, Chemistry, Mathematics, Computer Science
Cadence Design Systems July 2014 - July 2015
Cadence Design Systems [IP Group, Cosmic R&D] July 2012 - June 2014
Siemens AG May 2010 - July 2010
Skills
Analog Circuit Design, VLSI, Verilog, Mixed Signal, CMOS, Cadence Virtuoso, Analog, ASIC, VHDL, Circuit Design, EDA, Spectre, Power Management, SoC, DRC, Team Management
Education
University of California, San Diego 2015 — 2017
Master’s Degree, Electrical Engineering
National Institute of Technology Karnataka 2008 — 2012
Bachelor of Technology, Electronics and Communication
St. Joseph's Boys' High School Bangalore 2000 — 2008
ISC, Physics, Chemistry, Mathematics, Computer Science
Chirayu Hardikar's Cadence Design Systems Experience
Job Lead Design Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems
Skills
Verilog, EDA, ASIC, SoC, Semiconductors, IC, Perl, VLSI, Debugging, Static Timing Analysis, TCL, C, Place & Route, Timing Closure
Education
MS University, Baroda
North Carolina State University
MS, Electrical and Computer Engineering
Cadence Design Systems
Skills
Verilog, EDA, ASIC, SoC, Semiconductors, IC, Perl, VLSI, Debugging, Static Timing Analysis, TCL, C, Place & Route, Timing Closure
Education
MS University, Baroda
North Carolina State University
MS, Electrical and Computer Engineering
Szu-Tsung Cheng's Cadence Design Systems Experience 1996 - 1998
Job Senior Staff R&D at Synopsys
Industry Computer Software
Experience
Synopsys 2010 - Present
Incentia Design Systems, Inc. 1998 - 2010
Cadence Design Systems 1996 - 1998
Skills
RTL coding, RTL..., Multithreading, Algorithms, Distributed Algorithms, Static Timing Analysis, Logic Synthesis, Simulations, Formal Verification, VHDL, EDA, Software Development, Debugging, Verilog, C, ASIC, Perl, TCL, C++, Software Engineering, Semiconductors, VLSI
Education
University of California, Berkeley 1993 — 1998
PhD, Computer Science
University of California, Berkeley 1991 — 1993
M.S., Computer Science
National Taiwan University 1985 — 1989
Bachelor, Computer Science
Synopsys 2010 - Present
Incentia Design Systems, Inc. 1998 - 2010
Cadence Design Systems 1996 - 1998
Skills
RTL coding, RTL..., Multithreading, Algorithms, Distributed Algorithms, Static Timing Analysis, Logic Synthesis, Simulations, Formal Verification, VHDL, EDA, Software Development, Debugging, Verilog, C, ASIC, Perl, TCL, C++, Software Engineering, Semiconductors, VLSI
Education
University of California, Berkeley 1993 — 1998
PhD, Computer Science
University of California, Berkeley 1991 — 1993
M.S., Computer Science
National Taiwan University 1985 — 1989
Bachelor, Computer Science
Hancheng Liang's Cadence Design Systems Experience 2003 - 2006
Job VP of R&D at ProPlus Design Solutions, Inc.
Industry Semiconductors
Experience
ProPlus Design Solutions, Inc. January 2007 - Present
Cadence Design Systems 2003 - 2006
Education
New Jersey Institute of Technology 1992 — 1996
PhD, EE
South China University of Technology 1976 — 1984
MS, Physics
ProPlus Design Solutions, Inc. January 2007 - Present
Cadence Design Systems 2003 - 2006
Education
New Jersey Institute of Technology 1992 — 1996
PhD, EE
South China University of Technology 1976 — 1984
MS, Physics
Lannie Weng's Cadence Design Systems Experience March 2015 - Present
Job Sr Principal Product Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems March 2015 - Present
Synopsys April 2012 - February 2015
Magma Design Automation December 2010 - April 2012
Magma Design Automation August 2007 - December 2010
Magma Design Automation December 2003 - May 2007
ALI Acer Labs. Corporation June 2000 - November 2003
Skills
Static Timing Analysis, TCL, Physical Design, ASIC, EDA, Timing Closure, VLSI, Physical Verification, SoC, Primetime, IC, DRC, Low-power Design, Verilog, Floorplanning
Education
National Taiwan University 2006 — 2008
Master of Science, Electrical Engineering
Cadence Design Systems March 2015 - Present
Synopsys April 2012 - February 2015
Magma Design Automation December 2010 - April 2012
Magma Design Automation August 2007 - December 2010
Magma Design Automation December 2003 - May 2007
ALI Acer Labs. Corporation June 2000 - November 2003
Skills
Static Timing Analysis, TCL, Physical Design, ASIC, EDA, Timing Closure, VLSI, Physical Verification, SoC, Primetime, IC, DRC, Low-power Design, Verilog, Floorplanning
Education
National Taiwan University 2006 — 2008
Master of Science, Electrical Engineering
Jeff Shafer's Cadence Design Systems Experience 1998 - 2001
Job Sr. Principle Design Engineer, Cadence Design Systems
Industry Semiconductors
Experience
Qualcomm July 2011 - April 2015
Rapid Bridge LLC March 2010 - February 2012
Maxim Integrated Products 2001 - 2010
Cadence Design Systems 1998 - 2001
ZDBOP 1996 - 1998
Education
North Carolina State University 1992 — 1999
MSEE, Electrical Engineering
Qualcomm July 2011 - April 2015
Rapid Bridge LLC March 2010 - February 2012
Maxim Integrated Products 2001 - 2010
Cadence Design Systems 1998 - 2001
ZDBOP 1996 - 1998
Education
North Carolina State University 1992 — 1999
MSEE, Electrical Engineering
Randy Hwu's Cadence Design Systems Experience 2000 - 2003
Job Principal Member Technical Staff at Draper Laboratory
Industry Defense & Space
Experience
Charles Stark Draper Laboratory June 2006 - Present
Navic Networks 2004 - 2006
Suntron Corporation 2003 - 2004
Cadence Design Systems 2000 - 2003
Schneider Automation 1985 - 2000
PlantStar Inc 1983 - 1985
Duracell 1981 - 1983
Education
The Ohio State University 1979 — 1981
Master of Science (MS), Electrical and Electronics Engineering
National Tsing Hua University
Bachelor of Science (BS), Nuclear Engineering
Charles Stark Draper Laboratory June 2006 - Present
Navic Networks 2004 - 2006
Suntron Corporation 2003 - 2004
Cadence Design Systems 2000 - 2003
Schneider Automation 1985 - 2000
PlantStar Inc 1983 - 1985
Duracell 1981 - 1983
Education
The Ohio State University 1979 — 1981
Master of Science (MS), Electrical and Electronics Engineering
National Tsing Hua University
Bachelor of Science (BS), Nuclear Engineering
John Paul Saavedra's Cadence Design Systems Experience February 1998 - Present
Job Principal Design Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems February 1998 - Present
Mitsubishi Corporation July 1993 - February 1998
Skills
Verilog, ASIC, TCL, Physical Design, RTL design, IC, SoC
Education
North Carolina State University
Bachelor of Science (B.S.), Computer Engineering
North Carolina State University
Bachelor of Science (B.S.), Electrical Engineering
Cadence Design Systems February 1998 - Present
Mitsubishi Corporation July 1993 - February 1998
Skills
Verilog, ASIC, TCL, Physical Design, RTL design, IC, SoC
Education
North Carolina State University
Bachelor of Science (B.S.), Computer Engineering
North Carolina State University
Bachelor of Science (B.S.), Electrical Engineering
CP Chou's Cadence Design Systems Experience 2005 - October 2013
Job Sr. Member, Technical at Synopsys
Industry Computer Hardware
Experience
Synopsys November 2013 - Present
Cadence Design Systems 2005 - October 2013
Axis System Incorporation 2001 - 2005
C-Cube Microsystems 1999 - 2000
Skills
High Performance..., Digital Signal..., Embedded Systems, Robotics, Software Engineering, Software Design, Software Development, Device Drivers, Firmware, FPGA, ASIC, Logic Design, Simulations, Hardware, Computer Hardware, Hardware Architecture, System Architecture, Systems Engineering, System Design, Engineering Management, Project Management, Matlab, Perl, C++, C, Verilog
Education
University of Washington 1990 — 1996
MS, PhD, Electrical Engineering
National Taiwan University 1984 — 1988
Bachelor of Science (BS), Electrical Engineering
Synopsys November 2013 - Present
Cadence Design Systems 2005 - October 2013
Axis System Incorporation 2001 - 2005
C-Cube Microsystems 1999 - 2000
Skills
High Performance..., Digital Signal..., Embedded Systems, Robotics, Software Engineering, Software Design, Software Development, Device Drivers, Firmware, FPGA, ASIC, Logic Design, Simulations, Hardware, Computer Hardware, Hardware Architecture, System Architecture, Systems Engineering, System Design, Engineering Management, Project Management, Matlab, Perl, C++, C, Verilog
Education
University of Washington 1990 — 1996
MS, PhD, Electrical Engineering
National Taiwan University 1984 — 1988
Bachelor of Science (BS), Electrical Engineering
Gabe K Li's Cadence Design Systems Experience July 1997 - April 2001
Job Physical Design Engineer at Microsoft ( contract )
Industry Computer Software
Experience
Microsoft September 2015 - Present
Qualcomm October 2014 - September 2015
Embedded November 2013 - June 2014
Synopsys May 2012 - September 2013
Synopsys April 2006 - May 2012
Synopsys July 2004 - June 2006
Microsoft February 2004 - June 2004
MIPS Technologies April 2001 - September 2003
Cadence Design Systems July 1997 - April 2001
HAL Computer Systems May 1996 - June 1997
Skills
Static Timing Analysis, Timing Closure, IC Compiler, Design Compiler, Low-power Design, Perl, Synopsys Primetime, Python, Verilog, TCL, Scripting, Object Oriented Perl, C, Linux, MySQL, Microarchitecture, Unix Shell Scripting, DFT, Synopsys tools, Data Analysis, Computer Language, Signal Integrity, Shell Scripting, HTML scripting, Semiconductor Industry, PowerPoint, Test Automation, Formal Verification, Functional Verification, Microsoft Excel, Microsoft Word, Microsoft Office
Education
University of Southern California
Master of Science (MS), Electrical and Electronics Engineering
National Tsing Hua University
Bachelor of Science (BS), Electrical and Electronics Engineering
Microsoft September 2015 - Present
Qualcomm October 2014 - September 2015
Embedded November 2013 - June 2014
Synopsys May 2012 - September 2013
Synopsys April 2006 - May 2012
Synopsys July 2004 - June 2006
Microsoft February 2004 - June 2004
MIPS Technologies April 2001 - September 2003
Cadence Design Systems July 1997 - April 2001
HAL Computer Systems May 1996 - June 1997
Skills
Static Timing Analysis, Timing Closure, IC Compiler, Design Compiler, Low-power Design, Perl, Synopsys Primetime, Python, Verilog, TCL, Scripting, Object Oriented Perl, C, Linux, MySQL, Microarchitecture, Unix Shell Scripting, DFT, Synopsys tools, Data Analysis, Computer Language, Signal Integrity, Shell Scripting, HTML scripting, Semiconductor Industry, PowerPoint, Test Automation, Formal Verification, Functional Verification, Microsoft Excel, Microsoft Word, Microsoft Office
Education
University of Southern California
Master of Science (MS), Electrical and Electronics Engineering
National Tsing Hua University
Bachelor of Science (BS), Electrical and Electronics Engineering
Hewlett-Packard
SAP
Symantec
Intuit
HP
salesforce.com
Bloomberg LP
Autodesk