Cadence Design Systems
Industry: Software company
DescriptionCadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. CEO: Lip-Bu Tan (Jan 2009–) Headquarters: San Jose, California, United States Revenue: 1.816 billion USD (2016) Subsidiaries: Sigrity, Tensilica, Chip Estimate Corp, nusemi inc,
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Cadence Design Systems Employees
Employee
Years
Job
Industry
Rajeev Ranjan Rajeev Ranjan's Cadence Design Systems Experience June 2014 - Present
Job Sr. Group Director at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems June 2014 - Present
Jasper Design Automation April 2006 - June 2014
Jasper Design Automation September 2003 - March 2006
Real Intent May 1999 - September 2003
Synopsys October 1997 - May 1999
Cadence Design Systems, Berkeley Labs 1997 - 1997
Skills
Formal Verification, Semiconductors, SystemVerilog, Simulations, Functional Verification, Debugging, Logic Synthesis, FPGA, ASIC, Optimization, Testing, Optimizations, EDA, SoC, Verilog, Product Management, Start-ups, Engineering Management
Education
University of Pennsylvania - The Wharton School 2013 — 2015
Master of Business Administration (M.B.A.), Entrepreneurship/Entrepreneurial Studies, Management
University of California, Berkeley 1992 — 1997
Ph.D., Electricial Engineering and Computer Science
University of Illinois at Urbana-Champaign 1991 — 1992
M.S., Electrical Engineering
Indian Institute of Technology, Kanpur 1986 — 1990
B. Tech., Electrical Engineering, 9.8/10.0
Science College, Patna University 1984 — 1986
Intermediate of Science, Mathematics
Cadence Design Systems June 2014 - Present
Jasper Design Automation April 2006 - June 2014
Jasper Design Automation September 2003 - March 2006
Real Intent May 1999 - September 2003
Synopsys October 1997 - May 1999
Cadence Design Systems, Berkeley Labs 1997 - 1997
Skills
Formal Verification, Semiconductors, SystemVerilog, Simulations, Functional Verification, Debugging, Logic Synthesis, FPGA, ASIC, Optimization, Testing, Optimizations, EDA, SoC, Verilog, Product Management, Start-ups, Engineering Management
Education
University of Pennsylvania - The Wharton School 2013 — 2015
Master of Business Administration (M.B.A.), Entrepreneurship/Entrepreneurial Studies, Management
University of California, Berkeley 1992 — 1997
Ph.D., Electricial Engineering and Computer Science
University of Illinois at Urbana-Champaign 1991 — 1992
M.S., Electrical Engineering
Indian Institute of Technology, Kanpur 1986 — 1990
B. Tech., Electrical Engineering, 9.8/10.0
Science College, Patna University 1984 — 1986
Intermediate of Science, Mathematics
Aayush Pathak Aayush Pathak's Cadence Design Systems Experience October 2011 - August 2014
Job Teaching Mentor at University of Southern California
Industry Semiconductors
Experience
University of Southern California January 2015 - Present
Cadence Design Systems October 2011 - August 2014
Cadence Design Systems October 2011 - August 2014
Wipro Technologies June 2010 - September 2011
Power Grid Corporation of India Ltd May 2009 - July 2009
Skills
Physical Design, DFT, Front End Verification..., VLSI, Verilog, Verification, RTL coding, SystemVerilog, Bluetooth, Static Timing Analysis, Cadence, Functional Verification, Formal Verification, VHDL, EDA, FPGA, RTL design, TCL, ASIC, Timing Closure, Logic Synthesis, Integrated Circuit..., DRC, NCSim, ModelSim, Primetime, Debugging, Physical Verification, Cadence Virtuoso, LVS, RTL Design
Education
University of Southern California 2014 — 2015
Master's Degree, VLSI Design
Indian Institute of Technology, Delhi 2012 — 2013
Specialization in CAD of VLSI, CAD of VLSI, Distinction
Amity School of Engineering & Technology, Amity University 2006 — 2010
Bachelor's Degree, Electronics and Communication Engineering, First Class with Distinction
Somerville School 1999 — 2006
High School, Natural Sciences, Distinction
University of Southern California January 2015 - Present
Cadence Design Systems October 2011 - August 2014
Cadence Design Systems October 2011 - August 2014
Wipro Technologies June 2010 - September 2011
Power Grid Corporation of India Ltd May 2009 - July 2009
Skills
Physical Design, DFT, Front End Verification..., VLSI, Verilog, Verification, RTL coding, SystemVerilog, Bluetooth, Static Timing Analysis, Cadence, Functional Verification, Formal Verification, VHDL, EDA, FPGA, RTL design, TCL, ASIC, Timing Closure, Logic Synthesis, Integrated Circuit..., DRC, NCSim, ModelSim, Primetime, Debugging, Physical Verification, Cadence Virtuoso, LVS, RTL Design
Education
University of Southern California 2014 — 2015
Master's Degree, VLSI Design
Indian Institute of Technology, Delhi 2012 — 2013
Specialization in CAD of VLSI, CAD of VLSI, Distinction
Amity School of Engineering & Technology, Amity University 2006 — 2010
Bachelor's Degree, Electronics and Communication Engineering, First Class with Distinction
Somerville School 1999 — 2006
High School, Natural Sciences, Distinction
Ahmed Higazi, MBA, PMP, CSM Ahmed Higazi, MBA, PMP, CSM's Cadence Design Systems Experience June 1997 - September 2004
Job Technical Project Manager at Symantec
Industry Information Technology and Services
Experience
Symantec April 2015 - Present
SuccessFactors November 2014 - March 2015
Kaiser Permanente May 2014 - September 2014
Walmart eCommerce July 2013 - May 2014
CAIO Systems March 2011 - June 2013
Wells Fargo Bank July 2009 - December 2010
Katmai Technologies January 2005 - December 2008
Cadence Design Systems June 1997 - September 2004
Globalstar September 1996 - June 1997
Seagate Software March 1994 - September 1996
Education
University of Phoenix 2001 — 2003
MBA
University of California, Berkeley 2005 — 2006
Certificate Program
Heidelberg University 1984 — 1986
Symantec April 2015 - Present
SuccessFactors November 2014 - March 2015
Kaiser Permanente May 2014 - September 2014
Walmart eCommerce July 2013 - May 2014
CAIO Systems March 2011 - June 2013
Wells Fargo Bank July 2009 - December 2010
Katmai Technologies January 2005 - December 2008
Cadence Design Systems June 1997 - September 2004
Globalstar September 1996 - June 1997
Seagate Software March 1994 - September 1996
Education
University of Phoenix 2001 — 2003
MBA
University of California, Berkeley 2005 — 2006
Certificate Program
Heidelberg University 1984 — 1986
Lynnette M Leon Guerrero Lynnette M Leon Guerrero's Cadence Design Systems Experience 2000 - 2010
Job IT Analyst at Francis Ford Coppola Winery
Industry Information Technology and Services
Experience
Francis Ford Coppola Winery August 2012 - Present
Cadence Design Systems 2000 - 2010
Cadence Design Systems 2007 - 2009
Bank of America May 2001 - August 2001
Skills
Dreamweaver, Visual Studio, Windows, Cloud Computing, Software Project..., Software Development, Integration
Education
Solano Community College
Small Business Program
Heald College
Associates in Applied Science Degree, Networking Technology
Heald College
Associates in Applied Science Degree, Computer Technology
Francis Ford Coppola Winery August 2012 - Present
Cadence Design Systems 2000 - 2010
Cadence Design Systems 2007 - 2009
Bank of America May 2001 - August 2001
Skills
Dreamweaver, Visual Studio, Windows, Cloud Computing, Software Project..., Software Development, Integration
Education
Solano Community College
Small Business Program
Heald College
Associates in Applied Science Degree, Networking Technology
Heald College
Associates in Applied Science Degree, Computer Technology
Avi Gupta Avi Gupta's Cadence Design Systems Experience March 1998 - October 1999
Job President & CEO at SmartZip Analytics, Inc.
Industry Computer Software
Experience
SmartZip Analytics, Inc. February 2008 - Present
Mentor Graphics 2003 - 2007
Allegis Corp. 2002 - 2003
HAHT Commerce (via acquisition of arcadiaOne) December 2001 - June 2002
arcadiaOne (acquired by HAHT) March 2000 - December 2001
Cadence Design Systems March 1998 - October 1999
Intel Corp. October 1991 - March 1998
Skills
Product Management, Product Marketing, Enterprise Software, Business Development, Analytics, E-commerce, Strategy, Marketing Management, Real Estate, Technical Marketing, EDA, SaaS, Lead Generation, enterprise sales, Operations Management, corporate marketing, Channel Partners, Product Strategies, Marketing, New Business Development, Entrepreneurship, Sales, CEOs, Competitive Analysis, Start-ups, Salesforce.com, Complex Sales, Leadership, Business Strategy, Management
Education
University of California, Berkeley, Haas School of Business 2007 — 2007
Executive Development
University of Michigan 1994 — 1997
Ph.D.
University of California, Berkeley 1989 — 1991
MS
Indian Institute of Technology, Kharagpur 1985 — 1989
B.S.
M.E.S. College
SmartZip Analytics, Inc. February 2008 - Present
Mentor Graphics 2003 - 2007
Allegis Corp. 2002 - 2003
HAHT Commerce (via acquisition of arcadiaOne) December 2001 - June 2002
arcadiaOne (acquired by HAHT) March 2000 - December 2001
Cadence Design Systems March 1998 - October 1999
Intel Corp. October 1991 - March 1998
Skills
Product Management, Product Marketing, Enterprise Software, Business Development, Analytics, E-commerce, Strategy, Marketing Management, Real Estate, Technical Marketing, EDA, SaaS, Lead Generation, enterprise sales, Operations Management, corporate marketing, Channel Partners, Product Strategies, Marketing, New Business Development, Entrepreneurship, Sales, CEOs, Competitive Analysis, Start-ups, Salesforce.com, Complex Sales, Leadership, Business Strategy, Management
Education
University of California, Berkeley, Haas School of Business 2007 — 2007
Executive Development
University of Michigan 1994 — 1997
Ph.D.
University of California, Berkeley 1989 — 1991
MS
Indian Institute of Technology, Kharagpur 1985 — 1989
B.S.
M.E.S. College
Jun Gao Jun Gao's Cadence Design Systems Experience April 2015 - Present
Job Sr. Principal Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems April 2015 - Present
ANSYS, Inc. September 2012 - Present
ANSYS, Inc. February 2009 - August 2012
ANSYS, Inc. August 2006 - February 2009
Skills
Power Integrity, Electronics cooling, High Performance..., Computational..., Electromagnetic..., Signal Integrity, Power Electronics, Simulations, Algorithms, Numerical Analysis, System On Chip, Unix / Linux, C / C++ / C#, TCL / Python / Matlab, C++, Modeling, C, Signal Processing, Engineering, Fortran, ANSYS
Education
Huazhong University of Science and Technology
B.Engineering, B. Economics
Michigan State University
Ph.D, Electrical and Computer Engineering
Cadence Design Systems April 2015 - Present
ANSYS, Inc. September 2012 - Present
ANSYS, Inc. February 2009 - August 2012
ANSYS, Inc. August 2006 - February 2009
Skills
Power Integrity, Electronics cooling, High Performance..., Computational..., Electromagnetic..., Signal Integrity, Power Electronics, Simulations, Algorithms, Numerical Analysis, System On Chip, Unix / Linux, C / C++ / C#, TCL / Python / Matlab, C++, Modeling, C, Signal Processing, Engineering, Fortran, ANSYS
Education
Huazhong University of Science and Technology
B.Engineering, B. Economics
Michigan State University
Ph.D, Electrical and Computer Engineering
Jackey Yan Jackey Yan's Cadence Design Systems Experience June 2013 - Present
Job Principal Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems June 2013 - Present
Cadence Design Systems November 2010 - June 2013
Xilinx Research Labs May 2010 - October 2010
Cadence Research Labs May 2007 - August 2007
Skills
EDA, Programming, Linux, Python, Optimizations, C/C++ STL, Data Structures, VLSI CAD, Perl Script, Algorithm Design, Embedded Software, Software Development, Distributed Systems, VHDL, Verilog, C++, Optimization, Perl, TCL, Algorithms
Education
Iowa State University 2006 — 2011
Ph.D., Computer Engineering
Huazhong University of Science and Technology 2002 — 2006
B.S., Automation
Cadence Design Systems June 2013 - Present
Cadence Design Systems November 2010 - June 2013
Xilinx Research Labs May 2010 - October 2010
Cadence Research Labs May 2007 - August 2007
Skills
EDA, Programming, Linux, Python, Optimizations, C/C++ STL, Data Structures, VLSI CAD, Perl Script, Algorithm Design, Embedded Software, Software Development, Distributed Systems, VHDL, Verilog, C++, Optimization, Perl, TCL, Algorithms
Education
Iowa State University 2006 — 2011
Ph.D., Computer Engineering
Huazhong University of Science and Technology 2002 — 2006
B.S., Automation
Satya Nistala Satya Nistala's Cadence Design Systems Experience July 1998 - April 2000
Job Engineer at Intel Corporation
Industry Wireless
Experience
Intel Corporation February 2013 - Present
Motorola Mobility ( Google) July 2005 - February 2013
Alcatel September 2004 - July 2005
Marconi 2000 - September 2004
Cadence design systems July 1998 - April 2000
C-DOT March 1993 - July 1998
Skills
Wireless, Processors, ASIC, FPGA, Telecommunications, LTE, Wimax
Education
Indian Institute of Technology, Delhi 1995 — 1997
M.Tech, Integrated Electronics and Circuits
GITAM 1987 — 1991
B.E, Electronics and telecommmunications
S I C E S High School
Intel Corporation February 2013 - Present
Motorola Mobility ( Google) July 2005 - February 2013
Alcatel September 2004 - July 2005
Marconi 2000 - September 2004
Cadence design systems July 1998 - April 2000
C-DOT March 1993 - July 1998
Skills
Wireless, Processors, ASIC, FPGA, Telecommunications, LTE, Wimax
Education
Indian Institute of Technology, Delhi 1995 — 1997
M.Tech, Integrated Electronics and Circuits
GITAM 1987 — 1991
B.E, Electronics and telecommmunications
S I C E S High School
Malay Ganai Malay Ganai's Cadence Design Systems Experience November 1995 - August 1997
Job Sr. Product Director at Atrenta
Industry Computer Software
Experience
Atrenta March 2014 - Present
NEC Research Labs May 2006 - March 2014
NEC Reserch Labs May 2001 - May 2006
Cadence Design Systems November 1995 - August 1997
Larsen & Toubro Limited September 1992 - November 1995
Skills
Java, C++, SQL, Linux, C, Formal Verification, Model Checking, Constraint Solvers..., Dynamic Analysis, Modeling, Automated Error..., Python, Windows Multithreads, Algorithms, Computer Architecture, Computer Science, Data Structures, Distributed Systems, EDA, Embedded Systems, Programming, Software Design, Software Development, Testing, Software Engineering, ASIC
Education
The University of Texas at Austin 1997 — 2001
MS and Ph.D, Computer Engineering
IIT Kanpur 1988 — 1992
Bachelor of Technology (B.Tech.), Electrical Engineering
Atrenta March 2014 - Present
NEC Research Labs May 2006 - March 2014
NEC Reserch Labs May 2001 - May 2006
Cadence Design Systems November 1995 - August 1997
Larsen & Toubro Limited September 1992 - November 1995
Skills
Java, C++, SQL, Linux, C, Formal Verification, Model Checking, Constraint Solvers..., Dynamic Analysis, Modeling, Automated Error..., Python, Windows Multithreads, Algorithms, Computer Architecture, Computer Science, Data Structures, Distributed Systems, EDA, Embedded Systems, Programming, Software Design, Software Development, Testing, Software Engineering, ASIC
Education
The University of Texas at Austin 1997 — 2001
MS and Ph.D, Computer Engineering
IIT Kanpur 1988 — 1992
Bachelor of Technology (B.Tech.), Electrical Engineering
Nan Zhuang Nan Zhuang's Cadence Design Systems Experience October 2012 - Present
Job Architect/Software Engineering Director at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems October 2012 - Present
Tabula Inc. June 2007 - October 2012
Mentor Graphics September 2005 - June 2007
Synopsys Inc. June 1999 - September 2005
Actel June 1997 - June 1999
Skills
TCL, FPGA, ASIC, EDA, Verilog, Logic Synthesis, RTL design, Algorithms, SoC, Static Timing Analysis, Semiconductors, Microprocessors, VLSI, Timing Closure, Physical Design, SystemVerilog, R&D, IC, Functional Verification, Processors, Low-power Design
Education
Imperial College London 1993 — 1997
PhD, IC CAD, logic synthesis
Cadence Design Systems October 2012 - Present
Tabula Inc. June 2007 - October 2012
Mentor Graphics September 2005 - June 2007
Synopsys Inc. June 1999 - September 2005
Actel June 1997 - June 1999
Skills
TCL, FPGA, ASIC, EDA, Verilog, Logic Synthesis, RTL design, Algorithms, SoC, Static Timing Analysis, Semiconductors, Microprocessors, VLSI, Timing Closure, Physical Design, SystemVerilog, R&D, IC, Functional Verification, Processors, Low-power Design
Education
Imperial College London 1993 — 1997
PhD, IC CAD, logic synthesis
Pravil Gupta Pravil Gupta's Cadence Design Systems Experience 1995 - 1997
Job CTO at Quadeye Trading, LLC
Industry Computer Software
Experience
Quadeye Trading, LLC October 2010 - Present
SmartCloud Infotech Pvt Ltd February 2015 - Present
Trading Show West Coast 2015 March 2015 - March 2015
Trading Show West Coast 2014 February 2014 - February 2014
Amuura Corp August 2009 - October 2010
Selectica, Inc. December 1999 - June 2009
Nomadrive 2006 - 2008
Pratham Software 2000 - 2008
Get2Chip Inc. 1997 - 1999
Cadence Design Systems 1995 - 1997
Skills
Distributed Systems, Big Data, Enterprise Software, Scalability, Solution Architecture, Architecture, SaaS, Cloud Computing, Software Development, Software Project..., Pre-sales, Start-ups, Java Enterprise Edition, Technical Leadership, Web Services, Design Patterns, Enterprise Architecture, Java, Mobile Applications
Education
Univ. of Southern California 1989 — 1994
Ph.D., Computer Engineering
Univ. of Southern California 1988 — 1989
MS, Electrical Engineering
Indian Institute of Technology, Bombay 1984 — 1988
B.Tech., Electrical Engineering
Quadeye Trading, LLC October 2010 - Present
SmartCloud Infotech Pvt Ltd February 2015 - Present
Trading Show West Coast 2015 March 2015 - March 2015
Trading Show West Coast 2014 February 2014 - February 2014
Amuura Corp August 2009 - October 2010
Selectica, Inc. December 1999 - June 2009
Nomadrive 2006 - 2008
Pratham Software 2000 - 2008
Get2Chip Inc. 1997 - 1999
Cadence Design Systems 1995 - 1997
Skills
Distributed Systems, Big Data, Enterprise Software, Scalability, Solution Architecture, Architecture, SaaS, Cloud Computing, Software Development, Software Project..., Pre-sales, Start-ups, Java Enterprise Edition, Technical Leadership, Web Services, Design Patterns, Enterprise Architecture, Java, Mobile Applications
Education
Univ. of Southern California 1989 — 1994
Ph.D., Computer Engineering
Univ. of Southern California 1988 — 1989
MS, Electrical Engineering
Indian Institute of Technology, Bombay 1984 — 1988
B.Tech., Electrical Engineering
Pete Heller's Cadence Design Systems Experience 2010 - 2013
Job Senior Product Manager at Spirent Communications
Industry Computer Software
Experience
Spirent Communications May 2014 - Present
QuickDraw Technologies, Ltd. March 2011 - Present
Cadence Design Systems 2010 - 2013
Cadence Design Systems 2005 - 2009
Versity Design, Inc. 2001 - 2005
Marketing Consultant 2000 - 2001
Sonics, Inc. 1998 - 2000
Skills
EDA, ASIC, SoC, Semiconductors, IC, Functional Verification, Product Marketing, Processors, Product Management, Enterprise Software, Product Launch, Competitive Analysis, Go-to-market Strategy, Project Management, IP, Product Development, ARM, Business Development
Education
Indiana University - Kelley School of Business
MBA, Marketing
Indiana University Bloomington
BA, Computer Science
Spirent Communications May 2014 - Present
QuickDraw Technologies, Ltd. March 2011 - Present
Cadence Design Systems 2010 - 2013
Cadence Design Systems 2005 - 2009
Versity Design, Inc. 2001 - 2005
Marketing Consultant 2000 - 2001
Sonics, Inc. 1998 - 2000
Skills
EDA, ASIC, SoC, Semiconductors, IC, Functional Verification, Product Marketing, Processors, Product Management, Enterprise Software, Product Launch, Competitive Analysis, Go-to-market Strategy, Project Management, IP, Product Development, ARM, Business Development
Education
Indiana University - Kelley School of Business
MBA, Marketing
Indiana University Bloomington
BA, Computer Science
Ashwin Matta Ashwin Matta's Cadence Design Systems Experience 2011 - 2014
Job Product Strategy and Management at ARM
Industry Semiconductors
Experience
ARM November 2014 - Present
Cadence Design Systems 2011 - 2014
Denali Software (acquired by Cadence) 2008 - 2011
Denali Software (acquired by Cadence) 2005 - 2008
Denali (acquired by Cadence) 2002 - 2005
Cynergy System Design 1999 - 2001
Advanced Micro Devices 1994 - 1999
Skills
Product Management, Business Strategy, Product Strategy, Product Marketing, SoC, IP, EDA, Embedded Systems, PCIe, Functional Verification, SystemVerilog, ASIC, Simulations, Verilog, Architecture, Semiconductors, Tableau, IC, Architectures, Debugging, VLSI, Product Development, Technology Development, Design Methodology, Storage, Sales Presentations, DDR, Team Management, Emulation, Atlassian JIRA, Salesforce.com, Processors, Cross-functional Team..., ARM, Memory Controllers, Firmware
Education
Stanford Center for Professional Development 2014 — 2015
Professional Certification, Strategic Decision and Risk Management
Vanderbilt University 1992 — 1994
MS, Computer Engineering
Indian Institute of Technology, Bombay 1988 — 1992
B-Tech, Electrical Engineering
ARM November 2014 - Present
Cadence Design Systems 2011 - 2014
Denali Software (acquired by Cadence) 2008 - 2011
Denali Software (acquired by Cadence) 2005 - 2008
Denali (acquired by Cadence) 2002 - 2005
Cynergy System Design 1999 - 2001
Advanced Micro Devices 1994 - 1999
Skills
Product Management, Business Strategy, Product Strategy, Product Marketing, SoC, IP, EDA, Embedded Systems, PCIe, Functional Verification, SystemVerilog, ASIC, Simulations, Verilog, Architecture, Semiconductors, Tableau, IC, Architectures, Debugging, VLSI, Product Development, Technology Development, Design Methodology, Storage, Sales Presentations, DDR, Team Management, Emulation, Atlassian JIRA, Salesforce.com, Processors, Cross-functional Team..., ARM, Memory Controllers, Firmware
Education
Stanford Center for Professional Development 2014 — 2015
Professional Certification, Strategic Decision and Risk Management
Vanderbilt University 1992 — 1994
MS, Computer Engineering
Indian Institute of Technology, Bombay 1988 — 1992
B-Tech, Electrical Engineering
Roger Stevens Roger Stevens's Cadence Design Systems Experience August 1997 - October 2003
Job Layout Team Leader
Industry Semiconductors
Experience
Sandia National Laboratories June 2013 - Present
Cirtst Technology, Inc. October 2002 - June 2013
Freescale Semiconductor October 2003 - December 2012
Cadence Design Systems August 1997 - October 2003
Hinds Community College August 1999 - May 2001
AuE June 1995 - August 1997
US Army November 1986 - November 1989
Skills
LVS, CMOS, Mixed Signal, IC, Physical Design, Physical Verification, ASIC, Floorplanning, Analog, Cadence Virtuoso, Semiconductors, SoC, BiCMOS, VLSI, EDA, Power Management, PLL, Program Management, Virtuoso XL, People Skills, Cadence, RF, Processors, IC layout, SRAM, Team Management, Leadership, Methodology, Microelectronics
Education
University of Southern Mississippi 1992 — 1995
Bachelor of Applied Science (B.A.Sc.), EET minor in CET
Hinds Community College 1990 — 1992
Associate of Science (A.S.), EET
Sandia National Laboratories June 2013 - Present
Cirtst Technology, Inc. October 2002 - June 2013
Freescale Semiconductor October 2003 - December 2012
Cadence Design Systems August 1997 - October 2003
Hinds Community College August 1999 - May 2001
AuE June 1995 - August 1997
US Army November 1986 - November 1989
Skills
LVS, CMOS, Mixed Signal, IC, Physical Design, Physical Verification, ASIC, Floorplanning, Analog, Cadence Virtuoso, Semiconductors, SoC, BiCMOS, VLSI, EDA, Power Management, PLL, Program Management, Virtuoso XL, People Skills, Cadence, RF, Processors, IC layout, SRAM, Team Management, Leadership, Methodology, Microelectronics
Education
University of Southern Mississippi 1992 — 1995
Bachelor of Applied Science (B.A.Sc.), EET minor in CET
Hinds Community College 1990 — 1992
Associate of Science (A.S.), EET
Sanjay Baronia Sanjay Baronia's Cadence Design Systems Experience January 1990 - January 1992
Job Entrepreneur, Strategist, Product Management
Industry Computer Hardware
Experience
Trilio Data September 2013 - Present
EMC January 2012 - August 2013
EMC February 2008 - July 2012
EMC April 2005 - February 2008
EMC Corp January 2003 - April 2005
EMC Corp January 1999 - January 2003
Cambio Networks January 1995 - January 1997
Mentor Graphics, Inc January 1993 - January 1995
Cadence Design Systems January 1990 - January 1992
Tektronix January 1989 - January 1990
Skills
Storage, Cloud Computing, Product Management, Virtualization, Go-to-market Strategy, Enterprise Software, NAS, SaaS, Storage Virtualization, Business Alliances, Storage Area Networks, Pre-sales, Data Center, Software Engineering, Strategic Partnerships, Integration, Competitive Analysis, Enterprise Storage, VMware, Strategy, EMC Storage, Cross-functional Team..., NetApp, SAN, High Availability, Partner Management, Big Data, Business Development
Education
University of Michigan 1997 — 1999
MBA, General Management
Oregon State University
MS, Computer Science
Indian Institute of Technology, Kharagpur 1982 — 1986
BTech, Electrical Engineering
St Thomas High School
St Thomas High School
Trilio Data September 2013 - Present
EMC January 2012 - August 2013
EMC February 2008 - July 2012
EMC April 2005 - February 2008
EMC Corp January 2003 - April 2005
EMC Corp January 1999 - January 2003
Cambio Networks January 1995 - January 1997
Mentor Graphics, Inc January 1993 - January 1995
Cadence Design Systems January 1990 - January 1992
Tektronix January 1989 - January 1990
Skills
Storage, Cloud Computing, Product Management, Virtualization, Go-to-market Strategy, Enterprise Software, NAS, SaaS, Storage Virtualization, Business Alliances, Storage Area Networks, Pre-sales, Data Center, Software Engineering, Strategic Partnerships, Integration, Competitive Analysis, Enterprise Storage, VMware, Strategy, EMC Storage, Cross-functional Team..., NetApp, SAN, High Availability, Partner Management, Big Data, Business Development
Education
University of Michigan 1997 — 1999
MBA, General Management
Oregon State University
MS, Computer Science
Indian Institute of Technology, Kharagpur 1982 — 1986
BTech, Electrical Engineering
St Thomas High School
St Thomas High School
Ramoji Rao Ramoji Rao's Cadence Design Systems Experience July 1998 - May 2012
Job Sr. Staff R&D Engr at Synopsys Inc
Industry Computer Software
Experience
Synopsys Inc August 2015 - Present
Mentor Graphics June 2012 - August 2015
Cadence Design Systems July 1998 - May 2012
LSI, an Avago Technologies Company April 1995 - July 1998
Skills
EDA, Physical Synthesis, Low Power Optimization, C, C++, MSV, MultiThreading, EDA algorithms, Place&Route, Data Structures, Graph Theory, Place & Route, IC, ASIC, SoC, Verilog, Debugging, TCL, Algorithms, Multithreading, VLSI
Education
Indian Institute of Technology, Kharagpur
Master’s Degree, Integrated Circuits & Systems
National Institute of Technology Warangal
Bachelor of Technology (B.Tech.), Electronics & Communication Engg
Synopsys Inc August 2015 - Present
Mentor Graphics June 2012 - August 2015
Cadence Design Systems July 1998 - May 2012
LSI, an Avago Technologies Company April 1995 - July 1998
Skills
EDA, Physical Synthesis, Low Power Optimization, C, C++, MSV, MultiThreading, EDA algorithms, Place&Route, Data Structures, Graph Theory, Place & Route, IC, ASIC, SoC, Verilog, Debugging, TCL, Algorithms, Multithreading, VLSI
Education
Indian Institute of Technology, Kharagpur
Master’s Degree, Integrated Circuits & Systems
National Institute of Technology Warangal
Bachelor of Technology (B.Tech.), Electronics & Communication Engg
Narahari Nadiminti's Cadence Design Systems Experience July 2010 - March 2013
Job Design Verification Engineer at Apple
Industry Semiconductors
Experience
Apple July 2014 - Present
SmartPlay Technologies April 2013 - July 2014
Cadence Design Systems July 2010 - March 2013
Xilinx India Technology Services November 2007 - July 2010
CMC Ltd August 2005 - October 2007
Skills
Functional Verification, Open Verification..., Universal Verification..., System Verilog, SystemVerilog, Verilog, UART, UVM, AXI, Xilinx, Cadence, Ethernet, FPGA, ASIC, VLSI, Static Timing Analysis, EDA, SoC, VHDL, NCSim, ModelSim, Debugging, Integrated Circuit...
Education
Indian Institute of Technology, Bombay 2003 — 2005
Master of Technology (M.Tech.), Electronic Systems
Gayatri Vidya Parishad college of Engineering 1998 — 2002
Bachelor of Technology (BTech), Electrical and Electronics
Gayatri Jr College
Apple July 2014 - Present
SmartPlay Technologies April 2013 - July 2014
Cadence Design Systems July 2010 - March 2013
Xilinx India Technology Services November 2007 - July 2010
CMC Ltd August 2005 - October 2007
Skills
Functional Verification, Open Verification..., Universal Verification..., System Verilog, SystemVerilog, Verilog, UART, UVM, AXI, Xilinx, Cadence, Ethernet, FPGA, ASIC, VLSI, Static Timing Analysis, EDA, SoC, VHDL, NCSim, ModelSim, Debugging, Integrated Circuit...
Education
Indian Institute of Technology, Bombay 2003 — 2005
Master of Technology (M.Tech.), Electronic Systems
Gayatri Vidya Parishad college of Engineering 1998 — 2002
Bachelor of Technology (BTech), Electrical and Electronics
Gayatri Jr College
Johannes Grad Johannes Grad's Cadence Design Systems Experience February 2006 - Present
Job Product Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems February 2006 - Present
Cadence Design Systems September 2003 - February 2006
Illinois Institute of Technology August 2001 - August 2003
Epson May 2001 - August 2001
Skills
EDA, TCL, ASIC, VLSI, Physical Design, OpenAccess, Open Access, Cadence, Debugging, Verilog, SoC, Cadence Virtuoso, IC, Physical Verification, Analog Circuit Design, Firmware, Product Engineering, Semiconductors, Static Timing Analysis, Mixed Signal, Software Engineering, Integrated Circuit..., C, Analog, Corporate Finance, Operations Management, Simulations, Hardware Architecture, FPGA
Education
Illinois Institute of Technology 2003 — 2006
PhD
Illinois Institute of Technology 2001 — 2002
MS
Cadence Design Systems February 2006 - Present
Cadence Design Systems September 2003 - February 2006
Illinois Institute of Technology August 2001 - August 2003
Epson May 2001 - August 2001
Skills
EDA, TCL, ASIC, VLSI, Physical Design, OpenAccess, Open Access, Cadence, Debugging, Verilog, SoC, Cadence Virtuoso, IC, Physical Verification, Analog Circuit Design, Firmware, Product Engineering, Semiconductors, Static Timing Analysis, Mixed Signal, Software Engineering, Integrated Circuit..., C, Analog, Corporate Finance, Operations Management, Simulations, Hardware Architecture, FPGA
Education
Illinois Institute of Technology 2003 — 2006
PhD
Illinois Institute of Technology 2001 — 2002
MS
Sanchayan Sinha's Cadence Design Systems Experience May 2006 - November 2007
Job Director Product Management at AppliedMicro
Industry Semiconductors
Experience
AppliedMicro November 2014 - April 2015
AppliedMicro January 2012 - October 2014
Applied Micro October 2009 - January 2012
Cypress Semiconductor November 2007 - October 2009
Cadence Design Systems May 2006 - November 2007
Texas Instruments February 2002 - April 2006
Transwitch 2001 - 2002
Selco India 1998 - 1998
Skills
Marketing Strategy, Product Marketing, Mergers, Business Strategy, Wireless, Telecommunications, Go-to-market Strategy, Revenue Recognition, Account Management, Japanese market, PowerPC, VLSI, Semiconductors, ARM, Product Management, Business Analysis, New Business Development, Market Analysis, LOI, Due Diligence, Valuation, Portfolio Management, Business Development, ASIC, SoC, Market Research, EDA, Business Planning, Channel Partners, Competitive Analysis, Leadership, Digital Signal..., Power Management, IC, Processors, Embedded Systems, Consumer Electronics, Strategy, Enterprise Software, Entrepreneurship, Management, Product Lifecycle..., Cross-functional Team..., Strategic Partnerships, Start-ups, Mobile Devices, Product Launch, Venture Capital, Semiconductor Industry, Technical Marketing
Education
Indian Institute of Technology, Kharagpur 1997 — 2001
BTech
Delhi Public School - B.S City 1995 — 1997
AISSCE
AppliedMicro November 2014 - April 2015
AppliedMicro January 2012 - October 2014
Applied Micro October 2009 - January 2012
Cypress Semiconductor November 2007 - October 2009
Cadence Design Systems May 2006 - November 2007
Texas Instruments February 2002 - April 2006
Transwitch 2001 - 2002
Selco India 1998 - 1998
Skills
Marketing Strategy, Product Marketing, Mergers, Business Strategy, Wireless, Telecommunications, Go-to-market Strategy, Revenue Recognition, Account Management, Japanese market, PowerPC, VLSI, Semiconductors, ARM, Product Management, Business Analysis, New Business Development, Market Analysis, LOI, Due Diligence, Valuation, Portfolio Management, Business Development, ASIC, SoC, Market Research, EDA, Business Planning, Channel Partners, Competitive Analysis, Leadership, Digital Signal..., Power Management, IC, Processors, Embedded Systems, Consumer Electronics, Strategy, Enterprise Software, Entrepreneurship, Management, Product Lifecycle..., Cross-functional Team..., Strategic Partnerships, Start-ups, Mobile Devices, Product Launch, Venture Capital, Semiconductor Industry, Technical Marketing
Education
Indian Institute of Technology, Kharagpur 1997 — 2001
BTech
Delhi Public School - B.S City 1995 — 1997
AISSCE
Kishore Kathula Kishore Kathula's Cadence Design Systems Experience February 1998 - June 2002
Job PDK / Design Automation at MaxLinear
Industry Semiconductors
Experience
MaxLinear January 2011 - Present
Skyworks Solutions Inc June 2002 - January 2011
Cadence Design Systems February 1998 - June 2002
Skills
Spectre, EDA, Mixed Signal, Cadence Virtuoso, IC, PDK Development, CMOS, ASIC, Analog, SoC, Physical Design, DRC, VLSI, Analog Circuit Design, Integrated Circuit..., Circuit Design, LVS
Education
Indian Institute of Technology, Kharagpur 1996 — 1998
Masters, VLSI Design
MaxLinear January 2011 - Present
Skyworks Solutions Inc June 2002 - January 2011
Cadence Design Systems February 1998 - June 2002
Skills
Spectre, EDA, Mixed Signal, Cadence Virtuoso, IC, PDK Development, CMOS, ASIC, Analog, SoC, Physical Design, DRC, VLSI, Analog Circuit Design, Integrated Circuit..., Circuit Design, LVS
Education
Indian Institute of Technology, Kharagpur 1996 — 1998
Masters, VLSI Design
Shreyash Shukla Shreyash Shukla's Cadence Design Systems Experience July 2015 - Present
Job Sr Principal Product Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2015 - Present
Cadence Design Systems July 2013 - July 2015
Cadence Design Systems September 2011 - July 2013
Xilinx November 2010 - August 2011
Cadence Design Systems March 2008 - November 2010
Cadence Design Systems July 2005 - March 2008
Skills
Logic Synthesis, Static Timing Analysis, Power Analysis, ASIC, Formal Verification, RTL coding, Floorplanning, FPGA, Cadence, RTL Design, VLSI, Debugging, EDA, Verilog, DFT, SoC, TCL
Education
Indian Institute of Technology, Bombay 2000 — 2005
Dual Degree, Electrical/Microelectronics
MAV 1997 — 2000
Cadence Design Systems July 2015 - Present
Cadence Design Systems July 2013 - July 2015
Cadence Design Systems September 2011 - July 2013
Xilinx November 2010 - August 2011
Cadence Design Systems March 2008 - November 2010
Cadence Design Systems July 2005 - March 2008
Skills
Logic Synthesis, Static Timing Analysis, Power Analysis, ASIC, Formal Verification, RTL coding, Floorplanning, FPGA, Cadence, RTL Design, VLSI, Debugging, EDA, Verilog, DFT, SoC, TCL
Education
Indian Institute of Technology, Bombay 2000 — 2005
Dual Degree, Electrical/Microelectronics
MAV 1997 — 2000
Abhay Agarwal Abhay Agarwal's Cadence Design Systems Experience December 1990 - Present
Job Engineering Director at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems December 1990 - Present
WTI Advanced Technology Ltd March 1990 - December 1990
Sunray Computers Pvt Ltd July 1988 - March 1990
Education
Indian Institute of Technology, Kanpur 1984 — 1988
B.Tech, Electrical and Electronics
Kendriya Vidyalaya No 2 BHEL Haridwar 1978 — 1984
Cadence Design Systems December 1990 - Present
WTI Advanced Technology Ltd March 1990 - December 1990
Sunray Computers Pvt Ltd July 1988 - March 1990
Education
Indian Institute of Technology, Kanpur 1984 — 1988
B.Tech, Electrical and Electronics
Kendriya Vidyalaya No 2 BHEL Haridwar 1978 — 1984
Kaushik De Kaushik De's Cadence Design Systems Experience September 1997 - December 2000
Job Synopsys Scientist at Synopsys
Industry Semiconductors
Experience
Synopsys 2013 - Present
Synopsys India April 2005 - 2013
Zenasis Technologies Inc January 2003 - April 2005
Optim Networks December 2000 - February 2002
Cadence Design Systems September 1997 - December 2000
LSI Logic Corporation September 1993 - September 1997
Skills
EDA, Algorithms, Architecture, ASIC, Software Development, VLSI, Functional Verification, UPF, Engineering Management, Scalable Architecture, Software Platform, Low Power, Software Architectural..., Low-power Design, SoC, Logic Synthesis, Distributed Systems, Formal Verification, C++, TCL, Verilog, Debugging, Embedded Systems, Perl, FPGA, High Performance..., IC
Education
University of Illinois at Urbana-Champaign 1989 — 1993
PhD, Computer Science
Indian Institute of Technology, Kharagpur
B. Tech, Electronics Engg
Synopsys 2013 - Present
Synopsys India April 2005 - 2013
Zenasis Technologies Inc January 2003 - April 2005
Optim Networks December 2000 - February 2002
Cadence Design Systems September 1997 - December 2000
LSI Logic Corporation September 1993 - September 1997
Skills
EDA, Algorithms, Architecture, ASIC, Software Development, VLSI, Functional Verification, UPF, Engineering Management, Scalable Architecture, Software Platform, Low Power, Software Architectural..., Low-power Design, SoC, Logic Synthesis, Distributed Systems, Formal Verification, C++, TCL, Verilog, Debugging, Embedded Systems, Perl, FPGA, High Performance..., IC
Education
University of Illinois at Urbana-Champaign 1989 — 1993
PhD, Computer Science
Indian Institute of Technology, Kharagpur
B. Tech, Electronics Engg
Chittaranjan Mallipeddi Chittaranjan Mallipeddi's Cadence Design Systems Experience 1996 - 1998
Job Investor and Advisor at Several
Industry Information Technology and Services
Experience
Several Chief Strategy OfficerClinical Business Solutions, HCIT, GE HealthcareFebruary 2011 - March 2012
GE Healthcare March 2010 - March 2011
MedPlexus (Acquired by GE Healthcare) 2000 - April 2010
Cadence Design Systems 1996 - 1998
Cadence Design Systems 1995 - 1996
Cadence Design Systems 1994 - 1995
ViewLogic/Sunrise 1992 - 1994
Amdahl Corporation 1984 - 1992
Skills
Consulting, Strategy, SaaS, Strategic Planning, Software Development, Management, Agile Methodologies, Business Strategy, Healthcare Information..., SOA, Enterprise Architecture, Product Management, Business Intelligence
Education
Indian Institute of Technology, Delhi 1977 — 1978
Computer Science
Indian Institute of Technology, Kharagpur 1975 — 1977
M.S., Mathematics and Computer Science
Several Chief Strategy OfficerClinical Business Solutions, HCIT, GE HealthcareFebruary 2011 - March 2012
GE Healthcare March 2010 - March 2011
MedPlexus (Acquired by GE Healthcare) 2000 - April 2010
Cadence Design Systems 1996 - 1998
Cadence Design Systems 1995 - 1996
Cadence Design Systems 1994 - 1995
ViewLogic/Sunrise 1992 - 1994
Amdahl Corporation 1984 - 1992
Skills
Consulting, Strategy, SaaS, Strategic Planning, Software Development, Management, Agile Methodologies, Business Strategy, Healthcare Information..., SOA, Enterprise Architecture, Product Management, Business Intelligence
Education
Indian Institute of Technology, Delhi 1977 — 1978
Computer Science
Indian Institute of Technology, Kharagpur 1975 — 1977
M.S., Mathematics and Computer Science
Etienne JACQUES Etienne JACQUES's Cadence Design Systems Experience July 2002 - June 2005
Job Technologist
Industry Computer Software
Experience
Google March 2014 - Present
D2S Inc. April 2010 - March 2014
Avisto July 2007 - March 2010
Valdexia 2005 - 2007
Cadence Design Systems July 2002 - June 2005
Simplex Solutions April 2000 - June 2002
Snaketech July 1999 - March 2000
Courbon 1995 - 1998
JDM-ARGOS 1994 - 1995
Skills
C++, Windows, Software Engineering, Software Development, Distributed Systems, Data Structures, Algorithms, Computational Geometry, Parallel Computing, Unix, Linux, Embedded Linux, Windows NT, C, Java, PHP, x86 Assembly, EDA, Python, ASIC, CVS, Problem Solving, HTML, XML, SOAP, Ajax, SQL, HTTP, Java EE, Mathematics, Computer Graphics, Physical Design
Education
Université Joseph Fourier (Grenoble I) 1998 — 1999
MS, Computer Science, Coursework only - No degree
1990 — 1993
Engineer, Physics
Google March 2014 - Present
D2S Inc. April 2010 - March 2014
Avisto July 2007 - March 2010
Valdexia 2005 - 2007
Cadence Design Systems July 2002 - June 2005
Simplex Solutions April 2000 - June 2002
Snaketech July 1999 - March 2000
Courbon 1995 - 1998
JDM-ARGOS 1994 - 1995
Skills
C++, Windows, Software Engineering, Software Development, Distributed Systems, Data Structures, Algorithms, Computational Geometry, Parallel Computing, Unix, Linux, Embedded Linux, Windows NT, C, Java, PHP, x86 Assembly, EDA, Python, ASIC, CVS, Problem Solving, HTML, XML, SOAP, Ajax, SQL, HTTP, Java EE, Mathematics, Computer Graphics, Physical Design
Education
Université Joseph Fourier (Grenoble I) 1998 — 1999
MS, Computer Science, Coursework only - No degree
1990 — 1993
Engineer, Physics
Vahe Manugian Vahe Manugian's Cadence Design Systems Experience 2000 - 2001
Job Mgr Dev Eng
Industry Medical Devices
Experience
Covidien August 2011 - Present
Covidien June 2009 - August 2011
Siemens Medical Solutions 2002 - 2008
Cadence Design Systems 2000 - 2001
Quantum Micro Systems 1994 - 2000
AMRAY 1985 - 1993
KLA-Tencor 1982 - 1985
Advanced Micro Devices 1979 - 1982
Education
Heriot-Watt University 1972 — 1975
Ph.D., Electronics
University of Birmingham 1968 — 1971
B.SC., Electronics
Heriot-Watt University
M.Sc., Electronics
Covidien August 2011 - Present
Covidien June 2009 - August 2011
Siemens Medical Solutions 2002 - 2008
Cadence Design Systems 2000 - 2001
Quantum Micro Systems 1994 - 2000
AMRAY 1985 - 1993
KLA-Tencor 1982 - 1985
Advanced Micro Devices 1979 - 1982
Education
Heriot-Watt University 1972 — 1975
Ph.D., Electronics
University of Birmingham 1968 — 1971
B.SC., Electronics
Heriot-Watt University
M.Sc., Electronics
Amit Ganatra Amit Ganatra's Cadence Design Systems Experience July 1994 - June 1995
Job Data Engineer at Moat
Industry Information Services
Experience
Moat June 2014 - Present
Susquehanna International Group, LLP (SIG) February 2008 - May 2014
Goldman Sachs February 2007 - February 2008
VIDA Diagnostics February 2006 - February 2007
University Of Iowa May 2003 - August 2003
Mashreq Bank July 1997 - June 1999
Cadence Design Systems July 1994 - June 1995
Skills
Electronic Trading, Statistical Arbitrage, C++, Boost C++, Python, NumPy, SciPy, R, Regression Models, Logistic Regression, Linear Models, Trading Strategies, Trading Systems, Linux
Education
University Of Iowa 1999 — 2005
Doctor of Philosophy (Ph.D.), Mathematics
Indian Institute of Management, Lucknow 1995 — 1997
Master of Business Administration (MBA), Finance
Jadavpur University 1990 — 1994
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
Moat June 2014 - Present
Susquehanna International Group, LLP (SIG) February 2008 - May 2014
Goldman Sachs February 2007 - February 2008
VIDA Diagnostics February 2006 - February 2007
University Of Iowa May 2003 - August 2003
Mashreq Bank July 1997 - June 1999
Cadence Design Systems July 1994 - June 1995
Skills
Electronic Trading, Statistical Arbitrage, C++, Boost C++, Python, NumPy, SciPy, R, Regression Models, Logistic Regression, Linear Models, Trading Strategies, Trading Systems, Linux
Education
University Of Iowa 1999 — 2005
Doctor of Philosophy (Ph.D.), Mathematics
Indian Institute of Management, Lucknow 1995 — 1997
Master of Business Administration (MBA), Finance
Jadavpur University 1990 — 1994
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
Lian Huai Lian Huai's Cadence Design Systems Experience September 2013 - January 2014
Job Senior Engineer at Silicon Image
Industry Computer Hardware
Experience
Silicon Image January 2015 - Present
Cadence Design Systems September 2013 - January 2014
University of Minnesota 2011 - 2014
University of Minnesota 2009 - 2014
LSI Corporation May 2013 - August 2013
Asian Microelectronics CO., LTD. June 2007 - May 2009
Skills
Verilog, ASIC, FPGA, Matlab, VLSI, VHDL, ModelSim, Cadence Virtuoso, SystemVerilog, RTL design, C++, SPICE, Xilinx, Static Timing Analysis, Signal Processing, Pspice, Synopsys tools, Circuit Design, Computer Architecture, Cadence, EDA, Xilinx ISE, MIMO, TCL, Primetime, Synopsis Design Compiler, Digital Signal..., Wireless Communications
Education
University of Minnesota-Twin Cities 2009 — 2014
Ph.D, Electrical & Computer Engineering
Huazhong University of Science and Technology
Silicon Image January 2015 - Present
Cadence Design Systems September 2013 - January 2014
University of Minnesota 2011 - 2014
University of Minnesota 2009 - 2014
LSI Corporation May 2013 - August 2013
Asian Microelectronics CO., LTD. June 2007 - May 2009
Skills
Verilog, ASIC, FPGA, Matlab, VLSI, VHDL, ModelSim, Cadence Virtuoso, SystemVerilog, RTL design, C++, SPICE, Xilinx, Static Timing Analysis, Signal Processing, Pspice, Synopsys tools, Circuit Design, Computer Architecture, Cadence, EDA, Xilinx ISE, MIMO, TCL, Primetime, Synopsis Design Compiler, Digital Signal..., Wireless Communications
Education
University of Minnesota-Twin Cities 2009 — 2014
Ph.D, Electrical & Computer Engineering
Huazhong University of Science and Technology
Rakesh Dhoopar Rakesh Dhoopar's Cadence Design Systems Experience March 1989 - May 1994
Job VP, Product Management | Inspire Innovative Cloud Application Diagnostics through Machine Learning & Big Data Analytics
Industry Computer Software
Experience
DiagKnowLogy May 2013 - Present
BMC Software July 2010 - May 2013
Oracle January 2006 - July 2010
Oracle 2004 - 2006
Oracle 1997 - 2003
Oracle 1994 - 1997
Cadence Design Systems March 1989 - May 1994
Skills
Cloud Computing, Product Management, Go-to-market Strategy, Strategy, Enterprise Software, Machine Learning, Big Data, Analytics, Integration, Virtualization, Product Marketing, Middleware, SOA, Start-ups, Databases, SaaS, Business Development, Management, Systems Management, Oracle, Product Lifecycle...
Education
Santa Clara University 1994 — 1997
MBA
Louisiana State University 1986 — 1988
MS, Computer Science
IIT Kanpur 1980 — 1985
B. Tech, Engineering
DiagKnowLogy May 2013 - Present
BMC Software July 2010 - May 2013
Oracle January 2006 - July 2010
Oracle 2004 - 2006
Oracle 1997 - 2003
Oracle 1994 - 1997
Cadence Design Systems March 1989 - May 1994
Skills
Cloud Computing, Product Management, Go-to-market Strategy, Strategy, Enterprise Software, Machine Learning, Big Data, Analytics, Integration, Virtualization, Product Marketing, Middleware, SOA, Start-ups, Databases, SaaS, Business Development, Management, Systems Management, Oracle, Product Lifecycle...
Education
Santa Clara University 1994 — 1997
MBA
Louisiana State University 1986 — 1988
MS, Computer Science
IIT Kanpur 1980 — 1985
B. Tech, Engineering
Milind Weling Milind Weling's Cadence Design Systems Experience April 2007 - September 2011
Job Vice President, Semiconductor/Memory Programs at Intermolecular
Industry Semiconductors
Experience
Intermolecular November 2014 - Present
Intermolecular September 2011 - October 2014
Cadence Design Systems April 2007 - September 2011
Sun Microsystems 2003 - 2007
Philips Semiconductors 1999 - 2002
VLSI Technology, Inc. 1990 - 1999
Skills
Semiconductors, ASIC, IC, EDA
Education
University of Hawaii at Manoa 1988 — 1990
MS
Indian Institute of Technology, Bombay 1984 — 1988
B. Tech
Jai Hind College 1982 — 1984
St. Xavier's Boys' Academy 1976 — 1982
Intermolecular November 2014 - Present
Intermolecular September 2011 - October 2014
Cadence Design Systems April 2007 - September 2011
Sun Microsystems 2003 - 2007
Philips Semiconductors 1999 - 2002
VLSI Technology, Inc. 1990 - 1999
Skills
Semiconductors, ASIC, IC, EDA
Education
University of Hawaii at Manoa 1988 — 1990
MS
Indian Institute of Technology, Bombay 1984 — 1988
B. Tech
Jai Hind College 1982 — 1984
St. Xavier's Boys' Academy 1976 — 1982
Subhash Yallamilli Subhash Yallamilli's Cadence Design Systems Experience 1998 - 1999
Job Senior Software Architect, System Enginner, Power Management Expert
Industry Computer Software
Experience
Sony Mobile Communications Inc October 2013 - Present
Sasken Communication Technologies Ltd. October 2011 - Present
Sasken Communication Technologies Ltd. October 2006 - September 2011
Sasken Communication Technologies Ltd November 2000 - September 2006
Sasken Communication Technologies Ltd August 1999 - October 2000
Cadence Design Systems 1998 - 1999
Skills
Linux, Embedded Systems, Device Drivers, RTOS, Operating Systems, Android, Embedded Software, Cloud Computing, Mobile Devices, Debugging, Embedded Linux, ClearCase, Distributed Systems, Mobile Applications, Software Development, Wireless, Open Source, Perl, C, Algorithms, Linux Kernel, Software Design, System Architecture, Software Engineering, ARM, C++, Java, Power Management, SoC, Git, Perforce, Assembly Language, Python, BSP, Performance Tuning
Education
Indian Institute of Technology, Kanpur 1997 — 1999
M.Tech, Computer Science & Engineering
Nagarjuna University 1993 — 1997
B.Tech, Computer Science & Engineering
Sony Mobile Communications Inc October 2013 - Present
Sasken Communication Technologies Ltd. October 2011 - Present
Sasken Communication Technologies Ltd. October 2006 - September 2011
Sasken Communication Technologies Ltd November 2000 - September 2006
Sasken Communication Technologies Ltd August 1999 - October 2000
Cadence Design Systems 1998 - 1999
Skills
Linux, Embedded Systems, Device Drivers, RTOS, Operating Systems, Android, Embedded Software, Cloud Computing, Mobile Devices, Debugging, Embedded Linux, ClearCase, Distributed Systems, Mobile Applications, Software Development, Wireless, Open Source, Perl, C, Algorithms, Linux Kernel, Software Design, System Architecture, Software Engineering, ARM, C++, Java, Power Management, SoC, Git, Perforce, Assembly Language, Python, BSP, Performance Tuning
Education
Indian Institute of Technology, Kanpur 1997 — 1999
M.Tech, Computer Science & Engineering
Nagarjuna University 1993 — 1997
B.Tech, Computer Science & Engineering
Craig Quantz's Cadence Design Systems Experience 1994 - 2003
Job Managing Director at DaggerFoil Group
Industry Computer Software
Experience
DaggerFoil Group 2013 - Present
CONNECT 2010 - Present
Faros Group 2003 - 2013
Cadence Design Systems 1994 - 2003
Accenture 1990 - 1994
Skills
Product Management, Start-ups, Strategic Planning, Management, Entrepreneurship, International Operations, Product Marketing, Corporate Development, Partnerships, Software Product..., Venture Capital, Professional Services, Business, Software Product..., Professional Service..., Emerging Markets, Business Development, Strategic Partnerships, Business Strategy
Education
Indiana University - Kelley School of Business
BS
DaggerFoil Group 2013 - Present
CONNECT 2010 - Present
Faros Group 2003 - 2013
Cadence Design Systems 1994 - 2003
Accenture 1990 - 1994
Skills
Product Management, Start-ups, Strategic Planning, Management, Entrepreneurship, International Operations, Product Marketing, Corporate Development, Partnerships, Software Product..., Venture Capital, Professional Services, Business, Software Product..., Professional Service..., Emerging Markets, Business Development, Strategic Partnerships, Business Strategy
Education
Indiana University - Kelley School of Business
BS
Gopal Raghavan Gopal Raghavan's Cadence Design Systems Experience October 2012 - June 2014
Job
Industry Semiconductors
Experience
Private June 2014 - Present
Cadence Design Systems October 2012 - June 2014
Private February 2011 - December 2012
Inphi Corporation (NYSE: IPHI) January 2001 - February 2011
Conexant June 2000 - November 2000
Hughes Electronics September 1994 - May 2000
Intel July 1984 - July 1994
Skills
Semiconductors, ASIC, IC, Analog, Mixed Signal, SoC, Start-ups, Early-stage Startups, CMOS, Hardware Architecture, Semiconductor Industry, FPGA, Debugging, Firmware, Circuit Design, VLSI, Digital Signal..., Embedded Systems, Processors, Electronics, Integrated Circuit..., Microprocessors, Signal Integrity, PCIe, System Architecture, Computer Architecture, Analog Circuit Design, EDA, Simulations, RTL design, Functional Verification, TCL, Low-power Design, PCB design, PCB Design
Education
Stanford University 1987 — 1993
Ph. D., Electrical Engineering
Stanford University 1982 — 1984
M. S., Electrical Engineering
Indian Institute of Technology, Kanpur 1977 — 1982
B. Tech., Electrical Engineering
St. Xaviers
Private June 2014 - Present
Cadence Design Systems October 2012 - June 2014
Private February 2011 - December 2012
Inphi Corporation (NYSE: IPHI) January 2001 - February 2011
Conexant June 2000 - November 2000
Hughes Electronics September 1994 - May 2000
Intel July 1984 - July 1994
Skills
Semiconductors, ASIC, IC, Analog, Mixed Signal, SoC, Start-ups, Early-stage Startups, CMOS, Hardware Architecture, Semiconductor Industry, FPGA, Debugging, Firmware, Circuit Design, VLSI, Digital Signal..., Embedded Systems, Processors, Electronics, Integrated Circuit..., Microprocessors, Signal Integrity, PCIe, System Architecture, Computer Architecture, Analog Circuit Design, EDA, Simulations, RTL design, Functional Verification, TCL, Low-power Design, PCB design, PCB Design
Education
Stanford University 1987 — 1993
Ph. D., Electrical Engineering
Stanford University 1982 — 1984
M. S., Electrical Engineering
Indian Institute of Technology, Kanpur 1977 — 1982
B. Tech., Electrical Engineering
St. Xaviers
Ashwani Gupta's Cadence Design Systems Experience July 2014 - Present
Job Senior Principal Engineer/Project Leader at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2014 - Present
Samsung Semiconductor May 2011 - July 2014
NXP June 2010 - May 2011
Juniper Networks July 2009 - June 2010
NXP Semiconductors April 2001 - July 2009
Philips Semiconductors 2001 - 2006
STMicroelectronics 1996 - 2000
Central R&D, ST Microelectronics 1996 - 2000
Skills
Physical Design, Static Timing Analysis, ASIC, SoC, Physical Verification, Floorplanning, Signal Integrity, Place & Route, Timing, Circuit Design, Verilog, EDA, IC, Semiconductors, Low-power Design, RTL design, Clock Tree Synthesis, Timing Closure, TCL, Primetime, DFT
Education
Indian Institute of Technology, Roorkee 1992 — 1996
Bachelor of Engineering, Electrical, Electronics and Communications Engineering
Cadence Design Systems July 2014 - Present
Samsung Semiconductor May 2011 - July 2014
NXP June 2010 - May 2011
Juniper Networks July 2009 - June 2010
NXP Semiconductors April 2001 - July 2009
Philips Semiconductors 2001 - 2006
STMicroelectronics 1996 - 2000
Central R&D, ST Microelectronics 1996 - 2000
Skills
Physical Design, Static Timing Analysis, ASIC, SoC, Physical Verification, Floorplanning, Signal Integrity, Place & Route, Timing, Circuit Design, Verilog, EDA, IC, Semiconductors, Low-power Design, RTL design, Clock Tree Synthesis, Timing Closure, TCL, Primetime, DFT
Education
Indian Institute of Technology, Roorkee 1992 — 1996
Bachelor of Engineering, Electrical, Electronics and Communications Engineering
Sanyogita Gupta Sanyogita Gupta's Cadence Design Systems Experience 1990 - 1993
Job Technology Service Delivery/Solution Architect/ System Integration
Industry Information Technology and Services
Experience
Western Union July 2008 - Present
State Street October 2007 - June 2008
Teliris Inc February 2005 - September 2007
Telcordia January 1999 - August 2003
AT &T, Lucent Technologies, Deutsche Bank and Cadence Design Systems 1990 - 1998
Cadence Design Systems 1990 - 1993
Skills
SDLC, Vendor Management, Agile Methodologies, Unix, Requirements Analysis, Software Project..., Integration, Software Development, Business Analysis, Program Management, PMP, IT Strategy, Enterprise Architecture, Cloud Computing, Data Center, Telecommunications, Project Management, SOA, Visio, SQL, Quality Assurance, Product Management, Cross-functional Team...
Education
Indian Institute of Technology, Delhi 1988 — 1990
M.Tech, Computer Technology
Indian Institute of Technology, Roorkee 1983 — 1987
B.E, Electronics and Communications
Western Union July 2008 - Present
State Street October 2007 - June 2008
Teliris Inc February 2005 - September 2007
Telcordia January 1999 - August 2003
AT &T, Lucent Technologies, Deutsche Bank and Cadence Design Systems 1990 - 1998
Cadence Design Systems 1990 - 1993
Skills
SDLC, Vendor Management, Agile Methodologies, Unix, Requirements Analysis, Software Project..., Integration, Software Development, Business Analysis, Program Management, PMP, IT Strategy, Enterprise Architecture, Cloud Computing, Data Center, Telecommunications, Project Management, SOA, Visio, SQL, Quality Assurance, Product Management, Cross-functional Team...
Education
Indian Institute of Technology, Delhi 1988 — 1990
M.Tech, Computer Technology
Indian Institute of Technology, Roorkee 1983 — 1987
B.E, Electronics and Communications
Dennis Parker Dennis Parker's Cadence Design Systems Experience September 2012 - December 2012
Job Senior Technical Writer at Google via Artech staffing
Industry Computer Software
Experience
NetApp (Artizen) January 2014 - April 2014
Google via Artech August 2013 - October 2013
NVIDIA (West Valley Staffing) January 2013 - June 2013
Cadence Design Systems September 2012 - December 2012
Cisco Systems April 2012 - July 2012
Motorola Mobility Inc March 2008 - November 2011
Motorola Mobile Devices March 2008 - October 2011
Foundry Networks (acquired by Brocade) May 2007 - November 2007
Foundry Networks May 2007 - November 2007
ACCESS Systems Americas, Inc. December 2005 - May 2007
Skills
Microsoft Word,..., Adobe Acrobat..., MediaWiki/SourceForge/Co..., Google Apps (Mail,..., Leadership, Adobe Acrobat, Product Development, Technical Support, Marketing, Web Applications, Online Help, Editing, Hardware, Cisco Technologies, Manuals, IP
Education
Howard University 1960 — 1966
BA, Commercial Art
Howard University
Bachelor of Fine Arts, Commercial Art
NetApp (Artizen) January 2014 - April 2014
Google via Artech August 2013 - October 2013
NVIDIA (West Valley Staffing) January 2013 - June 2013
Cadence Design Systems September 2012 - December 2012
Cisco Systems April 2012 - July 2012
Motorola Mobility Inc March 2008 - November 2011
Motorola Mobile Devices March 2008 - October 2011
Foundry Networks (acquired by Brocade) May 2007 - November 2007
Foundry Networks May 2007 - November 2007
ACCESS Systems Americas, Inc. December 2005 - May 2007
Skills
Microsoft Word,..., Adobe Acrobat..., MediaWiki/SourceForge/Co..., Google Apps (Mail,..., Leadership, Adobe Acrobat, Product Development, Technical Support, Marketing, Web Applications, Online Help, Editing, Hardware, Cisco Technologies, Manuals, IP
Education
Howard University 1960 — 1966
BA, Commercial Art
Howard University
Bachelor of Fine Arts, Commercial Art
Subash Sundaresan Subash Sundaresan's Cadence Design Systems Experience 1990 - 1992
Job iAd Engineering at Apple
Industry Computer Software
Experience
Apple 2012 - Present
Zynga 2011 - 2012
Amobee Media Systems (acquired by SingTel) 2009 - 2011
Yahoo! 2006 - 2009
Synopsys Inc. 2004 - 2006
Inktomi Corp. 2000 - 2003
Synopsys Inc. 1994 - 2000
Duet Technologies 1992 - 1994
Cadence Design Systems 1990 - 1992
Education
The Ohio State University 1988 — 1990
MS
Indian Institute of Technology, Delhi 1984 — 1988
B.Tech
Apple 2012 - Present
Zynga 2011 - 2012
Amobee Media Systems (acquired by SingTel) 2009 - 2011
Yahoo! 2006 - 2009
Synopsys Inc. 2004 - 2006
Inktomi Corp. 2000 - 2003
Synopsys Inc. 1994 - 2000
Duet Technologies 1992 - 1994
Cadence Design Systems 1990 - 1992
Education
The Ohio State University 1988 — 1990
MS
Indian Institute of Technology, Delhi 1984 — 1988
B.Tech
David J Botticello Jr David J Botticello Jr's Cadence Design Systems Experience 1993 - Present
Job Sr Staff Support AE at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems 1993 - Present
GE 1985 - 1992
Security Bicycle Accessories 1979 - 1981
Skills
IC, Physical Verification, EDA, Electronics, Troubleshooting, Semiconductors, Physical Design, Analog Design, Analog, Analog Circuit Design, Unix, Program Management, Verilog, Mixed Signal, Hardware, Cadence, VLSI, Product Marketing, ASIC, Hardware Architecture, Cross-functional Team..., Product Development, Electrical Engineering, Perl, FPGA, Algorithms, SoC
Education
Hudson Valley Community College 1984 — 1985
AAS, Electronics Technology
Rensselaer Polytechnic Institute 1981 — 1985
EE
Lynbrook High School 1979 — 1984
Cadence Design Systems 1993 - Present
GE 1985 - 1992
Security Bicycle Accessories 1979 - 1981
Skills
IC, Physical Verification, EDA, Electronics, Troubleshooting, Semiconductors, Physical Design, Analog Design, Analog, Analog Circuit Design, Unix, Program Management, Verilog, Mixed Signal, Hardware, Cadence, VLSI, Product Marketing, ASIC, Hardware Architecture, Cross-functional Team..., Product Development, Electrical Engineering, Perl, FPGA, Algorithms, SoC
Education
Hudson Valley Community College 1984 — 1985
AAS, Electronics Technology
Rensselaer Polytechnic Institute 1981 — 1985
EE
Lynbrook High School 1979 — 1984
Shankar Hemmady's Cadence Design Systems Experience 2005 - 2007
Job Technologist, Entrepreneur, Author
Industry Computer Software
Experience
Project Happiness March 2012 - Present
Synopsys August 2007 - Present
Cadence Design Systems 2005 - 2007
Sun Microsystems 2003 - 2005
PharmQuest Corp. 1999 - 2003
Guru Technologies 1994 - 1999
Skills
Engineering Management, EDA, SoC, ASIC, IC, VLSI, RTL design, Physical Design, Semiconductors, TCL, Mixed Signal, PCIe, Verilog, Formal Verification, Processors, SystemVerilog, Functional Verification, FPGA, Microprocessors, Static Timing Analysis, Embedded Systems, Integrated Circuit..., DFT, Logic Synthesis, Entrepreneurship, Low-power Design, Mindfulness, Computer Architecture, Enterprise Software, UVM, Hardware Architecture, Timing Closure, Social Media, Logic Design, Analog Circuit Design, Signal Integrity, Digital Signal..., Start-up Ventures, RTL coding, ARM, Social Networking, Analog, Debugging, Simulations, VHDL
Education
Stanford University School of Medicine 2012 — 2013
CCARE Teacher Training
Stanford University Graduate School of Business 2002 — 2003
Executive Program, Advanced Management College
Kauffman Center for Entrepreneurial Leadership 2001 — 2001
Indian Institute of Technology, Bombay
B.S., Electrical Engineering
University of Iowa
M.S., Electrical & Computer Engineering
Project Happiness March 2012 - Present
Synopsys August 2007 - Present
Cadence Design Systems 2005 - 2007
Sun Microsystems 2003 - 2005
PharmQuest Corp. 1999 - 2003
Guru Technologies 1994 - 1999
Skills
Engineering Management, EDA, SoC, ASIC, IC, VLSI, RTL design, Physical Design, Semiconductors, TCL, Mixed Signal, PCIe, Verilog, Formal Verification, Processors, SystemVerilog, Functional Verification, FPGA, Microprocessors, Static Timing Analysis, Embedded Systems, Integrated Circuit..., DFT, Logic Synthesis, Entrepreneurship, Low-power Design, Mindfulness, Computer Architecture, Enterprise Software, UVM, Hardware Architecture, Timing Closure, Social Media, Logic Design, Analog Circuit Design, Signal Integrity, Digital Signal..., Start-up Ventures, RTL coding, ARM, Social Networking, Analog, Debugging, Simulations, VHDL
Education
Stanford University School of Medicine 2012 — 2013
CCARE Teacher Training
Stanford University Graduate School of Business 2002 — 2003
Executive Program, Advanced Management College
Kauffman Center for Entrepreneurial Leadership 2001 — 2001
Indian Institute of Technology, Bombay
B.S., Electrical Engineering
University of Iowa
M.S., Electrical & Computer Engineering
Kathleen Peters Kathleen Peters's Cadence Design Systems Experience May 1994 - July 1999
Job VP Product Management, Global Fraud & ID
Industry Security and Investigations
Experience
Experian April 2015 - Present
The 41st Parameter December 2013 - April 2015
Cellcrypt, Inc. July 2009 - November 2013
Carrier IQ July 2007 - July 2009
ACCESS Systems Americas (formerly PalmSource, Inc) September 2004 - May 2007
PacketVideo Corporation July 1999 - August 2004
Cadence Design Systems May 1994 - July 1999
Motorola, Inc. January 1991 - May 1994
Skills
Mobile Devices, Wireless, VoIP, Blackberry, 3G, Mobile Applications, Product Management, Start-ups, Telecommunications, Enterprise Software, Go-to-market Strategy, Business Development, Mobile Communications, Strategic Partnerships, Management, Security, Mobile Technology, Leadership, Networking, Strategy, SaaS
Education
Illinois Institute of Technology
MSEE
University of Missouri-Rolla
BSEE
Experian April 2015 - Present
The 41st Parameter December 2013 - April 2015
Cellcrypt, Inc. July 2009 - November 2013
Carrier IQ July 2007 - July 2009
ACCESS Systems Americas (formerly PalmSource, Inc) September 2004 - May 2007
PacketVideo Corporation July 1999 - August 2004
Cadence Design Systems May 1994 - July 1999
Motorola, Inc. January 1991 - May 1994
Skills
Mobile Devices, Wireless, VoIP, Blackberry, 3G, Mobile Applications, Product Management, Start-ups, Telecommunications, Enterprise Software, Go-to-market Strategy, Business Development, Mobile Communications, Strategic Partnerships, Management, Security, Mobile Technology, Leadership, Networking, Strategy, SaaS
Education
Illinois Institute of Technology
MSEE
University of Missouri-Rolla
BSEE
Bhawna Shiwani's Cadence Design Systems Experience July 2014 - July 2015
Job Masters in Robotics Engineering at Worcester Polytechnic Institute
Industry Research
Experience
Cadence Design Systems July 2014 - July 2015
Cadence Design Systems July 2012 - June 2014
techNITi'12( Anuual Technical Fest-NIT Jalandhar) November 2011 - March 2012
Advance Technology May 2011 - July 2011
TRI Technosolutions Pvt Ltd. June 2010 - July 2010
Skills
Technical Leadership, Embedded Systems, Wireless, Debugging, Embedded Software, Perl, Software Engineering, Unix, FPGA, Digital Signal..., Simulations, System Design, Verilog, Systems Engineering, PCB design, IP, Semiconductors, Matlab, CMOS RF IC Design, Integrated Circuit..., Microcontrollers, Cadence Virtuoso, Analog Circuit Design, Pspice, Analog, Mixed Signal, Cadence, EDA, VLSI, Electronics, PCB Design, PSpice
Education
Worcester Polytechnic Institute 2015 — 2017
Masters in Mechatronics, Robotics and Automation, Robotics and Artificial Intelligence
Indian Institute of Technology, Delhi 2013 — 2013
Professional Candidate, CMOS RF IC Design
Dr B R Ambedkar National Institute of Technology,Jalandhar 2008 — 2012
Bachelor of Technology, Electronics and Communication
Government Girls School, Fazilka 2006 — 2008
Senior Secondary, Non Medical
Worcester Polytechnic Institute
Cadence Design Systems July 2014 - July 2015
Cadence Design Systems July 2012 - June 2014
techNITi'12( Anuual Technical Fest-NIT Jalandhar) November 2011 - March 2012
Advance Technology May 2011 - July 2011
TRI Technosolutions Pvt Ltd. June 2010 - July 2010
Skills
Technical Leadership, Embedded Systems, Wireless, Debugging, Embedded Software, Perl, Software Engineering, Unix, FPGA, Digital Signal..., Simulations, System Design, Verilog, Systems Engineering, PCB design, IP, Semiconductors, Matlab, CMOS RF IC Design, Integrated Circuit..., Microcontrollers, Cadence Virtuoso, Analog Circuit Design, Pspice, Analog, Mixed Signal, Cadence, EDA, VLSI, Electronics, PCB Design, PSpice
Education
Worcester Polytechnic Institute 2015 — 2017
Masters in Mechatronics, Robotics and Automation, Robotics and Artificial Intelligence
Indian Institute of Technology, Delhi 2013 — 2013
Professional Candidate, CMOS RF IC Design
Dr B R Ambedkar National Institute of Technology,Jalandhar 2008 — 2012
Bachelor of Technology, Electronics and Communication
Government Girls School, Fazilka 2006 — 2008
Senior Secondary, Non Medical
Worcester Polytechnic Institute
Vibhor Garg Vibhor Garg's Cadence Design Systems Experience July 2012 - Present
Job Senior Member of Consulting Staff, Timing Team at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2012 - Present
Cadence Design Systems May 2011 - June 2012
Mentor Graphics Corporation July 2006 - May 2011
Mentor Graphics Corporation April 2003 - June 2006
IKOS Systems August 2001 - April 2002
Skills
Emulation, EDA, Static Timing Analysis, Hardware, Perl, Logic Design, FPGA, Testing, Linux, Unix, SoC, Debugging, ASIC, Compilers, Software Design, Verilog, TCL, Algorithms, Simulations, C++
Education
University of Massachusetts, Amherst 1999 — 2002
MS CSE, Computer Systems Engineering
Indian Institute of Technology, Roorkee 1995 — 1999
B.E., Electrical Engineering
Mahanagar Boys Inter College 1987 — 1994
Cadence Design Systems July 2012 - Present
Cadence Design Systems May 2011 - June 2012
Mentor Graphics Corporation July 2006 - May 2011
Mentor Graphics Corporation April 2003 - June 2006
IKOS Systems August 2001 - April 2002
Skills
Emulation, EDA, Static Timing Analysis, Hardware, Perl, Logic Design, FPGA, Testing, Linux, Unix, SoC, Debugging, ASIC, Compilers, Software Design, Verilog, TCL, Algorithms, Simulations, C++
Education
University of Massachusetts, Amherst 1999 — 2002
MS CSE, Computer Systems Engineering
Indian Institute of Technology, Roorkee 1995 — 1999
B.E., Electrical Engineering
Mahanagar Boys Inter College 1987 — 1994
Chien-Chung (Chris) Tsai Chien-Chung (Chris) Tsai's Cadence Design Systems Experience December 1988 - September 1990
Job Math Faculty at Bard High School Early College Baltimore
Industry Education Management
Experience
Bard High School Early College Baltimore August 2015 - Present
Denver Public Schools July 2014 - June 2015
Intel Corp. August 2011 - March 2014
Intel Corporation May 2005 - August 2011
Mentor Graphics January 1996 - February 2003
Cadence Design Systems December 1988 - September 1990
Unisys August 1984 - December 1988
Skills
Algorithms Design and..., Design For Test, Failure Diagnosis, Agile Methodologies, Teaching, Artificial Intelligence, Scan Design, Logic BIST, ATPG, SOC test, ASIC, Verilog, VHDL, SoC, Debugging, Software Engineering, Automated Software..., C, C++, Prolog, Perl, TCL, Lisp, SKILL, Fortran, Scrum Software...
Education
University of California, Santa Barbara 1991 — 1996
Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering
University of Florida 1981 — 1984
ABD (Candidate for Ph.D.), Mathematics
Illinois Institute of Technology 1979 — 1981
Master of Science (M.S.), Applied Mathematics
National Chengchi University 1973 — 1977
Bachelor of Science (BS), Applied Mathematics
Bard High School Early College Baltimore August 2015 - Present
Denver Public Schools July 2014 - June 2015
Intel Corp. August 2011 - March 2014
Intel Corporation May 2005 - August 2011
Mentor Graphics January 1996 - February 2003
Cadence Design Systems December 1988 - September 1990
Unisys August 1984 - December 1988
Skills
Algorithms Design and..., Design For Test, Failure Diagnosis, Agile Methodologies, Teaching, Artificial Intelligence, Scan Design, Logic BIST, ATPG, SOC test, ASIC, Verilog, VHDL, SoC, Debugging, Software Engineering, Automated Software..., C, C++, Prolog, Perl, TCL, Lisp, SKILL, Fortran, Scrum Software...
Education
University of California, Santa Barbara 1991 — 1996
Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering
University of Florida 1981 — 1984
ABD (Candidate for Ph.D.), Mathematics
Illinois Institute of Technology 1979 — 1981
Master of Science (M.S.), Applied Mathematics
National Chengchi University 1973 — 1977
Bachelor of Science (BS), Applied Mathematics
Miriam Ottesen Miriam Ottesen's Cadence Design Systems Experience 2004 - 2006
Job Executive Assistant at TIC / Kiewit
Industry Oil & Energy
Experience
TIC / Kiewit June 2014 - Present
CLYDEUNION Pumps August 2011 - June 2014
Sysco July 2011 - August 2011
Baker Hughes June 2011 - July 2011
Wood Partners March 2011 - June 2011
Foster Wheeler November 2010 - March 2011
Aramco Services Company - Ras Tanura Project with Dow Chemicals January 2008 - November 2010
Repsol YPF June 2007 - December 2007
Cadence Design Systems 2004 - 2006
New Focus 2000 - 2003
Skills
Administrative..., Microsoft Office, Customer Service, Human Resources, Microsoft Word, Outlook, Recruiting, Event Planning, Event Management, Office Management, PowerPoint, Microsoft Excel, Software Documentation, Logistics, Budgets, Time Management, Employee Relations, Leadership, Training, Access, Team Building, Payroll, Team Leadership, Administrative...
Education
College of Distributive Trades 1977 — 1980
BS, Communications
American High School, San Salvador, El Salvador 1962 — 1976
High School Diploma, Math and English
Academie de Tours
French as a foreign language, French Studies, A
Heald College
Administrative Assistant and Secretarial Science, General, A
TIC / Kiewit June 2014 - Present
CLYDEUNION Pumps August 2011 - June 2014
Sysco July 2011 - August 2011
Baker Hughes June 2011 - July 2011
Wood Partners March 2011 - June 2011
Foster Wheeler November 2010 - March 2011
Aramco Services Company - Ras Tanura Project with Dow Chemicals January 2008 - November 2010
Repsol YPF June 2007 - December 2007
Cadence Design Systems 2004 - 2006
New Focus 2000 - 2003
Skills
Administrative..., Microsoft Office, Customer Service, Human Resources, Microsoft Word, Outlook, Recruiting, Event Planning, Event Management, Office Management, PowerPoint, Microsoft Excel, Software Documentation, Logistics, Budgets, Time Management, Employee Relations, Leadership, Training, Access, Team Building, Payroll, Team Leadership, Administrative...
Education
College of Distributive Trades 1977 — 1980
BS, Communications
American High School, San Salvador, El Salvador 1962 — 1976
High School Diploma, Math and English
Academie de Tours
French as a foreign language, French Studies, A
Heald College
Administrative Assistant and Secretarial Science, General, A
Vinay Garg Vinay Garg's Cadence Design Systems Experience July 2007 - December 2008
Job Software Engineer at Google
Industry Computer Software
Experience
Google March 2015 - Present
Microsoft December 2008 - March 2015
Cadence Design Systems July 2007 - December 2008
Geometric Ltd. August 2002 - July 2007
Skills
Java, C#, Software Development, XML, JavaScript, Project Management, SDLC, Software Project..., C++, Project Planning, SQL, Requirements Analysis
Education
Indian Institute of Technology, Delhi 1998 — 2002
Bachelor of Technology (B.Tech.)
Google March 2015 - Present
Microsoft December 2008 - March 2015
Cadence Design Systems July 2007 - December 2008
Geometric Ltd. August 2002 - July 2007
Skills
Java, C#, Software Development, XML, JavaScript, Project Management, SDLC, Software Project..., C++, Project Planning, SQL, Requirements Analysis
Education
Indian Institute of Technology, Delhi 1998 — 2002
Bachelor of Technology (B.Tech.)
Seow Yin Lim Seow Yin Lim's Cadence Design Systems Experience March 2014 - Present
Job Consumer Apps, Enterprise Software, Internet of Things, Child Development
Industry Computer Software
Experience
AntWish Inc (Povi.me) April 2014 - Present
Cadence Design Systems March 2014 - Present
Cadence Design Systems June 2012 - February 2014
Telegent Systems (acquired by Spreadtrum) August 2010 - June 2011
Broadcom June 2006 - August 2010
Broadcom August 2003 - June 2006
AMCC (MMC Network acquired) 2001 - 2003
MMC Networks / AMCC 1997 - 2003
MMC Networks 1997 - 2001
Skills
Early-stage Startups, Entrepreneurship, Employee Wellness, Consumer Software, Branding, Child Development, Big Data, Wireless, Success Driven, Social Media Marketing, Design, IOT, Demand Generation, Semiconductors, Product Management, Enterprise Software, Telecommunications, ASIC, SoC, Strategic Partnerships, Product Launch, Bluetooth, Strategy, IC, Networking, Ethernet, Return on Investment, Team Building, Consumer Products, Start-ups, Product Marketing
Education
Stanford 1996 — 1997
MSEE, EE
Imperial College London 1993 — 1996
BSEE
AntWish Inc (Povi.me) April 2014 - Present
Cadence Design Systems March 2014 - Present
Cadence Design Systems June 2012 - February 2014
Telegent Systems (acquired by Spreadtrum) August 2010 - June 2011
Broadcom June 2006 - August 2010
Broadcom August 2003 - June 2006
AMCC (MMC Network acquired) 2001 - 2003
MMC Networks / AMCC 1997 - 2003
MMC Networks 1997 - 2001
Skills
Early-stage Startups, Entrepreneurship, Employee Wellness, Consumer Software, Branding, Child Development, Big Data, Wireless, Success Driven, Social Media Marketing, Design, IOT, Demand Generation, Semiconductors, Product Management, Enterprise Software, Telecommunications, ASIC, SoC, Strategic Partnerships, Product Launch, Bluetooth, Strategy, IC, Networking, Ethernet, Return on Investment, Team Building, Consumer Products, Start-ups, Product Marketing
Education
Stanford 1996 — 1997
MSEE, EE
Imperial College London 1993 — 1996
BSEE
Vigyan Singhal Vigyan Singhal's Cadence Design Systems Experience August 1995 - August 1999
Job CEO at Oski Technology
Industry Semiconductors
Experience
Oski Technology October 2005 - Present
Elastix September 2006 - December 2008
Jasper Design Automation March 2003 - October 2005
Jasper Design Automation October 1999 - March 2003
Cadence Design Systems August 1995 - August 1999
University of California at Berkeley August 1990 - July 1995
Skills
Formal Verification, Functional Verification, Leadership, Training, Entrepreneurship, EDA, Simulations, Verilog, SoC, ASIC, Hardware, Algorithms, Semiconductors, Start-ups, IC, Embedded Systems, FPGA, Debugging, C, Microprocessors, Python, Software Development, TCL, Software Engineering, Product Management, C++, Low-power Design, Embedded Software, SystemVerilog, SystemC, VLSI, Machine Learning, Linux, Digital Signal..., Processors, Logic Synthesis, System Architecture
Education
University of California at Berkeley 1992 — 1995
PhD, Computer Science
University of California at Berkeley 1989 — 1992
MS, Computer Science
Indian Institute of Technology, Kanpur 1985 — 1989
BTech, Computer Science and Engineering
The Mother's International School, New Delhi 1975 — 1985
High School
Oski Technology October 2005 - Present
Elastix September 2006 - December 2008
Jasper Design Automation March 2003 - October 2005
Jasper Design Automation October 1999 - March 2003
Cadence Design Systems August 1995 - August 1999
University of California at Berkeley August 1990 - July 1995
Skills
Formal Verification, Functional Verification, Leadership, Training, Entrepreneurship, EDA, Simulations, Verilog, SoC, ASIC, Hardware, Algorithms, Semiconductors, Start-ups, IC, Embedded Systems, FPGA, Debugging, C, Microprocessors, Python, Software Development, TCL, Software Engineering, Product Management, C++, Low-power Design, Embedded Software, SystemVerilog, SystemC, VLSI, Machine Learning, Linux, Digital Signal..., Processors, Logic Synthesis, System Architecture
Education
University of California at Berkeley 1992 — 1995
PhD, Computer Science
University of California at Berkeley 1989 — 1992
MS, Computer Science
Indian Institute of Technology, Kanpur 1985 — 1989
BTech, Computer Science and Engineering
The Mother's International School, New Delhi 1975 — 1985
High School
Madan Das Madan Das's Cadence Design Systems Experience January 2006 - August 2008
Job Sr. Staff Software Engineer at Xilinx Inc.
Industry Semiconductors
Experience
Mentor Graphics November 2013 - Present
Xilinx Inc. February 2011 - October 2013
Apache Design Solutions August 2008 - January 2011
Cadence Design Systems January 2006 - August 2008
Axis System April 2000 - December 2005
Gatefield Corporation April 1998 - April 2000
Cadence Spectrum Services October 1996 - April 1998
Cadence Design Systems (India) June 1994 - October 1996
Skills
EDA, Software Development, C++, PHP, phpMyAdmin, Verilog, Formal Verification, Compiler Optimization, Data Mining, Algorithm Design, Parallel Algorithms, Computer Architecture, Parallel Computing, Graph Theory, BDD, Cadence Skill, VLSI, Perl, Debugging, Algorithms, TCL, FPGA, Semiconductors
Education
University of California, Santa Cruz 2007 — 2014
Doctor of Philosophy (PhD), Computer Engineering, A
Indian Institute of Technology, Kharagpur 1990 — 1994
Bachelor of Technology (BTech), Computer Science & Engineering
Kendriya Vidyalaya 1980 — 1990
High School, Science
Mentor Graphics November 2013 - Present
Xilinx Inc. February 2011 - October 2013
Apache Design Solutions August 2008 - January 2011
Cadence Design Systems January 2006 - August 2008
Axis System April 2000 - December 2005
Gatefield Corporation April 1998 - April 2000
Cadence Spectrum Services October 1996 - April 1998
Cadence Design Systems (India) June 1994 - October 1996
Skills
EDA, Software Development, C++, PHP, phpMyAdmin, Verilog, Formal Verification, Compiler Optimization, Data Mining, Algorithm Design, Parallel Algorithms, Computer Architecture, Parallel Computing, Graph Theory, BDD, Cadence Skill, VLSI, Perl, Debugging, Algorithms, TCL, FPGA, Semiconductors
Education
University of California, Santa Cruz 2007 — 2014
Doctor of Philosophy (PhD), Computer Engineering, A
Indian Institute of Technology, Kharagpur 1990 — 1994
Bachelor of Technology (BTech), Computer Science & Engineering
Kendriya Vidyalaya 1980 — 1990
High School, Science
Mala Sarma Mala Sarma's Cadence Design Systems Experience February 1996 - February 1998
Job Sr CAE Manager at Synopsys
Industry Semiconductors
Experience
Synopsys November 2010 - December 2014
Synopsys September 2003 - November 2010
Synplicity Inc February 1998 - September 2003
Cadence Design Systems February 1996 - February 1998
Skills
EDA, ASIC, FPGA, SoC, VLSI, IC, Management, RTL Design, Verilog, SystemVerilog, VHDL, ModelSim, C, TCL, Perl, Product Management, Software Development, Product Development, Training, Cross-functional Team..., Semiconductors, SharePoint, Statistics, Electrical Engineering, Start-ups
Education
The University of Texas at Austin 1994 — 1996
MSEE, Electrical Engineering, Computer Engineering
Indian Institute of Technology, Kharagpur 1989 — 1993
Bachelor of Technology (B.Tech.), Electrical Eng
Synopsys November 2010 - December 2014
Synopsys September 2003 - November 2010
Synplicity Inc February 1998 - September 2003
Cadence Design Systems February 1996 - February 1998
Skills
EDA, ASIC, FPGA, SoC, VLSI, IC, Management, RTL Design, Verilog, SystemVerilog, VHDL, ModelSim, C, TCL, Perl, Product Management, Software Development, Product Development, Training, Cross-functional Team..., Semiconductors, SharePoint, Statistics, Electrical Engineering, Start-ups
Education
The University of Texas at Austin 1994 — 1996
MSEE, Electrical Engineering, Computer Engineering
Indian Institute of Technology, Kharagpur 1989 — 1993
Bachelor of Technology (B.Tech.), Electrical Eng
Sanjay Krishnan Sanjay Krishnan's Cadence Design Systems Experience 1998 - 2001
Job Ecosystem & Platforms: Hardware, Software and Data
Industry Information Technology and Services
Experience
Google 2014 - Present
Keystone Strategy 2010 - 2013
Maxim Integrated Products 2006 - 2010
Global Semiconductor Alliance 2006 - 2008
Skyworks Solutions, Inc 2001 - 2006
Cadence Design Systems 1998 - 2001
Skills
Electronics, Telecommunications, Semiconductors, Mixed Signal, Business Strategy, Analytics, Product Marketing, Enterprise Software, Business Development, Strategy, ASIC, Entrepreneurship, IC, CRM, Product Management, Management, Cross-functional Team...
Education
University of California, Berkeley - Walter A. Haas School of Business 2007 — 2010
MBA, Strategy
University of Southern California 1997 — 1998
MS, Electrical Engineering
Indian Institute of Technology, Madras 1993 — 1997
B.Tech, Electrical Engineering
PSBB Senior Secondary School, KK Nagar, Chennai
Google 2014 - Present
Keystone Strategy 2010 - 2013
Maxim Integrated Products 2006 - 2010
Global Semiconductor Alliance 2006 - 2008
Skyworks Solutions, Inc 2001 - 2006
Cadence Design Systems 1998 - 2001
Skills
Electronics, Telecommunications, Semiconductors, Mixed Signal, Business Strategy, Analytics, Product Marketing, Enterprise Software, Business Development, Strategy, ASIC, Entrepreneurship, IC, CRM, Product Management, Management, Cross-functional Team...
Education
University of California, Berkeley - Walter A. Haas School of Business 2007 — 2010
MBA, Strategy
University of Southern California 1997 — 1998
MS, Electrical Engineering
Indian Institute of Technology, Madras 1993 — 1997
B.Tech, Electrical Engineering
PSBB Senior Secondary School, KK Nagar, Chennai
Deepak Nadig Deepak Nadig's Cadence Design Systems Experience 1993 - 1995
Job Head of API & Developer Platform Engineering @ PayPal
Industry Computer Software
Experience
PayPal February 2012 - Present
eBay August 2011 - February 2012
eBay March 2010 - August 2011
eBay July 2006 - March 2010
Convenos July 2005 - June 2006
Covigna, Inc. (purchased by ProQuest Business Solutions) October 2000 - July 2005
Hewlett Packard Labs February 2000 - October 2000
VeriFone (acquired by HP) 1996 - January 2000
EIT (acquired by VeriFone) 1995 - 1996
Cadence Design Systems 1993 - 1995
Skills
Distributed Systems, Web Services, SOA, Enterprise Architecture, Application Architecture, Web Analytics, Experimentation, Advertising, Contract Management, Internet Security, Cryptography, Payment Systems, Online Advertising, DRM, Agile Project Management, Java Enterprise Edition, SaaS, Web Applications, Enterprise Software, Payment Industry, Scalability, IT Strategy, Analytics, CRM, Architectures, Engineering Leadership, Online Platforms, REST, Architecture
Education
Louisiana State University 1991 — 1993
M.S.
Indian Institute of Technology, Bombay 1985 — 1989
B. Tech.
Bharatiya Vidya Bhavan Public School 1976 — 1983
PayPal February 2012 - Present
eBay August 2011 - February 2012
eBay March 2010 - August 2011
eBay July 2006 - March 2010
Convenos July 2005 - June 2006
Covigna, Inc. (purchased by ProQuest Business Solutions) October 2000 - July 2005
Hewlett Packard Labs February 2000 - October 2000
VeriFone (acquired by HP) 1996 - January 2000
EIT (acquired by VeriFone) 1995 - 1996
Cadence Design Systems 1993 - 1995
Skills
Distributed Systems, Web Services, SOA, Enterprise Architecture, Application Architecture, Web Analytics, Experimentation, Advertising, Contract Management, Internet Security, Cryptography, Payment Systems, Online Advertising, DRM, Agile Project Management, Java Enterprise Edition, SaaS, Web Applications, Enterprise Software, Payment Industry, Scalability, IT Strategy, Analytics, CRM, Architectures, Engineering Leadership, Online Platforms, REST, Architecture
Education
Louisiana State University 1991 — 1993
M.S.
Indian Institute of Technology, Bombay 1985 — 1989
B. Tech.
Bharatiya Vidya Bhavan Public School 1976 — 1983
Jayashree Rajendran Jayashree Rajendran's Cadence Design Systems Experience 1995 - 1997
Job
Industry Internet
Experience
NeuronLinks August 1998 - Present
Cadence Design Systems 1995 - 1997
Cadence Design Systems 1989 - 1996
Cadence Design Systems 1990 - 1994
Cadence Design Systems 1988 - 1990
AMD 1987 - 1988
Skills
Leadership, Embedded Systems, Product Management, Enterprise Software, Start-ups, Distributed Systems, Perl, Software Development, Scalability, Program Management, Cloud Computing, Cross-functional Team..., SaaS
Education
San Jose State University
M.S. Electrical Engineering
Indian Institute of Science 1981 — 1984
BE, ECE
National College 1978 — 1981
B.Sc
NeuronLinks August 1998 - Present
Cadence Design Systems 1995 - 1997
Cadence Design Systems 1989 - 1996
Cadence Design Systems 1990 - 1994
Cadence Design Systems 1988 - 1990
AMD 1987 - 1988
Skills
Leadership, Embedded Systems, Product Management, Enterprise Software, Start-ups, Distributed Systems, Perl, Software Development, Scalability, Program Management, Cloud Computing, Cross-functional Team..., SaaS
Education
San Jose State University
M.S. Electrical Engineering
Indian Institute of Science 1981 — 1984
BE, ECE
National College 1978 — 1981
B.Sc
Ahmad Kamal Ahmad Kamal's Cadence Design Systems Experience July 2010 - January 2012
Job Software Developer II at Epic
Industry Computer Software
Experience
Epic May 2015 - Present
Epic February 2012 - April 2015
Cadence Design Systems July 2010 - January 2012
Cadence Design Systems March 2006 - June 2010
STMicroelectronics August 2004 - March 2006
Skills
EDA, Data Structures, Computer Architecture, C++, Distributed Systems, Signal Integrity, Software Development, Embedded Systems, Java, Linux, Software Engineering
Education
Indian Institute of Technology, Kanpur 2002 — 2004
Master of Technology, Computer Sc. & Engineering
HBTI, Kanpur 1998 — 2002
Bachelor of Technology, Computer Sc. & Engineering
Campus School, Pantnagar 1997 — 1998
PCM
Epic May 2015 - Present
Epic February 2012 - April 2015
Cadence Design Systems July 2010 - January 2012
Cadence Design Systems March 2006 - June 2010
STMicroelectronics August 2004 - March 2006
Skills
EDA, Data Structures, Computer Architecture, C++, Distributed Systems, Signal Integrity, Software Development, Embedded Systems, Java, Linux, Software Engineering
Education
Indian Institute of Technology, Kanpur 2002 — 2004
Master of Technology, Computer Sc. & Engineering
HBTI, Kanpur 1998 — 2002
Bachelor of Technology, Computer Sc. & Engineering
Campus School, Pantnagar 1997 — 1998
PCM
Manjeet Rekhi Manjeet Rekhi's Cadence Design Systems Experience 1992 - 1995
Job Principal Architect at Kellogg Company
Industry Food & Beverages
Experience
Kellogg Company November 2013 - Present
Kellogg Company November 2007 - November 2013
Kellogg Company September 2003 - November 2007
Kellogg Company January 2002 - September 2003
iGate Mastech 1995 - 2002
Xerox 1996 - 1997
Cadence Design Systems 1992 - 1995
Tata Unisys Ltd. 1989 - 1992
ORG Systems December 1986 - April 1989
DDE ORG 1986 - 1989
Skills
Analysis, Integration, Vendor Management, Requirements Analysis, Enterprise Architecture, Cross-functional Team..., Project Management, Unix, Servers, ERP, Management, TCP/IP, Operating Systems, Testing, DNS, Network Administration, System Administration, Perl, Solaris, Apache, Business Process, Hardware, Program Management, Storage, Networking, Shell Scripting, Telecommunications, Architectures, Disaster Recovery, Security, Cloud Computing
Education
Indira Gandhi National Open University 1993 — 1998
MBA, Marketing
National Institute of Technology Calicut 1982 — 1986
B. Tech, Electrical
Regional Engineering College, Calicut 1982 — 1986
B. Tech, Electrical
Kendriya Vidyalaya 1970 — 1982
Kellogg Company November 2013 - Present
Kellogg Company November 2007 - November 2013
Kellogg Company September 2003 - November 2007
Kellogg Company January 2002 - September 2003
iGate Mastech 1995 - 2002
Xerox 1996 - 1997
Cadence Design Systems 1992 - 1995
Tata Unisys Ltd. 1989 - 1992
ORG Systems December 1986 - April 1989
DDE ORG 1986 - 1989
Skills
Analysis, Integration, Vendor Management, Requirements Analysis, Enterprise Architecture, Cross-functional Team..., Project Management, Unix, Servers, ERP, Management, TCP/IP, Operating Systems, Testing, DNS, Network Administration, System Administration, Perl, Solaris, Apache, Business Process, Hardware, Program Management, Storage, Networking, Shell Scripting, Telecommunications, Architectures, Disaster Recovery, Security, Cloud Computing
Education
Indira Gandhi National Open University 1993 — 1998
MBA, Marketing
National Institute of Technology Calicut 1982 — 1986
B. Tech, Electrical
Regional Engineering College, Calicut 1982 — 1986
B. Tech, Electrical
Kendriya Vidyalaya 1970 — 1982
Abha Maheshwari Abha Maheshwari's Cadence Design Systems Experience June 2010 - March 2012
Job Product Growth and Strategy | Product Management | Facebook/ Mobile Advertising
Industry Internet
Experience
Facebook July 2012 - Present
Cadence Design Systems June 2010 - March 2012
Magma Design Automation October 2007 - June 2010
Magma Design Automation March 2004 - September 2007
Cadence Design Systems February 2002 - February 2004
Skills
Product Management, Product Marketing, Product Development, Product Strategy, IC, Technical Marketing, Product Lifecycle..., Embedded Systems, Strategic Partnerships, Engineering Management, Big Data, Social Media, Social Media Marketing, Wireless, Entrepreneurship, Software Development, Start-ups, Management, Cross-functional Team..., Go-to-market Strategy, ASIC, Strategy, Enterprise Software, Partnership Marketing, Semiconductors
Education
University of California, Berkeley - Walter A. Haas School of Business 2010 — 2013
Master of Business Administration (MBA), Business Administration and Management, General
University of California, Santa Barbara 2000 — 2001
MS, Computer Engineering
Indian Institute of Technology, Bombay 1996 — 2000
B.Tech, Electrical Engineering
Facebook July 2012 - Present
Cadence Design Systems June 2010 - March 2012
Magma Design Automation October 2007 - June 2010
Magma Design Automation March 2004 - September 2007
Cadence Design Systems February 2002 - February 2004
Skills
Product Management, Product Marketing, Product Development, Product Strategy, IC, Technical Marketing, Product Lifecycle..., Embedded Systems, Strategic Partnerships, Engineering Management, Big Data, Social Media, Social Media Marketing, Wireless, Entrepreneurship, Software Development, Start-ups, Management, Cross-functional Team..., Go-to-market Strategy, ASIC, Strategy, Enterprise Software, Partnership Marketing, Semiconductors
Education
University of California, Berkeley - Walter A. Haas School of Business 2010 — 2013
Master of Business Administration (MBA), Business Administration and Management, General
University of California, Santa Barbara 2000 — 2001
MS, Computer Engineering
Indian Institute of Technology, Bombay 1996 — 2000
B.Tech, Electrical Engineering
Rob Tripp Rob Tripp's Cadence Design Systems Experience January 2000 - October 2001
Job Service Project Manager at Schneider Electric
Industry Electrical/Electronic Manufacturing
Experience
Schneider Electric May 2014 - Present
Hoffman Building Technologies February 2011 - May 2014
Schneider Electric March 2006 - February 2011
Mark Hall Electric, Inc. June 2004 - March 2006
Cadence Design Systems January 2000 - October 2001
Skills
Troubleshooting, Energy Efficiency, Project Management, Automation, Operations Management, Microsoft Office, Construction, HVAC, Engineering, Manufacturing, Building Automation, Energy Management, Strategic Planning, Electricians, Alerton, BACnet, LonWorks, HVAC Controls, Control Systems Design, Building Management..., Electronics, Testing
Education
John Wesley College 2002 — 2005
BA, Christian Ministry
Hinds Community College 1997 — 1999
AAS, Electronics Technology
Clinton High School 1994 — 1997
Diploma
Schneider Electric May 2014 - Present
Hoffman Building Technologies February 2011 - May 2014
Schneider Electric March 2006 - February 2011
Mark Hall Electric, Inc. June 2004 - March 2006
Cadence Design Systems January 2000 - October 2001
Skills
Troubleshooting, Energy Efficiency, Project Management, Automation, Operations Management, Microsoft Office, Construction, HVAC, Engineering, Manufacturing, Building Automation, Energy Management, Strategic Planning, Electricians, Alerton, BACnet, LonWorks, HVAC Controls, Control Systems Design, Building Management..., Electronics, Testing
Education
John Wesley College 2002 — 2005
BA, Christian Ministry
Hinds Community College 1997 — 1999
AAS, Electronics Technology
Clinton High School 1994 — 1997
Diploma
Vishal Anand Vishal Anand's Cadence Design Systems Experience June 2011 - May 2012
Job Principal Engineer at Ericsson
Industry Semiconductors
Experience
Ericsson November 2014 - Present
XPliant August 2012 - November 2014
Cadence Design Systems June 2011 - May 2012
Cisco 2002 - June 2011
Aarohi Communications 2001 - 2001
VLSI Tech / Philips 1996 - 2001
US Robotics May 1995 - February 1996
IBM February 1994 - April 1995
HCL Hewlett Packard 1991 - 1994
Skills
Static Timing Analysis, EDA, ASIC, TCL, Verilog, Formal Verification, SystemVerilog, RTL design, Functional Verification, FPGA, SoC, Embedded Systems, Debugging, Ethernet, VLSI, Computer Architecture, IC, Perl, Semiconductors, PCIe, C, IP, Hardware Architecture
Education
Indian Institute of Technology, Roorkee 1987 — 1991
BE, Electronics & Communications
San Jose State University 1998 — 2001
MS, Computer Engineering
Springdales School 1973 — 1987
Ericsson November 2014 - Present
XPliant August 2012 - November 2014
Cadence Design Systems June 2011 - May 2012
Cisco 2002 - June 2011
Aarohi Communications 2001 - 2001
VLSI Tech / Philips 1996 - 2001
US Robotics May 1995 - February 1996
IBM February 1994 - April 1995
HCL Hewlett Packard 1991 - 1994
Skills
Static Timing Analysis, EDA, ASIC, TCL, Verilog, Formal Verification, SystemVerilog, RTL design, Functional Verification, FPGA, SoC, Embedded Systems, Debugging, Ethernet, VLSI, Computer Architecture, IC, Perl, Semiconductors, PCIe, C, IP, Hardware Architecture
Education
Indian Institute of Technology, Roorkee 1987 — 1991
BE, Electronics & Communications
San Jose State University 1998 — 2001
MS, Computer Engineering
Springdales School 1973 — 1987
Raja Mitra Raja Mitra's Cadence Design Systems Experience June 2010 - Present
Job Director at Cadence Design Systems Inc.
Industry Semiconductors
Experience
Cadence Design Systems June 2010 - Present
Aakash Educational Services Ltd. April 2009 - May 2010
Cadence Design Systems May 2001 - March 2008
IIT Kharagpur July 2000 - April 2001
G.A. Sullivan Software Development Solutions (now Avanade) January 1999 - August 1999
Skills
Project Management, Management, Leadership, Engineering, Global Delivery, Pre-sales, Product Management, Program Management, Team Management, Software Project..., Business Strategy, IT Strategy, Vendor Management, Business Development, Outsourcing, Start-ups, EDA, Strategy, Telecommunications, Requirements Analysis, Software Development, SaaS, Integration, Cloud Computing, Analytics, FPA, Statistical Modeling
Education
Indian Institute of Management, Ahmedabad 2008 — 2009
PGPX, Management
Washington University in St. Louis 1996 — 2000
D.Sc., MS, Systems Science and Mathematics
Indian Institute of Technology, Kharagpur 1992 — 1996
B.Tech., Electrical Engineering
St. Lawrence High School 1980 — 1992
High School, STEM
Cadence Design Systems June 2010 - Present
Aakash Educational Services Ltd. April 2009 - May 2010
Cadence Design Systems May 2001 - March 2008
IIT Kharagpur July 2000 - April 2001
G.A. Sullivan Software Development Solutions (now Avanade) January 1999 - August 1999
Skills
Project Management, Management, Leadership, Engineering, Global Delivery, Pre-sales, Product Management, Program Management, Team Management, Software Project..., Business Strategy, IT Strategy, Vendor Management, Business Development, Outsourcing, Start-ups, EDA, Strategy, Telecommunications, Requirements Analysis, Software Development, SaaS, Integration, Cloud Computing, Analytics, FPA, Statistical Modeling
Education
Indian Institute of Management, Ahmedabad 2008 — 2009
PGPX, Management
Washington University in St. Louis 1996 — 2000
D.Sc., MS, Systems Science and Mathematics
Indian Institute of Technology, Kharagpur 1992 — 1996
B.Tech., Electrical Engineering
St. Lawrence High School 1980 — 1992
High School, STEM
Aneesh Aggarwal, PhD Aneesh Aggarwal, PhD's Cadence Design Systems Experience 1999 - 1999
Job Computer Architect
Industry Semiconductors
Experience
Intel Corporation January 2011 - Present
NVIDIA June 2008 - December 2010
Portland State University March 2010 - April 2010
State University of New York September 2003 - July 2008
Air Force Research Laboratory June 2006 - August 2006
Hewlett-Packard Laboratories (Compaq Systems Research Center) May 2000 - August 2000
Ericsson 1999 - 1999
Cadence Design Systems 1999 - 1999
Tata Infotech 1996 - 1997
Skills
Computer Architecture, Microarchitecture, Programming, Compilers, Simulations, Hardware Architecture, Perl, Semiconductors, Embedded Systems, ASIC, Microprocessors, RTL design, VLSI, SoC, Processors, Debugging
Education
University of Maryland College Park
PhD, Computer Engineering
Indian Institute of Science
MS, Computer Science and Engineering
Visvesvaraya National Institute of Technology
BS, Electronics and Telecommunications
Intel Corporation January 2011 - Present
NVIDIA June 2008 - December 2010
Portland State University March 2010 - April 2010
State University of New York September 2003 - July 2008
Air Force Research Laboratory June 2006 - August 2006
Hewlett-Packard Laboratories (Compaq Systems Research Center) May 2000 - August 2000
Ericsson 1999 - 1999
Cadence Design Systems 1999 - 1999
Tata Infotech 1996 - 1997
Skills
Computer Architecture, Microarchitecture, Programming, Compilers, Simulations, Hardware Architecture, Perl, Semiconductors, Embedded Systems, ASIC, Microprocessors, RTL design, VLSI, SoC, Processors, Debugging
Education
University of Maryland College Park
PhD, Computer Engineering
Indian Institute of Science
MS, Computer Science and Engineering
Visvesvaraya National Institute of Technology
BS, Electronics and Telecommunications
Puneet Arora Puneet Arora's Cadence Design Systems Experience April 2012 - March 2013
Job Management Consultant (M&A Tech Strategy) at Deloitte Consulting
Industry Management Consulting
Experience
Deloitte Consulting (US) May 2014 - Present
Indian Institute of Management, Bangalore April 2013 - March 2014
Cadence Design Systems April 2012 - March 2013
Magma Design Automation October 2008 - March 2012
Cadence Design Systems November 2004 - October 2008
Skills
EDA, Semiconductors, Technical Marketing, Technical Product Sales, Logic Synthesis, SoC, Low-power Design, Software Engineering, DFT, ASIC, Technology Solutions, Process Integration, Solution Architecture, Strategy Implementation, Strategic Planning, Mergers & Acquisitions, Verilog, Business Analysis, Cross-functional..., Strategy, Debugging, Requirements Analysis, Management, Consulting, Leadership, Testing
Education
Indian Institute of Management, Bangalore 2013 — 2014
Executive Post Graduate Programme in Management (EPGP), Business, Management, Marketing, and Related Support Services
IIIT 2003 — 2005
MS, VLSI & Embedded Systems
Indraprastha University, Delhi 1999 — 2003
B. Tech, Computer Sciences/IT
Universal Public School, Delhi 1987 — 1999
High School, Physical Sciences
Deloitte Consulting (US) May 2014 - Present
Indian Institute of Management, Bangalore April 2013 - March 2014
Cadence Design Systems April 2012 - March 2013
Magma Design Automation October 2008 - March 2012
Cadence Design Systems November 2004 - October 2008
Skills
EDA, Semiconductors, Technical Marketing, Technical Product Sales, Logic Synthesis, SoC, Low-power Design, Software Engineering, DFT, ASIC, Technology Solutions, Process Integration, Solution Architecture, Strategy Implementation, Strategic Planning, Mergers & Acquisitions, Verilog, Business Analysis, Cross-functional..., Strategy, Debugging, Requirements Analysis, Management, Consulting, Leadership, Testing
Education
Indian Institute of Management, Bangalore 2013 — 2014
Executive Post Graduate Programme in Management (EPGP), Business, Management, Marketing, and Related Support Services
IIIT 2003 — 2005
MS, VLSI & Embedded Systems
Indraprastha University, Delhi 1999 — 2003
B. Tech, Computer Sciences/IT
Universal Public School, Delhi 1987 — 1999
High School, Physical Sciences
Sandeep Bhatia's Cadence Design Systems Experience 1998 - January 2009
Job TLM Software Engineering at Google
Industry Computer Software
Experience
Google September 2013 - Present
Oasys Design Systems February 2010 - September 2013
Atrenta January 2009 - February 2010
Cadence Design Systems 1998 - January 2009
Cross Check 1994 - 1998
Skills
Low-power Design, TCL, Logic Synthesis, C++, ATPG, EDA, SoC, ASIC, VLSI, Static Timing Analysis, DFT, Verilog, Embedded Systems, RTL coding, Semiconductors
Education
Princeton University 1990 — 1994
Ph.D.
University of Rochester 1988 — 1990
M.S.
Indian Institute of Technology, Delhi 1984 — 1988
B. Tech.
Google September 2013 - Present
Oasys Design Systems February 2010 - September 2013
Atrenta January 2009 - February 2010
Cadence Design Systems 1998 - January 2009
Cross Check 1994 - 1998
Skills
Low-power Design, TCL, Logic Synthesis, C++, ATPG, EDA, SoC, ASIC, VLSI, Static Timing Analysis, DFT, Verilog, Embedded Systems, RTL coding, Semiconductors
Education
Princeton University 1990 — 1994
Ph.D.
University of Rochester 1988 — 1990
M.S.
Indian Institute of Technology, Delhi 1984 — 1988
B. Tech.
Pierre-Xavier Thomas's Cadence Design Systems Experience April 2013 - Present
Job Director of Engineering, Baseband IP Product Line at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems April 2013 - Present
Tensilica (acquired by Cadence) August 2011 - Present
IPextreme, Inc August 2005 - June 2011
SGI May 2002 - August 2005
Clearwater Networks February 2001 - April 2002
Synopsys June 1997 - February 2001
Motorola SPS February 1996 - June 1997
STM - Thomson Consumer Electronic Components (TCEC) September 1993 - February 1996
Skills
SoC, ASIC, Semiconductor IP, Project Management, Digital Signal..., Processors, IC, Semiconductors, Product Development, Team Leadership, FPGA, SystemVerilog, VHDL, Product Marketing, Product Management, System Architecture, Computer Architecture, Microprocessors, EDA, Debugging, Verilog, Logic Design, RTL design, Static Timing Analysis, Physical Design, VLSI, ARM, Hardware Architecture, Functional Verification, Timing Closure, Embedded Systems, Integrated Circuit..., RTL Design
Education
Institut national polytechnique de Grenoble
MS
Universite de Technologie de Compiegne
Engineering Diploma
Cadence Design Systems April 2013 - Present
Tensilica (acquired by Cadence) August 2011 - Present
IPextreme, Inc August 2005 - June 2011
SGI May 2002 - August 2005
Clearwater Networks February 2001 - April 2002
Synopsys June 1997 - February 2001
Motorola SPS February 1996 - June 1997
STM - Thomson Consumer Electronic Components (TCEC) September 1993 - February 1996
Skills
SoC, ASIC, Semiconductor IP, Project Management, Digital Signal..., Processors, IC, Semiconductors, Product Development, Team Leadership, FPGA, SystemVerilog, VHDL, Product Marketing, Product Management, System Architecture, Computer Architecture, Microprocessors, EDA, Debugging, Verilog, Logic Design, RTL design, Static Timing Analysis, Physical Design, VLSI, ARM, Hardware Architecture, Functional Verification, Timing Closure, Embedded Systems, Integrated Circuit..., RTL Design
Education
Institut national polytechnique de Grenoble
MS
Universite de Technologie de Compiegne
Engineering Diploma
Himanshu Sanghavi's Cadence Design Systems Experience June 2014 - Present
Job Group Director, Tensilica R&D at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems June 2014 - Present
Tensilica October 2008 - Present
Tensilica October 2007 - September 2008
Tensilica Inc March 2000 - September 2007
Mediamatics Inc July 1995 - March 2000
Intel Corp. September 1991 - July 1995
Skills
Engineering Management, Computer Architecture, Computer Hardware, SoC, ASIC, Digital Signal..., Customer Engagement, Digital Video, Chip Architecture, Digital Audio, Debugging, EDA, VLSI, Functional Verification, Semiconductors, H.264, Processors, IC, RTL design, Verilog, Embedded Systems, FPGA, Microprocessors, System Architecture, Embedded Software, Technical Product..., Semiconductor Industry, Static Timing Analysis, Hardware Architecture, Technical Leadership, Technical Product..., Timing Closure, Algorithms, Physical Design, RTL Design, Firmware
Education
University of Texas at Austin 1990 — 1991
MS, Electrical & Computer Engineering
Indian Institute of Technology, Bombay 1985 — 1989
B.Tech, Electrical Engineering
Cadence Design Systems June 2014 - Present
Tensilica October 2008 - Present
Tensilica October 2007 - September 2008
Tensilica Inc March 2000 - September 2007
Mediamatics Inc July 1995 - March 2000
Intel Corp. September 1991 - July 1995
Skills
Engineering Management, Computer Architecture, Computer Hardware, SoC, ASIC, Digital Signal..., Customer Engagement, Digital Video, Chip Architecture, Digital Audio, Debugging, EDA, VLSI, Functional Verification, Semiconductors, H.264, Processors, IC, RTL design, Verilog, Embedded Systems, FPGA, Microprocessors, System Architecture, Embedded Software, Technical Product..., Semiconductor Industry, Static Timing Analysis, Hardware Architecture, Technical Leadership, Technical Product..., Timing Closure, Algorithms, Physical Design, RTL Design, Firmware
Education
University of Texas at Austin 1990 — 1991
MS, Electrical & Computer Engineering
Indian Institute of Technology, Bombay 1985 — 1989
B.Tech, Electrical Engineering
Charu Shah, Chartered Accountant's Cadence Design Systems Experience March 1998 - August 2002
Job Finance & Accounting Professional
Industry Accounting
Experience
Independent Consulting - Finance January 2010 - Present
VeriFone Inc. November 2007 - January 2010
VeriSign June 2005 - November 2007
Various companies in Bay Area January 2003 - June 2005
Cadence Design Systems March 1998 - August 2002
Infinity Financial Technology 1996 - 1998
Education
Institute of Chartered Accountants in England and Wales 1974 — 2007
FCA
Independent Consulting - Finance January 2010 - Present
VeriFone Inc. November 2007 - January 2010
VeriSign June 2005 - November 2007
Various companies in Bay Area January 2003 - June 2005
Cadence Design Systems March 1998 - August 2002
Infinity Financial Technology 1996 - 1998
Education
Institute of Chartered Accountants in England and Wales 1974 — 2007
FCA
Kumar Ramanathan's Cadence Design Systems Experience 1995 - 1999
Job CTO, Relona
Industry Computer Software
Experience
Relona November 2005 - Present
Transform Pharmaceuticals October 2001 - September 2005
Empirix March 2001 - July 2001
Transform Pharmaceuticals September 2000 - February 2001
iCOMS December 1999 - August 2000
Cadence Design Systems 1995 - 1999
Software Emancipation Technology 1995 - 1995
Skills
Telecommunications, Software Development, Start-ups, Strategy, Agile Methodologies, Product Management, C#, XML, Java, Python, Management, Distributed Systems, Web Services
Education
University of Massachusetts, Amherst 1992 — 1994
MS, Computer Science
Indian Institute of Technology, Madras 1988 — 1992
BTech, Electronics
Relona November 2005 - Present
Transform Pharmaceuticals October 2001 - September 2005
Empirix March 2001 - July 2001
Transform Pharmaceuticals September 2000 - February 2001
iCOMS December 1999 - August 2000
Cadence Design Systems 1995 - 1999
Software Emancipation Technology 1995 - 1995
Skills
Telecommunications, Software Development, Start-ups, Strategy, Agile Methodologies, Product Management, C#, XML, Java, Python, Management, Distributed Systems, Web Services
Education
University of Massachusetts, Amherst 1992 — 1994
MS, Computer Science
Indian Institute of Technology, Madras 1988 — 1992
BTech, Electronics
Vikas Khandelwal's Cadence Design Systems Experience December 2010 - March 2012
Job ASIC Verification Manager at HGST, a Western Digital company
Industry Computer Networking
Experience
HGST, a Western Digital company January 2015 - Present
Skyera Inc. (Acquired by HGST, a Western Digital Company) June 2013 - December 2014
Skyera Inc March 2012 - June 2013
Cadence Design Systems December 2010 - March 2012
Cisco Systems November 2009 - November 2010
Sandforce Inc September 2007 - November 2009
cisco sytems February 2002 - September 2007
San Valley Systems, a SAN Startup June 2001 - February 2002
3Com Corporation March 1999 - June 2001
Comit Systems 1998 - 1999
Skills
AMBA AHB, SATA, ASIC
Education
IIT Kanpur 1992 — 1996
BachelorsElectrical engineering
HGST, a Western Digital company January 2015 - Present
Skyera Inc. (Acquired by HGST, a Western Digital Company) June 2013 - December 2014
Skyera Inc March 2012 - June 2013
Cadence Design Systems December 2010 - March 2012
Cisco Systems November 2009 - November 2010
Sandforce Inc September 2007 - November 2009
cisco sytems February 2002 - September 2007
San Valley Systems, a SAN Startup June 2001 - February 2002
3Com Corporation March 1999 - June 2001
Comit Systems 1998 - 1999
Skills
AMBA AHB, SATA, ASIC
Education
IIT Kanpur 1992 — 1996
BachelorsElectrical engineering
Abhijit Maji's Cadence Design Systems Experience March 2014 - Present
Job Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems March 2014 - Present
Synopsys July 2012 - Present
Synopsys April 2012 - June 2012
Magma Design Automation Inc. February 2007 - March 2012
Magma Design Automation November 1999 - February 2007
Interra 1997 - 1999
Skills
EDA, Timing, Formal Verification, Timing Closure, Logic Synthesis, TCL, ASIC, VLSI
Education
Indian Institute of Technology, Kanpur
B. Tech.
University of California, Santa Cruz
MS
Cadence Design Systems March 2014 - Present
Synopsys July 2012 - Present
Synopsys April 2012 - June 2012
Magma Design Automation Inc. February 2007 - March 2012
Magma Design Automation November 1999 - February 2007
Interra 1997 - 1999
Skills
EDA, Timing, Formal Verification, Timing Closure, Logic Synthesis, TCL, ASIC, VLSI
Education
Indian Institute of Technology, Kanpur
B. Tech.
University of California, Santa Cruz
MS
Anupam Srivastava's Cadence Design Systems Experience August 1996 - November 1997
Job Managing Director and Member of the Investment Committee at Intel Capital
Industry Venture Capital & Private Equity
Experience
Intel Corporation September 2012 - Present
Intel Capital August 2006 - October 2012
Intel April 2005 - August 2006
First Sight Computing January 2003 - April 2005
Intel March 1999 - January 2003
Cadence Design Systems August 1996 - November 1997
Intel Corporation August 1993 - August 1996
Amdahl August 1990 - August 1993
Skills
Venture Capital, Mergers, Microprocessors, Client/server, Corporate Development, M&A experience, IPO, Private Equity, Start-ups, Strategic Partnerships, Entrepreneurship, Financial Modeling, Joint Ventures, Due Diligence
Education
INSEAD 1998 — 1998
MBA, General Management
Michigan State University 1988 — 1990
MS, Electrical Engineering
Michigan State University 1985 — 1988
B.S., Computer Science
Intel Corporation September 2012 - Present
Intel Capital August 2006 - October 2012
Intel April 2005 - August 2006
First Sight Computing January 2003 - April 2005
Intel March 1999 - January 2003
Cadence Design Systems August 1996 - November 1997
Intel Corporation August 1993 - August 1996
Amdahl August 1990 - August 1993
Skills
Venture Capital, Mergers, Microprocessors, Client/server, Corporate Development, M&A experience, IPO, Private Equity, Start-ups, Strategic Partnerships, Entrepreneurship, Financial Modeling, Joint Ventures, Due Diligence
Education
INSEAD 1998 — 1998
MBA, General Management
Michigan State University 1988 — 1990
MS, Electrical Engineering
Michigan State University 1985 — 1988
B.S., Computer Science
Mike Faster's Cadence Design Systems Experience 1991 - 1994
Job President & CIO at Coyote Creek Consulting
Industry Information Technology and Services
Experience
Coyote Creek Consulting 1998 - Present
WorldChain 2001 - 2001
Turbo Coverage 2001 - 2001
Spin Circuit 2000 - 2000
Ventro(Chemdex) 1999 - 2000
Ariba 1999 - 2000
Komag 1994 - 1998
Cadence Design Systems 1991 - 1994
Apple Computer 1983 - 1991
Fairchild Semiconductor 1983 - 1983
Skills
VMware, IT Management, Active Directory, SharePoint, Citrix, IT Strategy, Business Planning, Microsoft Exchange, Cisco Technologies, Microsoft Technologies, Servers, Cloud Computing, JIRA, Leadership, Virtualization, Technical Leadership, Management, Anything, Data Center, SaaS, Linux, Networking, IT Operations, Managed Services, Project Management, Disaster Recovery, Windows Server, Information Technology, Enterprise Software
Education
Indiana University of Pennsylvania 1977 — 1981
BS, Management
Coyote Creek Consulting 1998 - Present
WorldChain 2001 - 2001
Turbo Coverage 2001 - 2001
Spin Circuit 2000 - 2000
Ventro(Chemdex) 1999 - 2000
Ariba 1999 - 2000
Komag 1994 - 1998
Cadence Design Systems 1991 - 1994
Apple Computer 1983 - 1991
Fairchild Semiconductor 1983 - 1983
Skills
VMware, IT Management, Active Directory, SharePoint, Citrix, IT Strategy, Business Planning, Microsoft Exchange, Cisco Technologies, Microsoft Technologies, Servers, Cloud Computing, JIRA, Leadership, Virtualization, Technical Leadership, Management, Anything, Data Center, SaaS, Linux, Networking, IT Operations, Managed Services, Project Management, Disaster Recovery, Windows Server, Information Technology, Enterprise Software
Education
Indiana University of Pennsylvania 1977 — 1981
BS, Management
Ashish Guttedar's Cadence Design Systems Experience August 2006 - July 2009
Job Product Management & Business Development | SaaS & IoT
Industry Electrical/Electronic Manufacturing
Experience
Fluke Corporation, a Danaher Company June 2015 - Present
Philips March 2013 - April 2015
Philips September 2010 - February 2013
Cadence Design Systems August 2006 - July 2009
Analog Devices June 2002 - July 2006
Citicorp Overseas Software Ltd. August 1998 - August 2000
Education
INSEAD 2009 — 2010
M.B.A
Rutgers University 2000 — 2002
MS
National Institute of Technology Karnataka 1994 — 1998
BE
Fluke Corporation, a Danaher Company June 2015 - Present
Philips March 2013 - April 2015
Philips September 2010 - February 2013
Cadence Design Systems August 2006 - July 2009
Analog Devices June 2002 - July 2006
Citicorp Overseas Software Ltd. August 1998 - August 2000
Education
INSEAD 2009 — 2010
M.B.A
Rutgers University 2000 — 2002
MS
National Institute of Technology Karnataka 1994 — 1998
BE
Philippe Hurat's Cadence Design Systems Experience 2013 - Present
Job
Industry Computer Software
Experience
Cadence Design Systems 2013 - Present
Cadence Design Systems 2007 - Present
Skills
SoC, Analog, ASIC, Electronics, Product Marketing, Product Lifecycle..., EDA, Product Management, IC, Semiconductors, Software Design, Software Development, Marketing Strategy, Embedded Systems, Algorithms, Engineering Management, Physical Design, Marketing, CMOS, VLSI, Semiconductor Industry
Education
Institut polytechnique de Grenoble
Cadence Design Systems 2013 - Present
Cadence Design Systems 2007 - Present
Skills
SoC, Analog, ASIC, Electronics, Product Marketing, Product Lifecycle..., EDA, Product Management, IC, Semiconductors, Software Design, Software Development, Marketing Strategy, Embedded Systems, Algorithms, Engineering Management, Physical Design, Marketing, CMOS, VLSI, Semiconductor Industry
Education
Institut polytechnique de Grenoble
Nitin Raut's Cadence Design Systems Experience May 2008 - November 2010
Job Software Engineer at Google
Industry Computer Software
Experience
Google January 2014 - Present
Google India October 2012 - January 2014
Xilinx October 2010 - October 2012
Cadence Design Systems May 2008 - November 2010
Synopsys November 2005 - April 2008
Softjin Technolies Pvt Ltd February 2002 - November 2005
Skills
EDA, Automation, Algorithms, Data Structures, FPGA, Xilinx, Compilers, C++, C, Design Patterns, Perl, Unix, Linux, Shell Scripting, Programming, STL, Debugging
Education
Indian Institute of Technology, Bombay 2000 — 2002
M Tech, Computer Science
Visvesvaraya National Institute of Technology 1996 — 2000
B.E, Computer Science
Google January 2014 - Present
Google India October 2012 - January 2014
Xilinx October 2010 - October 2012
Cadence Design Systems May 2008 - November 2010
Synopsys November 2005 - April 2008
Softjin Technolies Pvt Ltd February 2002 - November 2005
Skills
EDA, Automation, Algorithms, Data Structures, FPGA, Xilinx, Compilers, C++, C, Design Patterns, Perl, Unix, Linux, Shell Scripting, Programming, STL, Debugging
Education
Indian Institute of Technology, Bombay 2000 — 2002
M Tech, Computer Science
Visvesvaraya National Institute of Technology 1996 — 2000
B.E, Computer Science
Grace Fang's Cadence Design Systems Experience January 2001 - February 2004
Job Finance Director, CPA & MST
Industry Electrical/Electronic Manufacturing
Experience
Mirion Technologies, Inc. July 2014 - Present
Thermo Fisher Scientific March 2009 - July 2014
Stanford Graduate School of Business March 2005 - February 2009
Cisco March 2004 - March 2005
Cadence Design Systems January 2001 - February 2004
Deloitte & Touche January 1998 - January 2001
Skills
Finance, Budgets, Financial Reporting, Tax, Sarbanes-Oxley Act, Accounting, Financial Analysis, Forecasting, US GAAP, Managerial Finance, Internal Controls, Revenue Recognition, Financial Modeling, Cost Accounting, GAAP, Variance Analysis, Hyperion Enterprise, Financial Accounting, Consolidation, Financial Audits
Education
San Jose State University 1998 — 2000
MS, Taxation
Illinois Wesleyan University 1995 — 1997
B.A., Public Accounting, Summa Cum Laude
Mirion Technologies, Inc. July 2014 - Present
Thermo Fisher Scientific March 2009 - July 2014
Stanford Graduate School of Business March 2005 - February 2009
Cisco March 2004 - March 2005
Cadence Design Systems January 2001 - February 2004
Deloitte & Touche January 1998 - January 2001
Skills
Finance, Budgets, Financial Reporting, Tax, Sarbanes-Oxley Act, Accounting, Financial Analysis, Forecasting, US GAAP, Managerial Finance, Internal Controls, Revenue Recognition, Financial Modeling, Cost Accounting, GAAP, Variance Analysis, Hyperion Enterprise, Financial Accounting, Consolidation, Financial Audits
Education
San Jose State University 1998 — 2000
MS, Taxation
Illinois Wesleyan University 1995 — 1997
B.A., Public Accounting, Summa Cum Laude
Saurav Gorai's Cadence Design Systems Experience June 2014 - July 2014
Job SoC Formal Verification Engineer at Apple
Industry Semiconductors
Experience
Apple July 2014 - Present
Cadence Design Systems June 2014 - July 2014
Jasper Design Automation January 2012 - June 2014
Jasper Design Automation May 2010 - December 2011
Mentor Graphics January 2008 - May 2010
Mentor Graphics April 2006 - December 2007
Texas Instruments March 2005 - April 2006
Synopsys June 2004 - February 2005
Skills
Functional Verification, EDA, Formal Verification, SystemVerilog, Verilog, SoC, RTL design, TCL, Algorithms, Simulations, Logic Synthesis, C++, Debugging, VLSI, Semiconductors, RTL Design, ASIC
Education
Indian Institute of Technology, Kharagpur 2000 — 2004
Bachelor of Technology (Honours), Electronics & Electrical Communication Engineering with Minor in Computer Science & Engineering
Apple July 2014 - Present
Cadence Design Systems June 2014 - July 2014
Jasper Design Automation January 2012 - June 2014
Jasper Design Automation May 2010 - December 2011
Mentor Graphics January 2008 - May 2010
Mentor Graphics April 2006 - December 2007
Texas Instruments March 2005 - April 2006
Synopsys June 2004 - February 2005
Skills
Functional Verification, EDA, Formal Verification, SystemVerilog, Verilog, SoC, RTL design, TCL, Algorithms, Simulations, Logic Synthesis, C++, Debugging, VLSI, Semiconductors, RTL Design, ASIC
Education
Indian Institute of Technology, Kharagpur 2000 — 2004
Bachelor of Technology (Honours), Electronics & Electrical Communication Engineering with Minor in Computer Science & Engineering
Mohit Mittal's Cadence Design Systems Experience June 2010 - May 2011
Job ASIC RTL Designer
Industry Semiconductors
Experience
Broadcom May 2011 - Present
Cadence Design Systems June 2010 - May 2011
Denali October 2006 - May 2011
Ittiam Systems Pvt Ltd July 2005 - October 2006
Skills
Verilog, ASIC, Static Timing Analysis, RTL design, Logic Synthesis, Primetime, Integrated Circuit..., SystemVerilog, FPGA, Altera, AMBA AHB, Xilinx, USB, Algorithms, RTL Design, SoC
Education
Indian Institute of Technology, Madras 2001 — 2005
Broadcom May 2011 - Present
Cadence Design Systems June 2010 - May 2011
Denali October 2006 - May 2011
Ittiam Systems Pvt Ltd July 2005 - October 2006
Skills
Verilog, ASIC, Static Timing Analysis, RTL design, Logic Synthesis, Primetime, Integrated Circuit..., SystemVerilog, FPGA, Altera, AMBA AHB, Xilinx, USB, Algorithms, RTL Design, SoC
Education
Indian Institute of Technology, Madras 2001 — 2005
John Konglathu's Cadence Design Systems Experience 1996 - 1997
Job Software Engineer at Google
Industry Computer Software
Experience
Google April 2008 - Present
TenFold Corporation 1999 - April 2008
Cadence Design Systems 1996 - 1997
Skills
Distributed Systems, Software Development, C, Enterprise Software, Cloud Computing, Hadoop, MapReduce, C++, SOA, XML, Scalability, Web Services, Enterprise Architecture, Big Data
Education
University of North Carolina at Chapel Hill 1997 — 1999
MS, Computer Science
Indian Institute of Technology, Kharagpur 1992 — 1996
B Tech, Computer Science & Engineering
Google April 2008 - Present
TenFold Corporation 1999 - April 2008
Cadence Design Systems 1996 - 1997
Skills
Distributed Systems, Software Development, C, Enterprise Software, Cloud Computing, Hadoop, MapReduce, C++, SOA, XML, Scalability, Web Services, Enterprise Architecture, Big Data
Education
University of North Carolina at Chapel Hill 1997 — 1999
MS, Computer Science
Indian Institute of Technology, Kharagpur 1992 — 1996
B Tech, Computer Science & Engineering
Vijay Pawar's Cadence Design Systems Experience July 2013 - Present
Job Principal Design Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2013 - Present
Tensilica April 2011 - June 2013
Tensilica April 2010 - March 2011
Tensilica April 2008 - March 2010
LSI, an Avago Technologies Company July 2005 - March 2008
Skills
ARM, Digital Signal..., Embedded Software, Firmware, SoC, RTOS, Debugging, Codecs
Education
Indian Institute of Technology, Kanpur 2003 — 2005
Cadence Design Systems July 2013 - Present
Tensilica April 2011 - June 2013
Tensilica April 2010 - March 2011
Tensilica April 2008 - March 2010
LSI, an Avago Technologies Company July 2005 - March 2008
Skills
ARM, Digital Signal..., Embedded Software, Firmware, SoC, RTOS, Debugging, Codecs
Education
Indian Institute of Technology, Kanpur 2003 — 2005
Pierce Keating's Cadence Design Systems Experience July 1997 - January 1999
Job FPGA Development Engineer at Kymeta Corporation
Industry Telecommunications
Experience
Kymeta Corporation March 2014 - Present
Sonosite September 2010 - February 2014
Agilent Technologies September 2010 - September 2011
RadioFrame Networks July 2000 - May 2009
Aptix March 1999 - June 2000
Cadence Design Systems July 1997 - January 1999
Motorola, Inc 1990 - 1997
Skills
FPGA, ASIC, Wireless, Embedded Software, Embedded Systems, Linux, Digital Signal..., VxWorks, RF, PCB design, Unix, Firmware, Debugging, RTOS, Device Drivers, Hardware Architecture, Verilog
Education
DeVry Institute of Technology
BSEET
Illinois Institute of Technology
Master of Science (MS), Electrical, Electronics and Communications Engineering
Kymeta Corporation March 2014 - Present
Sonosite September 2010 - February 2014
Agilent Technologies September 2010 - September 2011
RadioFrame Networks July 2000 - May 2009
Aptix March 1999 - June 2000
Cadence Design Systems July 1997 - January 1999
Motorola, Inc 1990 - 1997
Skills
FPGA, ASIC, Wireless, Embedded Software, Embedded Systems, Linux, Digital Signal..., VxWorks, RF, PCB design, Unix, Firmware, Debugging, RTOS, Device Drivers, Hardware Architecture, Verilog
Education
DeVry Institute of Technology
BSEET
Illinois Institute of Technology
Master of Science (MS), Electrical, Electronics and Communications Engineering
Samar Abdi's Cadence Design Systems Experience 1998 - 2000
Job Associate Professor at Concordia University
Industry Higher Education
Experience
Concordia University August 2009 - Present
UCI December 2005 - June 2009
Cadence Design Systems 1998 - 2000
Skills
Algorithms, Computer Architecture, Computer Science, Embedded Systems, Unix, LaTeX, Simulations, Matlab
Education
UCI 2000 — 2005
Ph.D., Computer Science
University of California, Irvine 2000 — 2005
Doctor of Philosophy (PhD), Computer Science
Indian Institute of Technology, Kharagpur 1994 — 1998
B.Tech, Computer Science
Concordia University August 2009 - Present
UCI December 2005 - June 2009
Cadence Design Systems 1998 - 2000
Skills
Algorithms, Computer Architecture, Computer Science, Embedded Systems, Unix, LaTeX, Simulations, Matlab
Education
UCI 2000 — 2005
Ph.D., Computer Science
University of California, Irvine 2000 — 2005
Doctor of Philosophy (PhD), Computer Science
Indian Institute of Technology, Kharagpur 1994 — 1998
B.Tech, Computer Science
Lalgudi Kannan's Cadence Design Systems Experience 1990 - 1994
Job Senior Director of Engineering at A10 Networks
Industry Internet
Experience
A10 Networks September 2007 - Present
Yahoo September 1998 - September 2007
Escalade Corp 1994 - 1998
Cadence Design Systems 1990 - 1994
CDOT, New Delhi, India 1985 - 1985
Skills
Scalability, Distributed Systems, Perl, Cloud Computing, Algorithms, Linux, Software Engineering, SaaS, Agile Methodologies, C, C++, High Performance..., Embedded Systems, TCP/IP, Information Retrieval, Unix, CVS, TCL, Multithreading
Education
Indian Institute of Technology, Kharagpur 1979 — 1984
B.Tech.(Hons)
University of Cincinnati 1985 — 1990
Ph.D.
A10 Networks September 2007 - Present
Yahoo September 1998 - September 2007
Escalade Corp 1994 - 1998
Cadence Design Systems 1990 - 1994
CDOT, New Delhi, India 1985 - 1985
Skills
Scalability, Distributed Systems, Perl, Cloud Computing, Algorithms, Linux, Software Engineering, SaaS, Agile Methodologies, C, C++, High Performance..., Embedded Systems, TCP/IP, Information Retrieval, Unix, CVS, TCL, Multithreading
Education
Indian Institute of Technology, Kharagpur 1979 — 1984
B.Tech.(Hons)
University of Cincinnati 1985 — 1990
Ph.D.
Dhananjay Griyage's Cadence Design Systems Experience 2001 - May 2014
Job Architect at Mentor Graphics
Industry Semiconductors
Experience
cadence ArchitectMentor GraphicsJune 2014 - Present
Cadence Design Systems 2001 - May 2014
Cadence Design Systems 2001 - 2014
Motorola Semiconductor 1997 - 2001
Motorola India 1997 - 2001
Motorola India Electronics Ltd 1997 - 2001
motorola 1997 - 2001
Skills
ASIC, EDA, SoC, Debugging, Perl, Verilog, Algorithms, TCL, Static Timing Analysis, Software Development
Education
Indian Institute of Technology, Kharagpur 1994 — 1996
M.Tech., Integrated Circuits and System Engineering
Indian Institute of Technology, Roorkee 1988 — 1992
Electrical and Electronics Engineering
cadence ArchitectMentor GraphicsJune 2014 - Present
Cadence Design Systems 2001 - May 2014
Cadence Design Systems 2001 - 2014
Motorola Semiconductor 1997 - 2001
Motorola India 1997 - 2001
Motorola India Electronics Ltd 1997 - 2001
motorola 1997 - 2001
Skills
ASIC, EDA, SoC, Debugging, Perl, Verilog, Algorithms, TCL, Static Timing Analysis, Software Development
Education
Indian Institute of Technology, Kharagpur 1994 — 1996
M.Tech., Integrated Circuits and System Engineering
Indian Institute of Technology, Roorkee 1988 — 1992
Electrical and Electronics Engineering
Vijay Sundararajan's Cadence Design Systems Experience 1998 - 1998
Job Systems Engineering Embedded WLAN at Broadcom Corp
Industry Telecommunications
Experience
Broadcom Corp March 2010 - Present
Texas Instruments April 2000 - February 2010
Department of Electrical and Computer Engineering, University of Minnesota 1994 - 2000
Cadence Design Systems 1998 - 1998
Skills
Baseband, DSP, PHY, SoC, ASIC, Digital Signal...
Education
University of Minnesota-Twin Cities 1994 — 2000
PhD, EE
Indian Institute of Technology, Delhi 1989 — 1993
BTECH, EE
Broadcom Corp March 2010 - Present
Texas Instruments April 2000 - February 2010
Department of Electrical and Computer Engineering, University of Minnesota 1994 - 2000
Cadence Design Systems 1998 - 1998
Skills
Baseband, DSP, PHY, SoC, ASIC, Digital Signal...
Education
University of Minnesota-Twin Cities 1994 — 2000
PhD, EE
Indian Institute of Technology, Delhi 1989 — 1993
BTECH, EE
Prakash Arunachalam's Cadence Design Systems Experience 2005 - 2009
Job Data Scientist at Quid
Industry Information Technology and Services
Experience
Quid August 2014 - Present
Epilepsy Foundation of Northern California (Epilepsy Norcal) 2014 - 2015
eBay 2010 - August 2014
Cadence Design Systems 2005 - 2009
Intel Corporation 1996 - 2005
Skills
Data Mining, Hadoop, Machine Learning, Algorithms, Artificial Intelligence, MapReduce, Big Data, Perl, Python, C++, Software Development, Scalability, Natural Language..., Information Retrieval, Neural Networks
Education
The University of Texas at Austin 1990 — 1996
PhD, Computer Engineering
Indian Institute of Technology, Kharagpur 1986 — 1990
B.Tech, Electrical Engineering
Quid August 2014 - Present
Epilepsy Foundation of Northern California (Epilepsy Norcal) 2014 - 2015
eBay 2010 - August 2014
Cadence Design Systems 2005 - 2009
Intel Corporation 1996 - 2005
Skills
Data Mining, Hadoop, Machine Learning, Algorithms, Artificial Intelligence, MapReduce, Big Data, Perl, Python, C++, Software Development, Scalability, Natural Language..., Information Retrieval, Neural Networks
Education
The University of Texas at Austin 1990 — 1996
PhD, Computer Engineering
Indian Institute of Technology, Kharagpur 1986 — 1990
B.Tech, Electrical Engineering
Stephanie Pusch's Cadence Design Systems Experience 1997 - 2003
Job VP of sales and marketing at Trusted Semiconductor Solutions
Industry Semiconductors
Experience
Trusted Semiconductor Solutions 2006 - Present
Honeywell 2003 - 2006
Cadence Design Systems 1997 - 2003
Motorola 1993 - 1997
Skills
Semiconductors, Analog, Electronics, IC, Wireless, ASIC, Cross-functional Team..., Embedded Systems, Product Management, Product Marketing, Engineering Management
Education
Illinois Institute of Technology 1993 — 1996
MS, Electrical Engineering
University of Wisconsin-Madison 1989 — 1993
BS, Electrical Engineering
Trusted Semiconductor Solutions 2006 - Present
Honeywell 2003 - 2006
Cadence Design Systems 1997 - 2003
Motorola 1993 - 1997
Skills
Semiconductors, Analog, Electronics, IC, Wireless, ASIC, Cross-functional Team..., Embedded Systems, Product Management, Product Marketing, Engineering Management
Education
Illinois Institute of Technology 1993 — 1996
MS, Electrical Engineering
University of Wisconsin-Madison 1989 — 1993
BS, Electrical Engineering
Pushkar Patwardhan's Cadence Design Systems Experience July 2014 - Present
Job Design Engineering Architect at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2014 - Present
Cadence Design Systems / Tensilica April 2013 - Present
Tensilica November 2011 - April 2013
Tensilica October 2009 - December 2011
Tensilica India 2006 - November 2009
NVIDIA 2006 - 2006
Sasken 2005 - 2006
Cirrus Logic 1998 - 2005
Hughes Network Systems 1997 - 1998
Skills
DSP, Signal Processing, Digital Signal..., SoC, ASIC, Processors, Audio Processing, MPEG, Mixed Signal, Embedded Software
Education
Indian Institute of Technology, Bombay 2003 — 2007
Ph. D., Electrical Engineering (Signal Processing)
Indian Institute of Technology, Bombay 1995 — 1997
M. Tech, Electrical Engineering (Signal Processing)
University of Mumbai 1991 — 1995
B. E., Electronics Engineering
Cadence Design Systems July 2014 - Present
Cadence Design Systems / Tensilica April 2013 - Present
Tensilica November 2011 - April 2013
Tensilica October 2009 - December 2011
Tensilica India 2006 - November 2009
NVIDIA 2006 - 2006
Sasken 2005 - 2006
Cirrus Logic 1998 - 2005
Hughes Network Systems 1997 - 1998
Skills
DSP, Signal Processing, Digital Signal..., SoC, ASIC, Processors, Audio Processing, MPEG, Mixed Signal, Embedded Software
Education
Indian Institute of Technology, Bombay 2003 — 2007
Ph. D., Electrical Engineering (Signal Processing)
Indian Institute of Technology, Bombay 1995 — 1997
M. Tech, Electrical Engineering (Signal Processing)
University of Mumbai 1991 — 1995
B. E., Electronics Engineering
Hemanga Das's Cadence Design Systems Experience July 1995 - July 1997
Job Senior Software Engineer at MobileIron
Industry Computer Software
Experience
MobileIron Enterprise Mobile ITPrincipal Hardware EngineerOracle CorporationJanuary 2010 - August 2012
Sun Microsystems October 2004 - December 2009
Denali Software November 1999 - July 2004
Cadence Design Systems July 1995 - July 1997
Skills
iOS development, Objective-C, C++, Verilog, EDA, Algorithms, Design Patterns, OOP, Low-power Design, TCL, Perl, Semiconductor Industry, Debugging, ASIC, Power Analysis, Embedded Systems, C, FPGA, Multithreading, SoC, Shell Scripting, Semiconductors
Education
Indian Institute of Technology, Kharagpur 1991 — 1995
Bachelor of Technology (B.Tech.), Computer Science & Engineering
MobileIron Enterprise Mobile ITPrincipal Hardware EngineerOracle CorporationJanuary 2010 - August 2012
Sun Microsystems October 2004 - December 2009
Denali Software November 1999 - July 2004
Cadence Design Systems July 1995 - July 1997
Skills
iOS development, Objective-C, C++, Verilog, EDA, Algorithms, Design Patterns, OOP, Low-power Design, TCL, Perl, Semiconductor Industry, Debugging, ASIC, Power Analysis, Embedded Systems, C, FPGA, Multithreading, SoC, Shell Scripting, Semiconductors
Education
Indian Institute of Technology, Kharagpur 1991 — 1995
Bachelor of Technology (B.Tech.), Computer Science & Engineering
Anish Malhotra's Cadence Design Systems Experience 2002 - 2006
Job Software Engineer at Google
Industry Computer Software
Experience
Google 2013 - Present
Synopsys 2007 - 2013
Mentor Graphics 2006 - 2007
Cadence Design Systems 2002 - 2006
@HDL Inc 2001 - 2002
Cadence Design Systems 1996 - 2001
Skills
C/C++ STL, Data structures, Algorithm Optimization, Algorithms, Java
Education
Indian Institute of Technology (Banaras Hindu University), Varanasi
Google 2013 - Present
Synopsys 2007 - 2013
Mentor Graphics 2006 - 2007
Cadence Design Systems 2002 - 2006
@HDL Inc 2001 - 2002
Cadence Design Systems 1996 - 2001
Skills
C/C++ STL, Data structures, Algorithm Optimization, Algorithms, Java
Education
Indian Institute of Technology (Banaras Hindu University), Varanasi
Shrinivasan Jaganathan's Cadence Design Systems Experience June 2013 - Present
Job Design Engineering Director at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems June 2013 - Present
Cosmic Circuits October 2012 - May 2013
Texas Instruments April 2010 - September 2012
Texas Instruments, Inc. August 2002 - March 2010
GTRAN 2000 - 2002
UC Santa Barbara 1996 - 2000
Skills
Analog, RF Systems, RF ICs, Mixed-Signal IC Design, Mixed Signal, IC, PLL, Integrated Circuit..., RF, Silicon, Power Supplies, RF design, Test Engineering, Analog Circuit Design, CMOS
Education
University of California, Santa Barbara 1996 — 2000
MS, PhD, Electrical Engineering
Indian Institute of Technology, Bombay 1989 — 1993
B. Tech., Electrical Engineering
Kendriya Vidyalaya, Indore
Cadence Design Systems June 2013 - Present
Cosmic Circuits October 2012 - May 2013
Texas Instruments April 2010 - September 2012
Texas Instruments, Inc. August 2002 - March 2010
GTRAN 2000 - 2002
UC Santa Barbara 1996 - 2000
Skills
Analog, RF Systems, RF ICs, Mixed-Signal IC Design, Mixed Signal, IC, PLL, Integrated Circuit..., RF, Silicon, Power Supplies, RF design, Test Engineering, Analog Circuit Design, CMOS
Education
University of California, Santa Barbara 1996 — 2000
MS, PhD, Electrical Engineering
Indian Institute of Technology, Bombay 1989 — 1993
B. Tech., Electrical Engineering
Kendriya Vidyalaya, Indore
Venkat Gokavarapu's Cadence Design Systems Experience February 2007 - November 2007
Job Owner, Maior technology Group
Industry Information Technology and Services
Experience
Maui Jim January 2014 - Present
Maior Technology Group LLC July 2006 - Present
Maui Jim 2014 - 2014
Beam Global Spirits & Wine June 2009 - November 2013
Motorola January 2008 - October 2008
Cadence Design Systems February 2007 - November 2007
Caterpillar Inc. November 2003 - July 2004
Hewlett-Packard March 2003 - October 2003
Chicago Kent College of Law 2001 - 2002
Skills
Business Process, SAP, Requirements Analysis, SAP ERP, Business Objects, SAP Netweaver, SAP BW, SAP R/3, SAP Implementation, SAP SRM, SAP BI, ERP, Business Intelligence, ABAP, SAP BPC, SD, Business Process Design, Data Migration
Education
Gowtham
Illinois Institute of Technology
Vasavi college of engineering
Maui Jim January 2014 - Present
Maior Technology Group LLC July 2006 - Present
Maui Jim 2014 - 2014
Beam Global Spirits & Wine June 2009 - November 2013
Motorola January 2008 - October 2008
Cadence Design Systems February 2007 - November 2007
Caterpillar Inc. November 2003 - July 2004
Hewlett-Packard March 2003 - October 2003
Chicago Kent College of Law 2001 - 2002
Skills
Business Process, SAP, Requirements Analysis, SAP ERP, Business Objects, SAP Netweaver, SAP BW, SAP R/3, SAP Implementation, SAP SRM, SAP BI, ERP, Business Intelligence, ABAP, SAP BPC, SD, Business Process Design, Data Migration
Education
Gowtham
Illinois Institute of Technology
Vasavi college of engineering
Padma Chivukula's Cadence Design Systems Experience July 1997 - July 2000
Job Principal Software Engineer at Hitachi Data Systems
Industry Computer Software
Experience
Hitachi Data Systems July 2013 - Present
NetApp March 2011 - June 2013
Yahoo! July 2007 - February 2011
UITS, Indiana University February 2004 - June 2007
Venux.net November 2002 - February 2003
Veritas Software Corporation May 2001 - August 2001
Cadence Design Systems July 1997 - July 2000
C-DOT Centre for Development of Telematics March 1994 - June 1997
Newgen Software Technologies July 1993 - March 1994
Skills
Languages: C, Perl,..., Platforms: Linux, Unix..., Application Servers:..., Technologies: Struts,..., Technologies: CGI,..., Tools: Jenkins, Ant,..., Version control:...
Education
Indiana University Bloomington
MS, Computer Science
Delhi Institute of Technology, Delhi
BE, Computer Engineering
Hitachi Data Systems July 2013 - Present
NetApp March 2011 - June 2013
Yahoo! July 2007 - February 2011
UITS, Indiana University February 2004 - June 2007
Venux.net November 2002 - February 2003
Veritas Software Corporation May 2001 - August 2001
Cadence Design Systems July 1997 - July 2000
C-DOT Centre for Development of Telematics March 1994 - June 1997
Newgen Software Technologies July 1993 - March 1994
Skills
Languages: C, Perl,..., Platforms: Linux, Unix..., Application Servers:..., Technologies: Struts,..., Technologies: CGI,..., Tools: Jenkins, Ant,..., Version control:...
Education
Indiana University Bloomington
MS, Computer Science
Delhi Institute of Technology, Delhi
BE, Computer Engineering
Mike Swienton's Cadence Design Systems Experience Sr. Staff Applications EngineerCadence1988 - Present
Job Core Comp Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems Sr. Staff Applications EngineerCadence1988 - Present
Valid Logic Systems 1988 - 1992
Valid Logic Systems 1988 - 1992
Education
Illinois Institute of Technology 1980 — 1984
Cadence Design Systems Sr. Staff Applications EngineerCadence1988 - Present
Valid Logic Systems 1988 - 1992
Valid Logic Systems 1988 - 1992
Education
Illinois Institute of Technology 1980 — 1984
Jayant Mittal's Cadence Design Systems Experience 1994 - 1995
Job Senior Staff Design Engineer at Xilinx Inc
Industry Semiconductors
Experience
Xilinx Inc December 2008 - Present
Xilinx Inc August 2005 - November 2008
Xilinx Inc. November 2000 - June 2005
Xiinx Inc. August 1996 - October 2000
Comit Systems, Inc July 1995 - August 1996
Cadence Design Systems 1994 - 1995
CDOT, New Delhi, India 1990 - 1994
Skills
PCIe, FPGA, Xilinx, IP, RTL design, Verilog, Perl, VHDL
Education
Santa Clara University 1997 — 2000
MS, Engineering Management
Indian Institute of Science 1986 — 1990
ME (Integrated), Electrical Communication
St. Stephens College, Delhi University, India 1983 — 1986
Bachelor of Science (BSc), Physics, 742/900 (9th position in the University)
Xilinx Inc December 2008 - Present
Xilinx Inc August 2005 - November 2008
Xilinx Inc. November 2000 - June 2005
Xiinx Inc. August 1996 - October 2000
Comit Systems, Inc July 1995 - August 1996
Cadence Design Systems 1994 - 1995
CDOT, New Delhi, India 1990 - 1994
Skills
PCIe, FPGA, Xilinx, IP, RTL design, Verilog, Perl, VHDL
Education
Santa Clara University 1997 — 2000
MS, Engineering Management
Indian Institute of Science 1986 — 1990
ME (Integrated), Electrical Communication
St. Stephens College, Delhi University, India 1983 — 1986
Bachelor of Science (BSc), Physics, 742/900 (9th position in the University)
Vijay Patri's Cadence Design Systems Experience January 2013 - Present
Job Engineer
Industry Semiconductors
Experience
Cadence Design Systems January 2013 - Present
Mentor Graphics November 2011 - December 2012
Magma Design Automation May 2010 - October 2011
Magma Design Automation January 2007 - April 2010
Intel Technology India Pvt Ltd January 2006 - December 2006
Mentor Graphics January 2005 - December 2005
Intel Technology India Pvt. Ltd. May 2004 - December 2004
Intel Technology India Pvt. Ltd. January 2003 - April 2004
Intel Technology India Pvt. Ltd. December 2001 - December 2002
Texas Instruments India Ltd. February 1998 - October 2001
Skills
Parasitic Extraction, Flow Development, DRC, LVS, CAD, Python, Physical Verification, Design for Manufacturing, Physical Design, Integrated Circuit..., EDA, Semiconductors, ASIC, VLSI, Signal Integrity
Education
Indian Institute of Technology, Delhi 1996 — 1998
M. S., Electrical Engineering
Osmania University 1991 — 1995
B.E, Electronics and Communications
Cadence Design Systems January 2013 - Present
Mentor Graphics November 2011 - December 2012
Magma Design Automation May 2010 - October 2011
Magma Design Automation January 2007 - April 2010
Intel Technology India Pvt Ltd January 2006 - December 2006
Mentor Graphics January 2005 - December 2005
Intel Technology India Pvt. Ltd. May 2004 - December 2004
Intel Technology India Pvt. Ltd. January 2003 - April 2004
Intel Technology India Pvt. Ltd. December 2001 - December 2002
Texas Instruments India Ltd. February 1998 - October 2001
Skills
Parasitic Extraction, Flow Development, DRC, LVS, CAD, Python, Physical Verification, Design for Manufacturing, Physical Design, Integrated Circuit..., EDA, Semiconductors, ASIC, VLSI, Signal Integrity
Education
Indian Institute of Technology, Delhi 1996 — 1998
M. S., Electrical Engineering
Osmania University 1991 — 1995
B.E, Electronics and Communications
Padmaja Narwankar's Cadence Design Systems Experience March 2001 - Present
Job Systems Engineer at Cadence Design Systems
Industry Information Technology and Services
Experience
Cadence Design Systems March 2001 - Present
Nike June 1999 - June 2000
Onward Technologies September 1996 - January 1999
Skills
Perl, Agile Methodologies, Requirements Analysis, Solaris, Leadership, Java Enterprise Edition, Software Project..., SDLC, Enterprise Architecture, Shell Scripting, Integration, Python, Unix Shell Scripting, SQL, XML, Cloud Computing, Software Development
Education
University of Mumbai 1992 — 1995
M.Phil, Mathematics
Indian Institute of Technology, Bombay 1990 — 1992
M.Sc., Mathematics
Cadence Design Systems March 2001 - Present
Nike June 1999 - June 2000
Onward Technologies September 1996 - January 1999
Skills
Perl, Agile Methodologies, Requirements Analysis, Solaris, Leadership, Java Enterprise Edition, Software Project..., SDLC, Enterprise Architecture, Shell Scripting, Integration, Python, Unix Shell Scripting, SQL, XML, Cloud Computing, Software Development
Education
University of Mumbai 1992 — 1995
M.Phil, Mathematics
Indian Institute of Technology, Bombay 1990 — 1992
M.Sc., Mathematics
Saibal Saha's Cadence Design Systems Experience October 2001 - Present
Job Software Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems October 2001 - Present
Atesto Technologies Inc, Fremont May 2000 - September 2001
Delsoft June 1996 - December 1999
Skills
EDA, C++, Software Engineering, Simulation, Simulations, Algorithms
Education
Indian Institute of Technology, Kharagpur 1992 — 1996
B. Tech., Electronics
RKM Residential College, Narendrapur
Cadence Design Systems October 2001 - Present
Atesto Technologies Inc, Fremont May 2000 - September 2001
Delsoft June 1996 - December 1999
Skills
EDA, C++, Software Engineering, Simulation, Simulations, Algorithms
Education
Indian Institute of Technology, Kharagpur 1992 — 1996
B. Tech., Electronics
RKM Residential College, Narendrapur
Vivek Chickermane's Cadence Design Systems Experience October 2002 - Present
Job Distinguished Engineer and R&D Director at Cadence
Industry Computer Software
Experience
Cadence Design Systems October 2002 - Present
IBM May 1993 - September 2002
Center for Development of Telematics (C-DoT) 1985 - 1987
Skills
EDA, DFT, Logic Synthesis, ASIC, Cadence, TCL, ATPG, SoC, Embedded Systems, Timing Closure, Physical Design, Testing, RTL coding, Logic Design, VLSI, Cross-functional Team..., Static Timing Analysis, Verilog, VHDL, Test Automation, Debugging, Low-power Design, RTL Design
Education
University of Illinois at Urbana-Champaign 1988 — 1993
Ph.D, Electrical and Computer Engineering
Indian Institute of Technology, Delhi
B.Tech, Electrical and Computer Engineering
Cadence Design Systems October 2002 - Present
IBM May 1993 - September 2002
Center for Development of Telematics (C-DoT) 1985 - 1987
Skills
EDA, DFT, Logic Synthesis, ASIC, Cadence, TCL, ATPG, SoC, Embedded Systems, Timing Closure, Physical Design, Testing, RTL coding, Logic Design, VLSI, Cross-functional Team..., Static Timing Analysis, Verilog, VHDL, Test Automation, Debugging, Low-power Design, RTL Design
Education
University of Illinois at Urbana-Champaign 1988 — 1993
Ph.D, Electrical and Computer Engineering
Indian Institute of Technology, Delhi
B.Tech, Electrical and Computer Engineering
Rajiv Narayan's Cadence Design Systems Experience 1995 - 1997
Job Principal Engineer/Manager at Qualcomm
Industry Telecommunications
Experience
Qualcomm June 1998 - Present
Motorola 1997 - 1998
Cadence Design Systems 1995 - 1997
Skills
Embedded Software, Debugging, Embedded Systems, SoC, Wireless, Device Drivers, ASIC, Firmware
Education
Indian Institute of Technology (Banaras Hindu University), Varanasi
B.Tech, Computer Science
University of Southern California
MS, Computer Science
Qualcomm June 1998 - Present
Motorola 1997 - 1998
Cadence Design Systems 1995 - 1997
Skills
Embedded Software, Debugging, Embedded Systems, SoC, Wireless, Device Drivers, ASIC, Firmware
Education
Indian Institute of Technology (Banaras Hindu University), Varanasi
B.Tech, Computer Science
University of Southern California
MS, Computer Science
Ashok Taneja's Cadence Design Systems Experience July 2013 - Present
Job Sr IT Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2013 - Present
CDNS June 2008 - Present
Skills
Software Project..., SDLC, Software Development, Requirements Analysis, Unix, Agile Methodologies, Program Management, Enterprise Software, Scrum, SOA, Solution Architecture, Perl, Enterprise Architecture, Cloud Computing, Integration
Education
Himachal Pradesh University 1992 — 1995
Kurukshetra University 1989 — 1992
Bachelor of Computer
Cadence Design Systems July 2013 - Present
CDNS June 2008 - Present
Skills
Software Project..., SDLC, Software Development, Requirements Analysis, Unix, Agile Methodologies, Program Management, Enterprise Software, Scrum, SOA, Solution Architecture, Perl, Enterprise Architecture, Cloud Computing, Integration
Education
Himachal Pradesh University 1992 — 1995
Kurukshetra University 1989 — 1992
Bachelor of Computer
Lakshmi Puthanveetil, PMP, CSM's Cadence Design Systems Experience July 2010 - Present
Job Sr. Member of Technical Staff at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2010 - Present
Cadence Design Systems April 2005 - June 2010
Cadence Design Systems June 2000 - March 2005
Skills
Debugging, EDA, Shell Scripting, Verilog, Algorithms, Perl, Software Engineering, Agile Methodologies, ClearCase, TCL, C
Education
University of Massachusetts, Amherst 1997 — 2000
MS, Mathematics
Indian Institute of Technology, Madras 1995 — 1997
MSc, Mathematics
Mercy College, Palakkad 1992 — 1995
BSc, Mathematics
Mercy College, Palakkad 1990 — 1992
Bachelor of Science (B.Sc.), Mathematics
Holy Trinity School, Palakkad 1989 — 1990
Ashoka Hall Girls High School 1986 — 1989
Chinmaya Vidyalaya, Chennai 1979 — 1986
Cadence Design Systems July 2010 - Present
Cadence Design Systems April 2005 - June 2010
Cadence Design Systems June 2000 - March 2005
Skills
Debugging, EDA, Shell Scripting, Verilog, Algorithms, Perl, Software Engineering, Agile Methodologies, ClearCase, TCL, C
Education
University of Massachusetts, Amherst 1997 — 2000
MS, Mathematics
Indian Institute of Technology, Madras 1995 — 1997
MSc, Mathematics
Mercy College, Palakkad 1992 — 1995
BSc, Mathematics
Mercy College, Palakkad 1990 — 1992
Bachelor of Science (B.Sc.), Mathematics
Holy Trinity School, Palakkad 1989 — 1990
Ashoka Hall Girls High School 1986 — 1989
Chinmaya Vidyalaya, Chennai 1979 — 1986
Shuo Sheng's Cadence Design Systems Experience April 2003 - July 2003
Job Staff Engineer at Mentor Graphics
Industry Semiconductors
Experience
Mentor Graphics July 2003 - Present
Cadence Design Systems April 2003 - July 2003
Fujitsu Labs. of America May 2001 - August 2001
Skills
EDA, Formal Verification, Sat, DFT, Simulations, Electrical Engineering, ATPG, TCL, Verilog, ASIC, VHDL, Algorithms
Education
Rutgers University-New Brunswick 1998 — 2003
Ph.D., Computer Engineering
Tsinghua University 1995 — 1998
M.E., Electrical Engineering
Huazhong University of Science and Technology 1991 — 1995
B.E., Automatic Control Engineering
Mentor Graphics July 2003 - Present
Cadence Design Systems April 2003 - July 2003
Fujitsu Labs. of America May 2001 - August 2001
Skills
EDA, Formal Verification, Sat, DFT, Simulations, Electrical Engineering, ATPG, TCL, Verilog, ASIC, VHDL, Algorithms
Education
Rutgers University-New Brunswick 1998 — 2003
Ph.D., Computer Engineering
Tsinghua University 1995 — 1998
M.E., Electrical Engineering
Huazhong University of Science and Technology 1991 — 1995
B.E., Automatic Control Engineering
Anshum Gupta's Cadence Design Systems Experience June 2010 - January 2013
Job Software Engineer at Google
Industry Computer Software
Experience
Google October 2013 - April 2015
Cadence Design Systems June 2010 - January 2013
Oracle Corporation 2008 - 2008
Skills
TCL, EDA, Algorithms, Data Structures, C, C++, Linux, Object Oriented Design
Education
Indian Institute of Technology, Delhi 2005 — 2010
MTech + BTech, Computer Science and Engineering
Google October 2013 - April 2015
Cadence Design Systems June 2010 - January 2013
Oracle Corporation 2008 - 2008
Skills
TCL, EDA, Algorithms, Data Structures, C, C++, Linux, Object Oriented Design
Education
Indian Institute of Technology, Delhi 2005 — 2010
MTech + BTech, Computer Science and Engineering
LaNae Avra's Cadence Design Systems Experience December 1997 - Present
Job R&D Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems December 1997 - Present
Education
Hope College
BS, Engineering
Rensselaer Polytechnic Institute
BS, Electrical Engineering
Stanford University
MS, Electrical Engineering
Stanford University
PhD, Electrical Engineering
Cadence Design Systems December 1997 - Present
Education
Hope College
BS, Engineering
Rensselaer Polytechnic Institute
BS, Electrical Engineering
Stanford University
MS, Electrical Engineering
Stanford University
PhD, Electrical Engineering
Jenn Molyneaux's Cadence Design Systems Experience August 2000 - February 2005
Job Scrum Master at OnDeck
Industry Information Technology and Services
Experience
OnDeck June 2015 - Present
PayPal September 2013 - June 2015
PayPal October 2011 - September 2013
PayPal September 2009 - October 2011
Micros Systems September 2007 - August 2009
Micros Systems May 2007 - September 2007
Micros Systems December 2006 - May 2007
Micros Systems March 2006 - December 2006
Cadence Design Systems August 2000 - February 2005
Skills
Data Center, Servers, VMware ESX, SQL, Microsoft Office, Windows, Windows Server, Vendor Management, Testing, Call Centers, Unix, Quality Assurance, Access, Management, ACD, AOD, Sybase SQL Anywhere, Micros, IVR, Agile Methodologies, Microsoft SQL Server, OS X, Software Installation, Databases, Aspect, Mac OS X, Oracle SQL, Scrum, Agile Methodolgy, Product Management, Software Product..., Product Owner, Technical Support, Business Analysis, Requirements Analysis, Software Project..., Integration, Strategy, Team Leadership, Process Improvement, Oracle, Disaster Recovery, Analytics, SDLC
Education
Community College of Baltimore County
Howard Community College
OnDeck June 2015 - Present
PayPal September 2013 - June 2015
PayPal October 2011 - September 2013
PayPal September 2009 - October 2011
Micros Systems September 2007 - August 2009
Micros Systems May 2007 - September 2007
Micros Systems December 2006 - May 2007
Micros Systems March 2006 - December 2006
Cadence Design Systems August 2000 - February 2005
Skills
Data Center, Servers, VMware ESX, SQL, Microsoft Office, Windows, Windows Server, Vendor Management, Testing, Call Centers, Unix, Quality Assurance, Access, Management, ACD, AOD, Sybase SQL Anywhere, Micros, IVR, Agile Methodologies, Microsoft SQL Server, OS X, Software Installation, Databases, Aspect, Mac OS X, Oracle SQL, Scrum, Agile Methodolgy, Product Management, Software Product..., Product Owner, Technical Support, Business Analysis, Requirements Analysis, Software Project..., Integration, Strategy, Team Leadership, Process Improvement, Oracle, Disaster Recovery, Analytics, SDLC
Education
Community College of Baltimore County
Howard Community College
Ankush Sood's Cadence Design Systems Experience July 2013 - Present
Job Product Engineering Director at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2013 - Present
Cadence Design Systems July 2010 - June 2013
Cadence Design Systems 2003 - June 2010
Skills
Formal Verification, ASIC, Physical Design, EDA, Integrated Circuit..., Semiconductors, IC, VLSI, Algorithms, Logic Synthesis, RTL design, TCL, Debugging, DFT, SoC, Clock Tree Synthesis, Functional Verification, Static Timing Analysis, DRC, Low-power Design, CMOS, Verilog, Timing Closure, Timing
Education
Indian Institute of Technology, Bombay 1998 — 2003
BTech Mtech, electrical, microelectronics
Cadence Design Systems July 2013 - Present
Cadence Design Systems July 2010 - June 2013
Cadence Design Systems 2003 - June 2010
Skills
Formal Verification, ASIC, Physical Design, EDA, Integrated Circuit..., Semiconductors, IC, VLSI, Algorithms, Logic Synthesis, RTL design, TCL, Debugging, DFT, SoC, Clock Tree Synthesis, Functional Verification, Static Timing Analysis, DRC, Low-power Design, CMOS, Verilog, Timing Closure, Timing
Education
Indian Institute of Technology, Bombay 1998 — 2003
BTech Mtech, electrical, microelectronics
Bo Wan's Cadence Design Systems Experience April 2004 - February 2012
Job CEO at NineCube, http://www.ninecubedesign.com
Industry Semiconductors
Experience
NineCube February 2012 - Present
Cadence Design Systems April 2004 - February 2012
Skills
EDA, ASIC, Semiconductors, Algorithms, Perl, IC, Simulations, C++, C, SoC
Education
University of Washington 1999 — 2004
Ph.D., Circuit Simulation, Optimization, Device Modeling
Huazhong University of Science and Technology
Huazhong University of Science and Technology
Tsinghua University
Master of Science (MS), Computer Science EDA
NineCube February 2012 - Present
Cadence Design Systems April 2004 - February 2012
Skills
EDA, ASIC, Semiconductors, Algorithms, Perl, IC, Simulations, C++, C, SoC
Education
University of Washington 1999 — 2004
Ph.D., Circuit Simulation, Optimization, Device Modeling
Huazhong University of Science and Technology
Huazhong University of Science and Technology
Tsinghua University
Master of Science (MS), Computer Science EDA
Udayan Gumaste's Cadence Design Systems Experience
Job Senior Member of Consulting Staff at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems
Skills
EDA, Algorithms, TCL, Perl, Python, STL, Debugging, CVS, Software Engineering, C++, VLSI, Data Structures, Object Oriented Design, GNU Debugger, C, Shell Scripting, Qt
Education
University of Colorado Boulder 1993 — 1998
Ph.D.
Indian Institute of Technology, Bombay 1988 — 1992
B.Tech
St. Vincent's High School, Pune 1980 — 1988
Cadence Design Systems
Skills
EDA, Algorithms, TCL, Perl, Python, STL, Debugging, CVS, Software Engineering, C++, VLSI, Data Structures, Object Oriented Design, GNU Debugger, C, Shell Scripting, Qt
Education
University of Colorado Boulder 1993 — 1998
Ph.D.
Indian Institute of Technology, Bombay 1988 — 1992
B.Tech
St. Vincent's High School, Pune 1980 — 1988
Don Felix's Cadence Design Systems Experience January 2000 - Present
Job Staff Systems Administrator at Cadence Design Systems
Industry Information Technology and Services
Experience
Cadence Design Systems January 2000 - Present
Weathernews 1998 - December 1999
Skills
Perl, Solaris, Unix Shell Scripting, Linux, Shell Scripting, Unix, System Administration, Virtualization, Python, Software Development, Software Project..., Operating Systems, Integration, SharePoint
Education
Humboldt State University 1986 — 2003
BA, Physics, Math
Cadence Design Systems January 2000 - Present
Weathernews 1998 - December 1999
Skills
Perl, Solaris, Unix Shell Scripting, Linux, Shell Scripting, Unix, System Administration, Virtualization, Python, Software Development, Software Project..., Operating Systems, Integration, SharePoint
Education
Humboldt State University 1986 — 2003
BA, Physics, Math
Sachchidananda Patel's Cadence Design Systems Experience 1995 - 1998
Job Sr. Staff R&D Engineer at Synopsys
Industry Computer Software
Experience
Synopsys January 1999 - Present
Synopsys India Private Limited 1998 - 1998
Cadence Design Systems 1995 - 1998
Education
Indian Institute of Technology, Delhi 1993 — 1995
Master of Technology (MTech), Computer Engineering
Indian Institute of Technology, Kharagpur 1988 — 1992
Bachelor of Technology (BTech), Electrical and Electronics Engineering
Synopsys January 1999 - Present
Synopsys India Private Limited 1998 - 1998
Cadence Design Systems 1995 - 1998
Education
Indian Institute of Technology, Delhi 1993 — 1995
Master of Technology (MTech), Computer Engineering
Indian Institute of Technology, Kharagpur 1988 — 1992
Bachelor of Technology (BTech), Electrical and Electronics Engineering
Roy Leventhal's Cadence Design Systems Experience March 1996 - June 1998
Job EMIEMC Contract Engineer and Trainer
Industry Aviation & Aerospace
Experience
Leventhal Design and Communications January 2010 - Present
National Technical Services September 2011 - June 2013
Illinois Institute of Technology January 2013 - January 2013
Northwestern University November 2012 - December 2012
Hamilton Sundstrand September 2007 - December 2009
Cinch Connectors July 2005 - April 2007
3Com August 1998 - April 2002
Cadence Design Systems March 1996 - June 1998
Skills
EMI-EMC Integrity, Signal Integrity, Power Integrity, Modeling and Simulation, Semiconductor Modeling, Device Physics, RF circuits, EMC compliance, PCB layout design, Reliability Engineering, Quality Assurance, EMI-EMC Measurements..., Testing, RF, PCB design, Microwave
Education
University of Wisconsin-Milwaukee 1990 — 1994
none, Micowaves and RF
Fairchild Semiconductor R&D 1972 — 1973
none, Semiconductor Physics
Santa Clara University 1971 — 1972
none, Semiconductor Physics
Illinois Institute of Technology 1956 — 1966
MSEE, Electronics
Leventhal Design and Communications January 2010 - Present
National Technical Services September 2011 - June 2013
Illinois Institute of Technology January 2013 - January 2013
Northwestern University November 2012 - December 2012
Hamilton Sundstrand September 2007 - December 2009
Cinch Connectors July 2005 - April 2007
3Com August 1998 - April 2002
Cadence Design Systems March 1996 - June 1998
Skills
EMI-EMC Integrity, Signal Integrity, Power Integrity, Modeling and Simulation, Semiconductor Modeling, Device Physics, RF circuits, EMC compliance, PCB layout design, Reliability Engineering, Quality Assurance, EMI-EMC Measurements..., Testing, RF, PCB design, Microwave
Education
University of Wisconsin-Milwaukee 1990 — 1994
none, Micowaves and RF
Fairchild Semiconductor R&D 1972 — 1973
none, Semiconductor Physics
Santa Clara University 1971 — 1972
none, Semiconductor Physics
Illinois Institute of Technology 1956 — 1966
MSEE, Electronics
Prasad Gudem's Cadence Design Systems Experience 1998 - 2000
Job Vice President, Engineering
Industry Telecommunications
Experience
University of California at San Diego 2014 - Present
Qualcomm Technologies Inc. 2002 - Present
T. J. Watson Research Center, International Business Machines (IBM) 2000 - 2002
Cadence Design Systems 1998 - 2000
Education
University of Waterloo 1991 — 1996
Ph.D., Electrical Engineering
Indian Institute of Technology, Madras 1984 — 1988
B.Tech, Electrical Engineering
Visakha Valley School
University of California at San Diego 2014 - Present
Qualcomm Technologies Inc. 2002 - Present
T. J. Watson Research Center, International Business Machines (IBM) 2000 - 2002
Cadence Design Systems 1998 - 2000
Education
University of Waterloo 1991 — 1996
Ph.D., Electrical Engineering
Indian Institute of Technology, Madras 1984 — 1988
B.Tech, Electrical Engineering
Visakha Valley School
Vikram Agarwal's Cadence Design Systems Experience July 2000 - Present
Job Sr. Sales Technical Leader at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems July 2000 - Present
Skills
EDA, Physical Design, IC, VLSI, Mixed Signal, Cadence Skill, Cadence Virtuoso, Cadence Virtuoso Layout..., Cadence Virtuoso Power...
Education
IIT Kharagpur 1991 — 1995
BTech, Electrical Engineering
Cadence Design Systems July 2000 - Present
Skills
EDA, Physical Design, IC, VLSI, Mixed Signal, Cadence Skill, Cadence Virtuoso, Cadence Virtuoso Layout..., Cadence Virtuoso Power...
Education
IIT Kharagpur 1991 — 1995
BTech, Electrical Engineering
Chandra Mouli Pingali's Cadence Design Systems Experience June 2008 - December 2008
Job SAP HR Technical Consultant at 3Core Systems Inc
Industry Information Technology and Services
Experience
3Core Systems Inc 2007 - Present
Mettler Toledo January 2009 - May 2009
Cadence Design Systems June 2008 - December 2008
Education
Indiana State University 2002 — 2003
Master of Science, Electronics and Computer Technology
Jawaharlal Nehru Technological University
3Core Systems Inc 2007 - Present
Mettler Toledo January 2009 - May 2009
Cadence Design Systems June 2008 - December 2008
Education
Indiana State University 2002 — 2003
Master of Science, Electronics and Computer Technology
Jawaharlal Nehru Technological University
Rachida Kebichi's Cadence Design Systems Experience February 2001 - May 2003
Job Member of Technical Staff Design Engineer at AMD
Industry Computer Hardware
Experience
AMD May 2005 - Present
AMD 2005 - Present
Cadence Design Systems February 2001 - May 2003
Micron Technology Incorporation, Hillsboro, OR January 2000 - March 2001
Skills
EDA, SystemVerilog, Functional Verification, SystemC, SoC, TCL, ASIC, RTL design, VLSI, Verilog, Computer Architecture, Debugging, Logic Synthesis, Simulations, C++, Integrated Circuit..., Perl, RTL Design, Emulation, IC
Education
Institut polytechnique de Grenoble 1992 — 1997
PhD, Computer science
National Polytechnic Institute of Grenoble 1992 — 1993
Master Degree, CS
AMD May 2005 - Present
AMD 2005 - Present
Cadence Design Systems February 2001 - May 2003
Micron Technology Incorporation, Hillsboro, OR January 2000 - March 2001
Skills
EDA, SystemVerilog, Functional Verification, SystemC, SoC, TCL, ASIC, RTL design, VLSI, Verilog, Computer Architecture, Debugging, Logic Synthesis, Simulations, C++, Integrated Circuit..., Perl, RTL Design, Emulation, IC
Education
Institut polytechnique de Grenoble 1992 — 1997
PhD, Computer science
National Polytechnic Institute of Grenoble 1992 — 1993
Master Degree, CS
Amandeep Bharti's Cadence Design Systems Experience May 2008 - July 2008
Job AVP at Credit Suisse
Industry Banking
Experience
Credit Suisse July 2010 - Present
Cadence Design Systems May 2008 - July 2008
Skills
Derivatives, Quantitative Finance
Education
Indian Institute of Technology, Delhi 2005 — 2010
Credit Suisse July 2010 - Present
Cadence Design Systems May 2008 - July 2008
Skills
Derivatives, Quantitative Finance
Education
Indian Institute of Technology, Delhi 2005 — 2010
Jie Yang's Cadence Design Systems Experience July 2010 - 2013
Job Software engineer
Industry Computer Software
Experience
Nest January 2015 - Present
Captora October 2013 - December 2014
Cadence Design Systems July 2010 - 2013
Synopsys August 2007 - July 2010
Optimal/Apache DA/ANSYS October 2003 - August 2007
Skills
EDA, TCL, Purify, Data Structures, Physical Modeling, Gdb, Physical Design, VLSI, Algorithms, CVS, Object Oriented Design, MFC, Signal Integrity, IC, GUI, C++, OOP, Software Engineering, C, Software Design, Software Development, Linux, Unix, Qt, Excellent in C++, STL, C, GNU Debugger, Debugging, IBM Rational Purify, Perl, Java, Distributed Systems, VLSI CAD
Education
Huazhong University of Science and Technology
Bachelor of Science (BS)
University of Illinois at Urbana-Champaign
MS, Computer Science
Nest January 2015 - Present
Captora October 2013 - December 2014
Cadence Design Systems July 2010 - 2013
Synopsys August 2007 - July 2010
Optimal/Apache DA/ANSYS October 2003 - August 2007
Skills
EDA, TCL, Purify, Data Structures, Physical Modeling, Gdb, Physical Design, VLSI, Algorithms, CVS, Object Oriented Design, MFC, Signal Integrity, IC, GUI, C++, OOP, Software Engineering, C, Software Design, Software Development, Linux, Unix, Qt, Excellent in C++, STL, C, GNU Debugger, Debugging, IBM Rational Purify, Perl, Java, Distributed Systems, VLSI CAD
Education
Huazhong University of Science and Technology
Bachelor of Science (BS)
University of Illinois at Urbana-Champaign
MS, Computer Science
Juneann McDonald's Cadence Design Systems Experience 2002 - 2003
Job
Industry Logistics and Supply Chain
Experience
Jawbone November 2013 - Present
NetApp January 2006 - March 2013
NetApp November 2004 - December 2005
Cadence Design Systems 2002 - 2003
Quantum Corporation 1999 - 2001
Quantum Corporation 1997 - 1999
Quantum Corporation 1994 - 1997
Hewlett-Packard 1986 - 1989
Skills
Logistics, Program Management, Management, Product Development, Manufacturing, Supply Chain, Business Development, Team Leadership, Supply Management, Budgets, Negotiation, Process Improvement, Supply Chain Management, Contract Negotiation, Inventory Management, Leadership, Strategy, Strategic Planning, Cross-functional Team..., Business Process, Six Sigma, Project Portfolio..., Operations Management, Vendor Management, Strategic Sourcing, Business Process..., Change Management, Outsourcing, Procurement, ERP, Continuous Improvement, Project Planning
Education
Stanford University 1986 — 1987
Master's degree, Manufacturing Systems Engineering
Howard University 1983 — 1984
Master of Engineering (M.Eng.), Mechanical Engineering
Howard University 1978 — 1982
Bachelor of Science (B.S.), Mechanical Engineering
BHS
Jawbone November 2013 - Present
NetApp January 2006 - March 2013
NetApp November 2004 - December 2005
Cadence Design Systems 2002 - 2003
Quantum Corporation 1999 - 2001
Quantum Corporation 1997 - 1999
Quantum Corporation 1994 - 1997
Hewlett-Packard 1986 - 1989
Skills
Logistics, Program Management, Management, Product Development, Manufacturing, Supply Chain, Business Development, Team Leadership, Supply Management, Budgets, Negotiation, Process Improvement, Supply Chain Management, Contract Negotiation, Inventory Management, Leadership, Strategy, Strategic Planning, Cross-functional Team..., Business Process, Six Sigma, Project Portfolio..., Operations Management, Vendor Management, Strategic Sourcing, Business Process..., Change Management, Outsourcing, Procurement, ERP, Continuous Improvement, Project Planning
Education
Stanford University 1986 — 1987
Master's degree, Manufacturing Systems Engineering
Howard University 1983 — 1984
Master of Engineering (M.Eng.), Mechanical Engineering
Howard University 1978 — 1982
Bachelor of Science (B.S.), Mechanical Engineering
BHS
Neeharika K's Cadence Design Systems Experience March 2013 - January 2014
Job
Industry Human Resources
Experience
Cadence Design Systems March 2013 - January 2014
Infosys January 2012 - January 2013
Robert Half International April 2011 - December 2011
Media Pro Inc December 2009 - March 2011
Skills
Background Checks, Full-cycle Recruiting, Salary Negotiation, Contract Recruitment, Technical Recruiting, Applicant Tracking..., Screening, Talent Acquisition, Recruitment Advertising, Direct Recruiting, Hiring, Sourcing, Permanent Placement, Staffing Industry, Professional Staffing, Internet Recruiting, Interviewing, Cold Calling, Candidate Screening, Account Management, Employee Relations, Outlook, Temporary Staffing, Client Retention, Interviews, Recruiting, Corporate Recruiting, Negotiation, Boolean Searching, Business Partner..., Business Partner Support, Human Resources, Onboarding
Education
University of San Francisco 2010 — 2011
Masters Certificate in Online Marketing, SEO / SEM
Indian Institute of Information Technology 2006 — 2006
MSIT - Certificate in IT, Information Technology
Jawaharlal Nehru Technological University 1998 — 2002
B Tech, Mechanical Engineering
Cadence Design Systems March 2013 - January 2014
Infosys January 2012 - January 2013
Robert Half International April 2011 - December 2011
Media Pro Inc December 2009 - March 2011
Skills
Background Checks, Full-cycle Recruiting, Salary Negotiation, Contract Recruitment, Technical Recruiting, Applicant Tracking..., Screening, Talent Acquisition, Recruitment Advertising, Direct Recruiting, Hiring, Sourcing, Permanent Placement, Staffing Industry, Professional Staffing, Internet Recruiting, Interviewing, Cold Calling, Candidate Screening, Account Management, Employee Relations, Outlook, Temporary Staffing, Client Retention, Interviews, Recruiting, Corporate Recruiting, Negotiation, Boolean Searching, Business Partner..., Business Partner Support, Human Resources, Onboarding
Education
University of San Francisco 2010 — 2011
Masters Certificate in Online Marketing, SEO / SEM
Indian Institute of Information Technology 2006 — 2006
MSIT - Certificate in IT, Information Technology
Jawaharlal Nehru Technological University 1998 — 2002
B Tech, Mechanical Engineering
Chong Hao's Cadence Design Systems Experience 1998 - 2000
Job Professor
Industry Computer Networking
Experience
MiraCosta College 2006 - Present
eSilicon 2000 - 2003
Cadence Design Systems 1998 - 2000
Bell Labs 1979 - 1998
Cornell University 1977 - 1978
Skills
EDA, Simulations, IC, Mixed Signal, Semiconductors, CMOS, VLSI, ASIC, Low-power Design, TCL, Integrated Circuit..., Analog Circuit Design, Cisco Certified, Microsoft Servers &..., C++, Analog
Education
Indiana University Bloomington 1973 — 1977
Ph.D., Physics
MiraCosta College 2006 - Present
eSilicon 2000 - 2003
Cadence Design Systems 1998 - 2000
Bell Labs 1979 - 1998
Cornell University 1977 - 1978
Skills
EDA, Simulations, IC, Mixed Signal, Semiconductors, CMOS, VLSI, ASIC, Low-power Design, TCL, Integrated Circuit..., Analog Circuit Design, Cisco Certified, Microsoft Servers &..., C++, Analog
Education
Indiana University Bloomington 1973 — 1977
Ph.D., Physics
Srini Arikati's Cadence Design Systems Experience 1998 - 2006
Job R&D Manager at Synopsys
Industry Computer Software
Experience
Synopsys July 2006 - Present
Cadence Design Systems 1998 - 2006
Skills
Algorithms, ASIC, Software Engineering, VLSI, EDA, Verilog, SoC, Graph Algorithms, Graph Theory
Education
University of Illinois at Chicago 1989 — 1993
Doctor of Philosophy (PhD), Computer Science
IIT Madras 1987 — 1989
Master of Science (MS), Computer Science
National Institute of Technology Warangal 1982 — 1986
B.Tech, ECE
APRJ College, Nagarjuna Sagar, AP, India
Synopsys July 2006 - Present
Cadence Design Systems 1998 - 2006
Skills
Algorithms, ASIC, Software Engineering, VLSI, EDA, Verilog, SoC, Graph Algorithms, Graph Theory
Education
University of Illinois at Chicago 1989 — 1993
Doctor of Philosophy (PhD), Computer Science
IIT Madras 1987 — 1989
Master of Science (MS), Computer Science
National Institute of Technology Warangal 1982 — 1986
B.Tech, ECE
APRJ College, Nagarjuna Sagar, AP, India
Ashutosh Mujumdar's Cadence Design Systems Experience 1995 - 1999
Job Engineering Manager at ARM
Industry Semiconductors
Experience
ARM August 2001 - Present
Synplicity 1999 - 2001
Cadence Design Systems 1995 - 1999
Skills
Digital hardware..., Low power design, Synthesis, place & route, SoC, ASIC, Semiconductors, Verilog, ARM, IC, EDA, Processors, VLSI
Education
Indian Institute of Technology, Bombay
B. Tech., Electrical and Electronics Engineering
University of Wisconsin-Madison
Doctor of Philosophy (PhD), Computer Engineering
ARM August 2001 - Present
Synplicity 1999 - 2001
Cadence Design Systems 1995 - 1999
Skills
Digital hardware..., Low power design, Synthesis, place & route, SoC, ASIC, Semiconductors, Verilog, ARM, IC, EDA, Processors, VLSI
Education
Indian Institute of Technology, Bombay
B. Tech., Electrical and Electronics Engineering
University of Wisconsin-Madison
Doctor of Philosophy (PhD), Computer Engineering
Arun Taylor's Cadence Design Systems Experience July 2005 - January 2007
Job Cofounder at Accord Software, Inc. Massachusetts, USA
Industry Information Technology and Services
Experience
Accord Software, Inc. Massachusetts, USA Principal Software EngineerAccord Software, Inc.February 2007 - Present
Cadence Design Systems July 2005 - January 2007
Accord Software, Inc. September 2004 - June 2005
EMC February 2004 - August 2004
Accord Software, Inc. February 2003 - January 2004
EMC April 2002 - January 2003
Accord Software, Inc. July 1999 - March 2002
Comverse May 1998 - June 1999
Accord Software, Inc. January 1997 - April 1998
Comverse July 1995 - December 1996
Skills
Software Development, Java, Agile Methodologies, Cloud Computing, JavaScript, Distributed Systems, Automated Software..., Perl, Shell Scripting, Networking, File Systems, Device Drivers, Parallel Programming, Scalable Architecture, Scalable Web..., HTTP, RESTful WebServices, HTML, CSS, XML, JSON, Language Development, Lex, Yacc, Compiler Construction, Real Time Monitoring, Real Time Reports, Event Driven Programming, Object Oriented Design, ActiveML, CORBA, RPC, High Performance...
Education
Imperial College London
B.Sc(Eng)
Accord Software, Inc. Massachusetts, USA Principal Software EngineerAccord Software, Inc.February 2007 - Present
Cadence Design Systems July 2005 - January 2007
Accord Software, Inc. September 2004 - June 2005
EMC February 2004 - August 2004
Accord Software, Inc. February 2003 - January 2004
EMC April 2002 - January 2003
Accord Software, Inc. July 1999 - March 2002
Comverse May 1998 - June 1999
Accord Software, Inc. January 1997 - April 1998
Comverse July 1995 - December 1996
Skills
Software Development, Java, Agile Methodologies, Cloud Computing, JavaScript, Distributed Systems, Automated Software..., Perl, Shell Scripting, Networking, File Systems, Device Drivers, Parallel Programming, Scalable Architecture, Scalable Web..., HTTP, RESTful WebServices, HTML, CSS, XML, JSON, Language Development, Lex, Yacc, Compiler Construction, Real Time Monitoring, Real Time Reports, Event Driven Programming, Object Oriented Design, ActiveML, CORBA, RPC, High Performance...
Education
Imperial College London
B.Sc(Eng)
Abhishek Kanungo's Cadence Design Systems Experience June 1997 - Present
Job Software Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems June 1997 - Present
Skills
EDA, C, C, Debugging, Verilog, Software Engineering, Algorithms, Software Development, C++
Education
IIT Kharagpur 1993 — 1997
Bachelor of Technology (B.Tech.), Computer Science
Cadence Design Systems June 1997 - Present
Skills
EDA, C, C, Debugging, Verilog, Software Engineering, Algorithms, Software Development, C++
Education
IIT Kharagpur 1993 — 1997
Bachelor of Technology (B.Tech.), Computer Science
Hewlett-Packard
SAP
Symantec
Intuit
HP
salesforce.com
Bloomberg LP
Autodesk