Cadence Design Systems
Industry: Software company
DescriptionCadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. CEO: Lip-Bu Tan (Jan 2009–) Headquarters: San Jose, California, United States Revenue: 1.816 billion USD (2016) Subsidiaries: Sigrity, Tensilica, Chip Estimate Corp, nusemi inc,
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Cadence Design Systems Employees
Employee
Years
Job
Industry
Frederico Yoshida Frederico Yoshida's Cadence Design Systems Experience June 2014 - Present
Job Lead Application Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems June 2014 - Present
Jasper Design Automation August 2013 - June 2014
Jasper Design Automation January 2012 - July 2013
Instituto de Cultura Oriental April 2010 - September 2012
Lightning Research Center - CEMIG/UFMG September 2011 - December 2011
Global Ciência e Tecnologia Bio S/A September 2007 - February 2010
Skills
Verilog, Formal Verification, TCL, C++, Software Engineering, Programming, SystemVerilog, Simulations, AMBA, Matlab, FPGA, C, Embedded Systems
Education
Universidade Federal de Minas Gerais 2007 — 2013
B.S., Control & Automation Engineering
Cadence Design Systems June 2014 - Present
Jasper Design Automation August 2013 - June 2014
Jasper Design Automation January 2012 - July 2013
Instituto de Cultura Oriental April 2010 - September 2012
Lightning Research Center - CEMIG/UFMG September 2011 - December 2011
Global Ciência e Tecnologia Bio S/A September 2007 - February 2010
Skills
Verilog, Formal Verification, TCL, C++, Software Engineering, Programming, SystemVerilog, Simulations, AMBA, Matlab, FPGA, C, Embedded Systems
Education
Universidade Federal de Minas Gerais 2007 — 2013
B.S., Control & Automation Engineering
Emma Salom SCPM Emma Salom SCPM's Cadence Design Systems Experience September 2013 - Present
Job Sr. Program Manager at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems September 2013 - Present
Cadence Design Systems July 2010 - September 2013
Cadence Design Systems May 2001 - 2010
IBM 2000 - 2001
Yield Engineering Systems January 1999 - January 2000
Skills
FrameMaker, EDA, TCL, Wikis, Formal Verification, Verilog, Technical Writing, VHDL, FPGA, Software Development, XML, HTML, Start-ups, SQL, Software Documentation, Program Management, CSS, Event Management, Event Planning, Editing, Technical Documentation, Agile Methodologies
Education
University of Asia and the Pacific 1994 — 1998
Bachelor of Science (BS), Information Technology
Cadence Design Systems September 2013 - Present
Cadence Design Systems July 2010 - September 2013
Cadence Design Systems May 2001 - 2010
IBM 2000 - 2001
Yield Engineering Systems January 1999 - January 2000
Skills
FrameMaker, EDA, TCL, Wikis, Formal Verification, Verilog, Technical Writing, VHDL, FPGA, Software Development, XML, HTML, Start-ups, SQL, Software Documentation, Program Management, CSS, Event Management, Event Planning, Editing, Technical Documentation, Agile Methodologies
Education
University of Asia and the Pacific 1994 — 1998
Bachelor of Science (BS), Information Technology
Younes Chouia Younes Chouia's Cadence Design Systems Experience February 2013 - December 2013
Job Physical Design Manager at Altera
Industry Semiconductors
Experience
Altera January 2014 - Present
Cadence Design Systems February 2013 - December 2013
Semtech Corporation – Gennum Products November 2012 - March 2013
AMD November 2009 - October 2012
ESS Technology January 2005 - January 2009
Prompt Quebec January 2003 - January 2005
Skills
IC layout, DRC, LVS, DFM, Floorplanning, Power Management, Analog Circuit Design, VLSI, VLSI CAD, RC Extraction, EMIR Analysis, PLL, CMOS, Cadence Virtuoso, Virtuoso XL, Mixed-Signal IC Design, Mixed Signal, Physical Verification, Physical Design, VHDL, Verilog, ADCs
Education
Ecole Polytechnique de Montreal 2002 — 2005
M Sc. A., Microelectronics
Altera January 2014 - Present
Cadence Design Systems February 2013 - December 2013
Semtech Corporation – Gennum Products November 2012 - March 2013
AMD November 2009 - October 2012
ESS Technology January 2005 - January 2009
Prompt Quebec January 2003 - January 2005
Skills
IC layout, DRC, LVS, DFM, Floorplanning, Power Management, Analog Circuit Design, VLSI, VLSI CAD, RC Extraction, EMIR Analysis, PLL, CMOS, Cadence Virtuoso, Virtuoso XL, Mixed-Signal IC Design, Mixed Signal, Physical Verification, Physical Design, VHDL, Verilog, ADCs
Education
Ecole Polytechnique de Montreal 2002 — 2005
M Sc. A., Microelectronics
Anthony Mazzi's Cadence Design Systems Experience 2004 - 2005
Job Manager, Asset Lifecycle Management
Industry Information Technology and Services
Experience
Symantec Corporation, Cloud Platform Engineering July 2013 - Present
Symantec Corporation, Trust Services May 2011 - July 2013
STAPLES, INC. October 2008 - May 2009
IBM/COMPUCOM AT CISCO SYSTEMS February 2006 - October 2008
TAME 2005 - 2006
Cadence Design Systems 2004 - 2005
Cadence Design Systems 2003 - 2004
Cadence Design Systems 2002 - 2003
Cadence Design Systems 2000 - 2002
TAME, INC. 1988 - 2000
Skills
Process Improvement, Cross-functional Team..., Vendor Management, Strategy, Team Management, Program Management, ITIL, Business Analysis, IT Asset Management, Integration, Management, Team Leadership, Software Documentation, Data Center, Business Planning, Software Licensing, Cloud Computing, Enterprise Software, Analysis, Consulting, Service Delivery, IT Service Management, Contract Negotiation, Business Process, SaaS, Business Process...
Education
IAITAM CSAM & CHAMP 2005 — 2005
ITIL v.3 Foundations, Continual Service Improvement, Service Offerings & Agreements
University of California, Berkeley
BA
Symantec Corporation, Cloud Platform Engineering July 2013 - Present
Symantec Corporation, Trust Services May 2011 - July 2013
STAPLES, INC. October 2008 - May 2009
IBM/COMPUCOM AT CISCO SYSTEMS February 2006 - October 2008
TAME 2005 - 2006
Cadence Design Systems 2004 - 2005
Cadence Design Systems 2003 - 2004
Cadence Design Systems 2002 - 2003
Cadence Design Systems 2000 - 2002
TAME, INC. 1988 - 2000
Skills
Process Improvement, Cross-functional Team..., Vendor Management, Strategy, Team Management, Program Management, ITIL, Business Analysis, IT Asset Management, Integration, Management, Team Leadership, Software Documentation, Data Center, Business Planning, Software Licensing, Cloud Computing, Enterprise Software, Analysis, Consulting, Service Delivery, IT Service Management, Contract Negotiation, Business Process, SaaS, Business Process...
Education
IAITAM CSAM & CHAMP 2005 — 2005
ITIL v.3 Foundations, Continual Service Improvement, Service Offerings & Agreements
University of California, Berkeley
BA
Farid Mashayekh Farid Mashayekh's Cadence Design Systems Experience October 2012 - Present
Job Finance Group Director at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems October 2012 - Present
Cadence Design Systems January 2010 - October 2012
Cadence Design Systems April 2002 - January 2010
University Planet April 1999 - April 2002
Duet Technologies July 1998 - March 1999
Synopsys March 1997 - July 1998
Cadence Design Systems July 1990 - March 1997
Zilog July 1989 - July 1990
Intersil April 1984 - July 1989
Intel Corporation June 1982 - April 1984
Skills
Investment Advisory, Market Analysis, Competitive Intelligence, Business Intelligence, Executive Management, Business Development, Sales, Marketing, EDA, Enterprise Software, Higher Education, Microsoft Excel, Business Strategy
Education
University of California, Berkeley 1980 — 1982
Master of Science (M.S.), Electrical Engineering and Computer Science, 3.7
University of Southern California 1977 — 1980
Bachelor of Science (B.S.), Electrical Engineering, 3.7
Cadence Design Systems October 2012 - Present
Cadence Design Systems January 2010 - October 2012
Cadence Design Systems April 2002 - January 2010
University Planet April 1999 - April 2002
Duet Technologies July 1998 - March 1999
Synopsys March 1997 - July 1998
Cadence Design Systems July 1990 - March 1997
Zilog July 1989 - July 1990
Intersil April 1984 - July 1989
Intel Corporation June 1982 - April 1984
Skills
Investment Advisory, Market Analysis, Competitive Intelligence, Business Intelligence, Executive Management, Business Development, Sales, Marketing, EDA, Enterprise Software, Higher Education, Microsoft Excel, Business Strategy
Education
University of California, Berkeley 1980 — 1982
Master of Science (M.S.), Electrical Engineering and Computer Science, 3.7
University of Southern California 1977 — 1980
Bachelor of Science (B.S.), Electrical Engineering, 3.7
Richard Goering Richard Goering's Cadence Design Systems Experience April 2009 - June 2015
Job Technology journalist
Industry Semiconductors
Experience
Cadence Design Systems April 2009 - June 2015
SCDsource.com September 2007 - January 2009
CMP Media August 1989 - June 2007
Personal Engineering and Instrumentation News August 1988 - July 1989
Penwell Publishing August 1984 - August 1988
Skills
Blogging, White Papers, Product Marketing, Technical Writing, EDA, Corporate Communications, SoC, Web Content, Content Development, Content Strategy, Semiconductors, Publications, Content Management, Start-ups, Integrated Circuit..., Editorial, Marketing Strategy, ASIC, Editing, Electronics, Press Releases, Video, Storytelling, Microprocessors, Publishing, FPGA, Copywriting, Marketing Communications, IC, Magazines, Management, Testing, Product Management, Journalism, High Performance..., Newspapers, Embedded Software
Education
University of California, Berkeley 1969 — 1973
B.A., Journalism
University of Missouri-Kansas City
Computer science
Cadence Design Systems April 2009 - June 2015
SCDsource.com September 2007 - January 2009
CMP Media August 1989 - June 2007
Personal Engineering and Instrumentation News August 1988 - July 1989
Penwell Publishing August 1984 - August 1988
Skills
Blogging, White Papers, Product Marketing, Technical Writing, EDA, Corporate Communications, SoC, Web Content, Content Development, Content Strategy, Semiconductors, Publications, Content Management, Start-ups, Integrated Circuit..., Editorial, Marketing Strategy, ASIC, Editing, Electronics, Press Releases, Video, Storytelling, Microprocessors, Publishing, FPGA, Copywriting, Marketing Communications, IC, Magazines, Management, Testing, Product Management, Journalism, High Performance..., Newspapers, Embedded Software
Education
University of California, Berkeley 1969 — 1973
B.A., Journalism
University of Missouri-Kansas City
Computer science
Robert Sleeper Robert Sleeper's Cadence Design Systems Experience 2000 - 2002
Job IP Licensing Manager for the College of Engineering at The University of Arizona
Industry Law Practice
Experience
The University of Arizona June 2013 - Present
Honeywell Aerospace October 2005 - June 2013
Honeywell Aerospace January 1987 - October 2005
Cadence Design Systems 2000 - 2002
Trimble Navigation 1999 - 2000
Parker Hannifin 1984 - 1986
Skills
Intellectual Property, Licensing, Contract Negotiation, Patents, Engineering, Aerospace, Technology Transfer, Business Strategy, Licensing Negotiations, Licensing Strategy, IP transactions, Manufacturing Agreements, Intellectual Property..., Legal Writing, Legal Compliance, Mergers & Acquisitions, Cross-functional Team..., Engineering Management, Start-ups, Business Development, Copyright Law, Strategy, Electronics, Six Sigma, Venture Capital, Negotiation, Systems Engineering, Product Development
Education
Phoenix School of Law 2005 — 2008
JD, Intellectual Property
UNH School of Law 2008 — 2008
None, Intellectual Property Law
Valparaiso University 1980 — 1984
BS, Mechanical Engineering
The University of Arizona June 2013 - Present
Honeywell Aerospace October 2005 - June 2013
Honeywell Aerospace January 1987 - October 2005
Cadence Design Systems 2000 - 2002
Trimble Navigation 1999 - 2000
Parker Hannifin 1984 - 1986
Skills
Intellectual Property, Licensing, Contract Negotiation, Patents, Engineering, Aerospace, Technology Transfer, Business Strategy, Licensing Negotiations, Licensing Strategy, IP transactions, Manufacturing Agreements, Intellectual Property..., Legal Writing, Legal Compliance, Mergers & Acquisitions, Cross-functional Team..., Engineering Management, Start-ups, Business Development, Copyright Law, Strategy, Electronics, Six Sigma, Venture Capital, Negotiation, Systems Engineering, Product Development
Education
Phoenix School of Law 2005 — 2008
JD, Intellectual Property
UNH School of Law 2008 — 2008
None, Intellectual Property Law
Valparaiso University 1980 — 1984
BS, Mechanical Engineering
Vladimir Uzelac Vladimir Uzelac's Cadence Design Systems Experience April 2013 - Present
Job Principal Design Engineer at Cadence Design Systems, RTOS & Debuggers team
Industry Computer Software
Experience
Cadence Design Systems April 2013 - Present
Tensilica May 2010 - Present
University of Alabama in Huntsville August 2006 - May 2010
Tensilica May 2009 - September 2009
ELSYS Eastern Europe March 2006 - July 2006
HDL Design House February 2003 - February 2006
Texas Instruments 2005 - 2005
Skills
Verilog, FPGA, C, Xtensa, Computer Architecture, ARM, Electronics, Debuggers, ASIC, Microcontrollers, VHDL
Education
University of Alabama in Huntsville 2006 — 2010
PhD, Computer Engineering
University of Belgrade 1996 — 2002
Dipl. Ing., Electrical Engineer
Cadence Design Systems April 2013 - Present
Tensilica May 2010 - Present
University of Alabama in Huntsville August 2006 - May 2010
Tensilica May 2009 - September 2009
ELSYS Eastern Europe March 2006 - July 2006
HDL Design House February 2003 - February 2006
Texas Instruments 2005 - 2005
Skills
Verilog, FPGA, C, Xtensa, Computer Architecture, ARM, Electronics, Debuggers, ASIC, Microcontrollers, VHDL
Education
University of Alabama in Huntsville 2006 — 2010
PhD, Computer Engineering
University of Belgrade 1996 — 2002
Dipl. Ing., Electrical Engineer
Jizhe ZHANG Jizhe ZHANG's Cadence Design Systems Experience May 2015 - August 2015
Job Ph.D. student at University of Southern California
Industry Computer Hardware
Experience
University of Southern California January 2013 - Present
University of Southern California January 2013 - Present
Cadence Design Systems May 2015 - August 2015
University of Southern California August 2011 - December 2012
Skills
Verilog, Statistical Modeling, R, Cadence Virtuoso, Matlab, C++, Python, SRAM, Cadence Spectre
Education
USC 2011 — 2017
Doctor of Philosophy (PhD), Electrical and Electronics Engineering, GPA 4.0/4.0
Tsinghua University 2007 — 2011
Bachelor of Engineering (BE), Automatic Control
University of Southern California January 2013 - Present
University of Southern California January 2013 - Present
Cadence Design Systems May 2015 - August 2015
University of Southern California August 2011 - December 2012
Skills
Verilog, Statistical Modeling, R, Cadence Virtuoso, Matlab, C++, Python, SRAM, Cadence Spectre
Education
USC 2011 — 2017
Doctor of Philosophy (PhD), Electrical and Electronics Engineering, GPA 4.0/4.0
Tsinghua University 2007 — 2011
Bachelor of Engineering (BE), Automatic Control
Brandon Dominguez, ARM Brandon Dominguez, ARM's Cadence Design Systems Experience January 2000 - May 2001
Job
Industry Insurance
Experience
FM Global July 2011 - February 2013
FM Global July 2010 - July 2011
FM Global February 2006 - July 2010
FM Global December 2002 - February 2006
Corillian June 2001 - July 2002
Cadence Design Systems January 2000 - May 2001
WaferTech July 1999 - January 2000
United States Navy May 1994 - June 1999
Skills
Property & Casualty..., Risk Management, Insurance, Engineering
Education
Navy Nuclear Power School Officer Course 1996 — 1997
United States Naval Academy 1990 — 1994
BS
FM Global July 2011 - February 2013
FM Global July 2010 - July 2011
FM Global February 2006 - July 2010
FM Global December 2002 - February 2006
Corillian June 2001 - July 2002
Cadence Design Systems January 2000 - May 2001
WaferTech July 1999 - January 2000
United States Navy May 1994 - June 1999
Skills
Property & Casualty..., Risk Management, Insurance, Engineering
Education
Navy Nuclear Power School Officer Course 1996 — 1997
United States Naval Academy 1990 — 1994
BS
Michel Bernier Michel Bernier's Cadence Design Systems Experience February 2001 - November 2008
Job Account Executive, Services at Microsoft
Industry Information Technology and Services
Experience
Microsoft July 2015 - Present
Microsoft December 2012 - Present
Microsoft December 2008 - December 2012
Cadence Design Systems February 2001 - November 2008
Conceptis Technologies 2000 - 2001
IBM Canada 1997 - 2000
IBM Canada 1985 - 1997
Skills
Account Management, Business Strategy, Consulting, Negotiation, Software, Leadership, Solution Selling, Enterprise Software, SaaS, Cloud Computing, Sales Process, Strategic Partnerships
Education
Université de Sherbrooke 1989 — 1990
DESS, Management
Université de Montréal - Ecole polytechnique de Montréal 1981 — 1985
B.ING, Industrial Engineering
Microsoft July 2015 - Present
Microsoft December 2012 - Present
Microsoft December 2008 - December 2012
Cadence Design Systems February 2001 - November 2008
Conceptis Technologies 2000 - 2001
IBM Canada 1997 - 2000
IBM Canada 1985 - 1997
Skills
Account Management, Business Strategy, Consulting, Negotiation, Software, Leadership, Solution Selling, Enterprise Software, SaaS, Cloud Computing, Sales Process, Strategic Partnerships
Education
Université de Sherbrooke 1989 — 1990
DESS, Management
Université de Montréal - Ecole polytechnique de Montréal 1981 — 1985
B.ING, Industrial Engineering
Michael Pepe Michael Pepe's Cadence Design Systems Experience October 1995 - March 1999
Job Senior Account Executive Teradata
Industry Information Technology and Services
Experience
Teradata September 2013 - Present
Open Text January 2007 - April 2013
CSC Consulting January 2001 - February 2002
European Semiconductor Manufacturing, Ltd. January 2000 - December 2000
Cadence Design Systems October 1995 - March 1999
StorageTek / Network Systems Corporation April 1993 - September 1995
Electronic Data Systems June 1981 - March 1993
Education
State University of New York at Albany 1977 — 1981
BS/BA, Management Information Systems and Computer Science
Teradata September 2013 - Present
Open Text January 2007 - April 2013
CSC Consulting January 2001 - February 2002
European Semiconductor Manufacturing, Ltd. January 2000 - December 2000
Cadence Design Systems October 1995 - March 1999
StorageTek / Network Systems Corporation April 1993 - September 1995
Electronic Data Systems June 1981 - March 1993
Education
State University of New York at Albany 1977 — 1981
BS/BA, Management Information Systems and Computer Science
Stuart Bush Stuart Bush's Cadence Design Systems Experience January 1998 - January 1999
Job
Industry Capital Markets
Experience
Consist Capital April 2011 - Present
RBC Capital Markets January 2004 - April 2011
Thomas Weisel Partners June 2001 - August 2001
Robertson Stephens January 1999 - September 1999
Cadence Design Systems January 1998 - January 1999
Synopsys June 1995 - December 1997
Skills
Valuation, Hedge Funds, Equity Research, Capital Markets, Solar Energy, Investment Banking, Equities, Financial Modeling, Private Equity, ETFs, Alternative Energy, Indexing, IPO, Due Diligence, Equity Valuation, Portfolio Management, Equity Capital Markets, Bloomberg, Investment Management
Education
University of California at Berkeley 2000 — 2002
MBA, Business
Yale University 1991 — 1995
BSEE, Electrical Engineering
Consist Capital April 2011 - Present
RBC Capital Markets January 2004 - April 2011
Thomas Weisel Partners June 2001 - August 2001
Robertson Stephens January 1999 - September 1999
Cadence Design Systems January 1998 - January 1999
Synopsys June 1995 - December 1997
Skills
Valuation, Hedge Funds, Equity Research, Capital Markets, Solar Energy, Investment Banking, Equities, Financial Modeling, Private Equity, ETFs, Alternative Energy, Indexing, IPO, Due Diligence, Equity Valuation, Portfolio Management, Equity Capital Markets, Bloomberg, Investment Management
Education
University of California at Berkeley 2000 — 2002
MBA, Business
Yale University 1991 — 1995
BSEE, Electrical Engineering
Roxan Saint-Hilaire Roxan Saint-Hilaire's Cadence Design Systems Experience July 2014 - Present
Job AE Director at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2014 - Present
Skills
EDA, Functional Verification, UVM, SystemVerilog, Presentations, Sales Presentations, Technical Presentations, Solution Selling, Account Management, Consulting, Pre-Sales Technical..., Mixed Signal, Enterprise Software, Debugging, ASIC, SoC, Semiconductors, Processors, Specman, Simulations, Low-power Design, Qualifying Opportunities
Education
University of California, Berkeley - Walter A. Haas School of Business 2008 — 2011
MBA
Université de Montréal - Ecole polytechnique de Montréal 1995 — 1999
B. Sc.
Cadence Design Systems July 2014 - Present
Skills
EDA, Functional Verification, UVM, SystemVerilog, Presentations, Sales Presentations, Technical Presentations, Solution Selling, Account Management, Consulting, Pre-Sales Technical..., Mixed Signal, Enterprise Software, Debugging, ASIC, SoC, Semiconductors, Processors, Specman, Simulations, Low-power Design, Qualifying Opportunities
Education
University of California, Berkeley - Walter A. Haas School of Business 2008 — 2011
MBA
Université de Montréal - Ecole polytechnique de Montréal 1995 — 1999
B. Sc.
Housseine Rejouan Housseine Rejouan's Cadence Design Systems Experience April 2003 - September 2003
Job Software Architect, R&D at Atrenta Inc.
Industry Computer Software
Experience
Atrenta Inc. June 2006 - Present
Synplicity April 2004 - June 2006
Mentor Graphics September 2003 - April 2004
Cadence Design Systems April 2003 - September 2003
Get2Chip.com March 2001 - April 2003
Lattice Semiconductor January 1999 - March 2001
Skills
EDA, SoC, TCL, ASIC, Verilog, FPGA, Debugging, Algorithms, Semiconductors, Linux, Static Timing Analysis, Logic Synthesis, Unix
Education
Université Pierre et Marie Curie (Paris VI) 1985 — 1997
Ph.D., Electrical Engineering And Computer Science, "Built-In Self-Test VLSI Architecture"
Atrenta Inc. June 2006 - Present
Synplicity April 2004 - June 2006
Mentor Graphics September 2003 - April 2004
Cadence Design Systems April 2003 - September 2003
Get2Chip.com March 2001 - April 2003
Lattice Semiconductor January 1999 - March 2001
Skills
EDA, SoC, TCL, ASIC, Verilog, FPGA, Debugging, Algorithms, Semiconductors, Linux, Static Timing Analysis, Logic Synthesis, Unix
Education
Université Pierre et Marie Curie (Paris VI) 1985 — 1997
Ph.D., Electrical Engineering And Computer Science, "Built-In Self-Test VLSI Architecture"
Cho Moon Cho Moon's Cadence Design Systems Experience October 1996 - October 2004
Job R&D Manager at Synopsys
Industry Computer Software
Experience
Synopsys March 2009 - Present
Atrenta June 2007 - January 2009
Blaze DFM October 2004 - May 2007
Cadence Design Systems October 1996 - October 2004
Lattice Semiconductor November 1992 - October 1996
Skills
EDA, Static Timing Analysis, Physical Design, TCL, Logic Synthesis, SoC, Awk, Formal Verification, DFT
Education
University of California, Berkeley 1988 — 1992
Ph.D., EECS
University of California, Berkeley 1985 — 1988
M.S., EECS
University of California, Berkeley 1981 — 1985
B.S., EECS and Materials Science (Double Major)
Synopsys March 2009 - Present
Atrenta June 2007 - January 2009
Blaze DFM October 2004 - May 2007
Cadence Design Systems October 1996 - October 2004
Lattice Semiconductor November 1992 - October 1996
Skills
EDA, Static Timing Analysis, Physical Design, TCL, Logic Synthesis, SoC, Awk, Formal Verification, DFT
Education
University of California, Berkeley 1988 — 1992
Ph.D., EECS
University of California, Berkeley 1985 — 1988
M.S., EECS
University of California, Berkeley 1981 — 1985
B.S., EECS and Materials Science (Double Major)
Lauren Moriarty Lauren Moriarty's Cadence Design Systems Experience June 1996 - January 2000
Job Digital design and Verification Engineer at Chaparral Design
Industry Computer Hardware
Experience
NXP Semiconductors June 2010 - October 2013
Qualcomm December 2007 - December 2008
NXP Semiconductors December 2006 - December 2007
Sigmatel January 2005 - January 2006
ADI 2004 - 2006
Analog Devices 2001 - February 2002
Qualis Design Corporation 2000 - 2001
Cadence Design Systems June 1996 - January 2000
Texas Instruments 1975 - 1995
Education
University of California, Berkeley 1970 — 1975
NXP Semiconductors June 2010 - October 2013
Qualcomm December 2007 - December 2008
NXP Semiconductors December 2006 - December 2007
Sigmatel January 2005 - January 2006
ADI 2004 - 2006
Analog Devices 2001 - February 2002
Qualis Design Corporation 2000 - 2001
Cadence Design Systems June 1996 - January 2000
Texas Instruments 1975 - 1995
Education
University of California, Berkeley 1970 — 1975
Tom Katsioulas's Cadence Design Systems Experience 1993 - 1998
Job Technology Executive | Marketing & Business Development Leader who Delivers Rapid Growth
Industry Computer Software
Experience
Runtime Design Automation 2012 - 2015
Up and to the Right Consulting, Inc. 2006 - 2012
Forte Design Systems 2004 - 2006
Archon Design Solutions, Inc. 2002 - 2004
AmmoCore Technology, Inc. 1999 - 2002
Synopsys Corporation 1998 - 1999
Cadence Design Systems 1993 - 1998
Various Companies 1985 - 1993
Skills
Strategic Partnerships, Start-ups, Semiconductors, Business Strategy, Strategy, EDA, Consulting, ASIC, Cross-functional Team..., Business Planning, Go-to-market Strategy, Product Management, Marketing Strategy, Business Development, Product Development, SoC, IP, Product Marketing, Executive Management, Cloud Computing, New Business Development, Venture Capital, Enterprise Software, Mobile Devices, IC, FPGA, SaaS, Leadership, Mergers & Acquisitions, Integration, Product Lifecycle..., Marketing Management, Sales Management, Solution Selling, M&A experience, Embedded Systems, Mobile Applications, Change Management, Value Propositions, Platform Development, Enterprise Content..., Strategic Planning, Business Turn-arounds, Global Business..., Profit Maximization, Market Development, Relationship Building, Collaboration Solutions, Solutions Marketing, Big Data
Education
University of California, Berkeley
Associate's Degree, Marketing
University of Massachusetts, Amherst
Master's degree, Electrical Engineering & Computer Science
University of Bridgeport
Bachelor's Degree, Computer Engineering
Runtime Design Automation 2012 - 2015
Up and to the Right Consulting, Inc. 2006 - 2012
Forte Design Systems 2004 - 2006
Archon Design Solutions, Inc. 2002 - 2004
AmmoCore Technology, Inc. 1999 - 2002
Synopsys Corporation 1998 - 1999
Cadence Design Systems 1993 - 1998
Various Companies 1985 - 1993
Skills
Strategic Partnerships, Start-ups, Semiconductors, Business Strategy, Strategy, EDA, Consulting, ASIC, Cross-functional Team..., Business Planning, Go-to-market Strategy, Product Management, Marketing Strategy, Business Development, Product Development, SoC, IP, Product Marketing, Executive Management, Cloud Computing, New Business Development, Venture Capital, Enterprise Software, Mobile Devices, IC, FPGA, SaaS, Leadership, Mergers & Acquisitions, Integration, Product Lifecycle..., Marketing Management, Sales Management, Solution Selling, M&A experience, Embedded Systems, Mobile Applications, Change Management, Value Propositions, Platform Development, Enterprise Content..., Strategic Planning, Business Turn-arounds, Global Business..., Profit Maximization, Market Development, Relationship Building, Collaboration Solutions, Solutions Marketing, Big Data
Education
University of California, Berkeley
Associate's Degree, Marketing
University of Massachusetts, Amherst
Master's degree, Electrical Engineering & Computer Science
University of Bridgeport
Bachelor's Degree, Computer Engineering
Nicola Goulding's Cadence Design Systems Experience September 2012 - September 2014
Job Senior Consultant at CrossCountry Consulting
Industry Accounting
Experience
CrossCountry Consulting October 2014 - Present
Cadence Design Systems September 2012 - September 2014
KPMG in Ireland 2008 - 2012
Skills
IFRS, Advanced Microsoft..., Intermediate Microsoft..., Proficient at various..., Excellent communication..., Ability to work..., Ability to work in..., Strong leadership skills, Proficient in Spanish, Auditing, Financial Accounting, SAP, Mergers & Acquisitions, US GAAP, Sarbanes-Oxley Act, Financial Reporting, Internal Controls
Education
University College Cork 2004 — 2008
B.Comm (Hons) International Degree with Hispanic Studies, Coursework: Accounting, Management, Business Economics, Mathematics, Spanish Language and Literature, 1st Class Honours Degree (4.0 GPA equivalent)
Universidad de Alcalá 2006 — 2007
Erasmus Exchange Year: European Business and Spanish Focus
Institute of Chartered Accountants in Ireland
1st time pass, with a ranking in the top 10% of results in Ireland
CrossCountry Consulting October 2014 - Present
Cadence Design Systems September 2012 - September 2014
KPMG in Ireland 2008 - 2012
Skills
IFRS, Advanced Microsoft..., Intermediate Microsoft..., Proficient at various..., Excellent communication..., Ability to work..., Ability to work in..., Strong leadership skills, Proficient in Spanish, Auditing, Financial Accounting, SAP, Mergers & Acquisitions, US GAAP, Sarbanes-Oxley Act, Financial Reporting, Internal Controls
Education
University College Cork 2004 — 2008
B.Comm (Hons) International Degree with Hispanic Studies, Coursework: Accounting, Management, Business Economics, Mathematics, Spanish Language and Literature, 1st Class Honours Degree (4.0 GPA equivalent)
Universidad de Alcalá 2006 — 2007
Erasmus Exchange Year: European Business and Spanish Focus
Institute of Chartered Accountants in Ireland
1st time pass, with a ranking in the top 10% of results in Ireland
Bruce Kinmonth Bruce Kinmonth's Cadence Design Systems Experience September 2015 - Present
Job Principal Software Engineer at Cadence Design Systems
Industry Research
Experience
Cadence Design Systems September 2015 - Present
Intel Labs August 2001 - April 2014
Compaq 1998 - August 2001
Digital Equipment Corporation January 1980 - 1998
Skills
Tcl-Tk, PHP, HTML, MySQL, GUI development, Compilers, Layout Tools, Linux, Scripting, Music, Genealogy
Education
University of Massachusetts, Amherst
Master of Science (MS), Computer and Information Sciences, General
Trinity College-Hartford
Bachelor of Science (BS), Computer and Electrical Engineering
Cadence Design Systems September 2015 - Present
Intel Labs August 2001 - April 2014
Compaq 1998 - August 2001
Digital Equipment Corporation January 1980 - 1998
Skills
Tcl-Tk, PHP, HTML, MySQL, GUI development, Compilers, Layout Tools, Linux, Scripting, Music, Genealogy
Education
University of Massachusetts, Amherst
Master of Science (MS), Computer and Information Sciences, General
Trinity College-Hartford
Bachelor of Science (BS), Computer and Electrical Engineering
Steven Gartner Steven Gartner's Cadence Design Systems Experience June 1996 - November 2008
Job ASICs, IC Design and Layout Services
Industry Semiconductors
Experience
Huawei Technologies June 2015 - Present
ANSYS, Inc. February 2013 - January 2014
Hoodz of the North Shore July 2010 - September 2013
Sensiics December 2009 - February 2011
Wenesco September 2009 - December 2009
ClioSoft, Inc. February 2009 - October 2009
Cadence Design Systems June 1996 - November 2008
Motorola Semiconductor April 1995 - June 1996
Intersil January 1993 - April 1995
Harris Semiconductor 1990 - January 1993
Skills
Mixed Signal IC Designer, Account Management, Idea Generation, Semiconductors, EDA, Solution Selling, Analog, Start-ups, IC, Mixed Signal, ASIC, Integrated Circuit..., Electronics, CMOS, Sales Process, Leadership, Program Management, Testing, Circuit Design, Debugging, Sales, RF, Engineering Management, Embedded Software, Telecommunications, Microprocessors, SoC, Selling, Management, Product Marketing, Go-to-market Strategy, Product Management, Wireless
Education
University of Illinois at Chicago 1986 — 1989
BSEE, Communication Systems and Semiconductor Design
University of Arizona 1979 — 1983
Aerospace Engineering, Rocket Science
New Trier West High School
Huawei Technologies June 2015 - Present
ANSYS, Inc. February 2013 - January 2014
Hoodz of the North Shore July 2010 - September 2013
Sensiics December 2009 - February 2011
Wenesco September 2009 - December 2009
ClioSoft, Inc. February 2009 - October 2009
Cadence Design Systems June 1996 - November 2008
Motorola Semiconductor April 1995 - June 1996
Intersil January 1993 - April 1995
Harris Semiconductor 1990 - January 1993
Skills
Mixed Signal IC Designer, Account Management, Idea Generation, Semiconductors, EDA, Solution Selling, Analog, Start-ups, IC, Mixed Signal, ASIC, Integrated Circuit..., Electronics, CMOS, Sales Process, Leadership, Program Management, Testing, Circuit Design, Debugging, Sales, RF, Engineering Management, Embedded Software, Telecommunications, Microprocessors, SoC, Selling, Management, Product Marketing, Go-to-market Strategy, Product Management, Wireless
Education
University of Illinois at Chicago 1986 — 1989
BSEE, Communication Systems and Semiconductor Design
University of Arizona 1979 — 1983
Aerospace Engineering, Rocket Science
New Trier West High School
Ken Slattery Ken Slattery's Cadence Design Systems Experience October 2000 - January 2001
Job Senior Information Developer at Kenandy, Inc.
Industry Writing and Editing
Experience
Kenandy, Inc. January 2015 - Present
Granicus, Inc. October 2012 - December 2014
IST Inc November 2006 - July 2012
Interactive Services May 2006 - August 2006
BEA Systems May 2004 - December 2005
Qantel Technologies February 2001 - April 2004
Cadence Design Systems October 2000 - January 2001
Skills
Online Help, Manuals, Software Documentation, Release Notes, Tutorials, Technical Documentation, FrameMaker, Editing, Technical Communication, Adobe Acrobat, Technical Writing, Content Management, Captivate, Content Development, HTML, Usability
Education
University of Limerick 1999 — 2000
Graduate Diploma in Technical Communication, Technical Communication
University of Limerick 1999 — 2000
Graduate Diploma, Technical Writing
Trinity College 1992 — 1996
B.A. (Hons), Drama Studies and Sociology
Trinity College, Dublin 1992 — 1996
Drama and Sociology, Theatre Studies, Sociology
Kenandy, Inc. January 2015 - Present
Granicus, Inc. October 2012 - December 2014
IST Inc November 2006 - July 2012
Interactive Services May 2006 - August 2006
BEA Systems May 2004 - December 2005
Qantel Technologies February 2001 - April 2004
Cadence Design Systems October 2000 - January 2001
Skills
Online Help, Manuals, Software Documentation, Release Notes, Tutorials, Technical Documentation, FrameMaker, Editing, Technical Communication, Adobe Acrobat, Technical Writing, Content Management, Captivate, Content Development, HTML, Usability
Education
University of Limerick 1999 — 2000
Graduate Diploma in Technical Communication, Technical Communication
University of Limerick 1999 — 2000
Graduate Diploma, Technical Writing
Trinity College 1992 — 1996
B.A. (Hons), Drama Studies and Sociology
Trinity College, Dublin 1992 — 1996
Drama and Sociology, Theatre Studies, Sociology
Sathishkumar Balasubramanian Sathishkumar Balasubramanian's Cadence Design Systems Experience May 2012 - February 2014
Job Experienced Marketing and Product Executive Berkeley MBA
Industry Semiconductors
Experience
Synopsys February 2014 - Present
Cadence Design Systems May 2012 - February 2014
Dow Venture Capital May 2012 - August 2012
Cadence Design Systems March 2011 - July 2012
Oasys Design Systems January 2010 - March 2011
Cadence Design Systems April 2008 - December 2009
Cadence Design Systems January 2006 - December 2009
Cadence Design Systems January 2001 - December 2005
Synopsys Inc May 2000 - September 2000
Skills
SoC, IC, Semiconductors, Product Strategy, EDA, Product Marketing, International Sales, Competitive Marketing..., Competitive Analysis, Strategic Planning, Corporate Blogging, Mixed Signal, ASIC, Cross-functional Team..., Go-to-market Strategy, Product Launch, Awesomeness, Product Management, Low-power Design, Market Analysis, Mobile Devices, Simulations, Enterprise Software, Product Lifecycle..., ARM, Lead Generation, Management, FPGA, Market Research, Embedded Systems, Analog, Microprocessors, VHDL, Technical Marketing, Verilog, Business Development, Wireless, SaaS, Semiconductor Industry, Strategic Partnerships, Consumer Electronics, Sales Enablement, Leadership, Strategy
Education
University of California, Berkeley - Walter A. Haas School of Business
MBA, Marketing & Strategy
University of Alabama in Huntsville
Masters in ECE, Electrical & Computer Engineering
University of Madras
Bachelor of Engineering, Electronics & Communication
Sindhi Model School
High School
Synopsys February 2014 - Present
Cadence Design Systems May 2012 - February 2014
Dow Venture Capital May 2012 - August 2012
Cadence Design Systems March 2011 - July 2012
Oasys Design Systems January 2010 - March 2011
Cadence Design Systems April 2008 - December 2009
Cadence Design Systems January 2006 - December 2009
Cadence Design Systems January 2001 - December 2005
Synopsys Inc May 2000 - September 2000
Skills
SoC, IC, Semiconductors, Product Strategy, EDA, Product Marketing, International Sales, Competitive Marketing..., Competitive Analysis, Strategic Planning, Corporate Blogging, Mixed Signal, ASIC, Cross-functional Team..., Go-to-market Strategy, Product Launch, Awesomeness, Product Management, Low-power Design, Market Analysis, Mobile Devices, Simulations, Enterprise Software, Product Lifecycle..., ARM, Lead Generation, Management, FPGA, Market Research, Embedded Systems, Analog, Microprocessors, VHDL, Technical Marketing, Verilog, Business Development, Wireless, SaaS, Semiconductor Industry, Strategic Partnerships, Consumer Electronics, Sales Enablement, Leadership, Strategy
Education
University of California, Berkeley - Walter A. Haas School of Business
MBA, Marketing & Strategy
University of Alabama in Huntsville
Masters in ECE, Electrical & Computer Engineering
University of Madras
Bachelor of Engineering, Electronics & Communication
Sindhi Model School
High School
Thiago Radicchi Thiago Radicchi's Cadence Design Systems Experience June 2014 - Present
Job Senior Principal Software Engineer na Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems June 2014 - Present
Jasper Design Automation January 2012 - June 2014
Jasper Design Automation July 2004 - January 2012
UFMG February 2001 - November 2004
Skills
Linux, Solaris, Verilog, Java, Perl, Shell Scripting, TCL, Bash, Algorithms, C, C++, Unix, Computer Science, Software Engineering, Programming, Software Development, VHDL, Debugging, Formal Verification, RTL design, Computer Architecture, Embedded Systems, Object Oriented Design, EDA, DNS, Network Administration, OOP, Operating Systems, SystemVerilog, Functional Verification, Hardware, Unix Shell Scripting, Hardware Architecture, CentOS, Multithreading, Distributed Systems, Shell script
Education
Universidade Federal de Minas Gerais 2004 — 2007
MSc, Computer Science, Formal Verification
Universidade Federal de Minas Gerais 2000 — 2003
BSc, Computer Science
Cadence Design Systems June 2014 - Present
Jasper Design Automation January 2012 - June 2014
Jasper Design Automation July 2004 - January 2012
UFMG February 2001 - November 2004
Skills
Linux, Solaris, Verilog, Java, Perl, Shell Scripting, TCL, Bash, Algorithms, C, C++, Unix, Computer Science, Software Engineering, Programming, Software Development, VHDL, Debugging, Formal Verification, RTL design, Computer Architecture, Embedded Systems, Object Oriented Design, EDA, DNS, Network Administration, OOP, Operating Systems, SystemVerilog, Functional Verification, Hardware, Unix Shell Scripting, Hardware Architecture, CentOS, Multithreading, Distributed Systems, Shell script
Education
Universidade Federal de Minas Gerais 2004 — 2007
MSc, Computer Science, Formal Verification
Universidade Federal de Minas Gerais 2000 — 2003
BSc, Computer Science
Bill Hobson Bill Hobson's Cadence Design Systems Experience 2008 - 2009
Job Independent Computer Software & Electronics Professional
Industry Computer Software
Experience
Coupa Software 2014 - Present
Servio (Acquired by CrowdSource) 2013 - 2014
Servio 2013 - 2013
Cadence Design Systems 2008 - 2009
TheGreatEvent.com 2002 - 2006
CoWare Incorporated 2000 - 2001
Cadence Design Systems 1992 - 2000
Valid Logic Systems 1988 - 1992
Silvar-Lisco September 1986 - August 1988
California Devices August 1983 - August 1986
Skills
EDA, C++, Software Development, Software Design, ASIC, Verilog, Circuit Simulation, Electrical Engineering, Java, Git, Ruby on Rails, Unix, Testing, SQL
Education
University of California, Berkeley 1979 — 1982
BSEE, Electrical Engineering
Coupa Software 2014 - Present
Servio (Acquired by CrowdSource) 2013 - 2014
Servio 2013 - 2013
Cadence Design Systems 2008 - 2009
TheGreatEvent.com 2002 - 2006
CoWare Incorporated 2000 - 2001
Cadence Design Systems 1992 - 2000
Valid Logic Systems 1988 - 1992
Silvar-Lisco September 1986 - August 1988
California Devices August 1983 - August 1986
Skills
EDA, C++, Software Development, Software Design, ASIC, Verilog, Circuit Simulation, Electrical Engineering, Java, Git, Ruby on Rails, Unix, Testing, SQL
Education
University of California, Berkeley 1979 — 1982
BSEE, Electrical Engineering
Luca Ravezzi Luca Ravezzi's Cadence Design Systems Experience May 2000 - July 2003
Job Distinguished Engineer at Applied Micro
Industry Semiconductors
Experience
AppliedMicro July 2009 - Present
AMD January 2009 - July 2009
Qimonda NA July 2006 - December 2008
Infineon Technologies July 2003 - July 2006
Cadence Design systems May 2000 - July 2003
Fondazione Bruno Kessler (FBK-irst) November 1999 - May 2000
Skills
Analog, Mixed Signal..., High Speed Data..., EDA: Cadence, Synopsys,..., Languages: Python,..., Mathematical Modeling..., Mixed Signal, Analog, Data Conversion, Verilog-A, EDA, High Speed Clock..., Scripting: Python, Skill, Microprocessors, CMOS, VLSI, Signal Integrity, SoC, IC, Circuit Design, FPGA, Digital Signal..., Semiconductors, Electronics
Education
Università degli Studi di Trento 1996 — 1999
Ph.D., Electronics
Università di Bologna 1990 — 1996
Master in Electronic Engineering, Electronic Engineer
AppliedMicro July 2009 - Present
AMD January 2009 - July 2009
Qimonda NA July 2006 - December 2008
Infineon Technologies July 2003 - July 2006
Cadence Design systems May 2000 - July 2003
Fondazione Bruno Kessler (FBK-irst) November 1999 - May 2000
Skills
Analog, Mixed Signal..., High Speed Data..., EDA: Cadence, Synopsys,..., Languages: Python,..., Mathematical Modeling..., Mixed Signal, Analog, Data Conversion, Verilog-A, EDA, High Speed Clock..., Scripting: Python, Skill, Microprocessors, CMOS, VLSI, Signal Integrity, SoC, IC, Circuit Design, FPGA, Digital Signal..., Semiconductors, Electronics
Education
Università degli Studi di Trento 1996 — 1999
Ph.D., Electronics
Università di Bologna 1990 — 1996
Master in Electronic Engineering, Electronic Engineer
Jonathan Hicks Jonathan Hicks's Cadence Design Systems Experience February 2013 - Present
Job Sr. Corporate Counsel
Industry Law Practice
Experience
Cadence Design Systems February 2013 - Present
Hoge Fenton Jones & Appel May 2006 - January 2013
Skills
Litigation, Health Law, Trade Secrets, Corporate Law, Appeals, Legal Research, Legal Writing, Depositions, Arbitration, Civil Litigation, Employment Law
Education
USC Gould School of Law 2001 — 2004
Doctor of Law (J.D.)
University of California, Berkeley
BA, Political Science
Cadence Design Systems February 2013 - Present
Hoge Fenton Jones & Appel May 2006 - January 2013
Skills
Litigation, Health Law, Trade Secrets, Corporate Law, Appeals, Legal Research, Legal Writing, Depositions, Arbitration, Civil Litigation, Employment Law
Education
USC Gould School of Law 2001 — 2004
Doctor of Law (J.D.)
University of California, Berkeley
BA, Political Science
Arun Gopalakrishnan Arun Gopalakrishnan's Cadence Design Systems Experience July 2000 - March 2003
Job Product Developer
Industry Computer Software
Experience
Q Point Technology, Inc. August 2011 - Present
Arena Solutions March 2008 - August 2011
Arena Solutions December 2005 - March 2008
Arena Solutions March 2003 - December 2005
Cadence Design Systems July 2000 - March 2003
OrCAD 1997 - 2000
Q Point Technology August 1996 - October 1997
CSWL February 1994 - August 1997
Skills
Enterprise Software, SaaS, Product Development, Product Integration, Entrepreneurship, Software Development
Education
University of Calicut 1986 — 1990
B.S, Computer Science
Q Point Technology, Inc. August 2011 - Present
Arena Solutions March 2008 - August 2011
Arena Solutions December 2005 - March 2008
Arena Solutions March 2003 - December 2005
Cadence Design Systems July 2000 - March 2003
OrCAD 1997 - 2000
Q Point Technology August 1996 - October 1997
CSWL February 1994 - August 1997
Skills
Enterprise Software, SaaS, Product Development, Product Integration, Entrepreneurship, Software Development
Education
University of Calicut 1986 — 1990
B.S, Computer Science
Jamie Metcalfe Jamie Metcalfe's Cadence Design Systems Experience 1996 - 2006
Job Hitech Marketing and Business Development
Industry Computer Software
Experience
Mentor Graphics 2008 - Present
Optimal Corporation 2006 - 2007
Cadence Design Systems 1996 - 2006
Mentor Graphics 1986 - 1996
Skills
Product Marketing, EDA, IC, Product Management, Product Lifecycle..., PCB design, Enterprise Software, Executive Management, Microcontrollers, ASIC, Semiconductors, Business Development, VAR recruitment, Channel Relationships, Go-to-market Strategy, Strategic Partnerships, Lead Generation, Competitive Analysis, Demand Generation, Product Planning, Marketing Strategy
Education
Birmingham University 1977 — 1980
BSc
Mentor Graphics 2008 - Present
Optimal Corporation 2006 - 2007
Cadence Design Systems 1996 - 2006
Mentor Graphics 1986 - 1996
Skills
Product Marketing, EDA, IC, Product Management, Product Lifecycle..., PCB design, Enterprise Software, Executive Management, Microcontrollers, ASIC, Semiconductors, Business Development, VAR recruitment, Channel Relationships, Go-to-market Strategy, Strategic Partnerships, Lead Generation, Competitive Analysis, Demand Generation, Product Planning, Marketing Strategy
Education
Birmingham University 1977 — 1980
BSc
Ahmad T. Ahdab Ahmad T. Ahdab's Cadence Design Systems Experience February 1998 - November 1998
Job CEO, Razi Education
Industry Semiconductors
Experience
Razi Education October 2007 - Present
Convergence Devices Inc. August 2008 - March 2010
inVu Semiconductor Corp. June 2004 - June 2006
Pixelworks, formerly Jaldi Semiconductor July 2000 - October 2003
Genesis Microchip December 1998 - July 2000
Cadence Design Systems February 1998 - November 1998
Silcom Technology Inc. February 1995 - November 1997
ATI Technologies Inc. June 1992 - February 1995
Mitel Semiconductor (now Zarlink) January 1984 - June 1992
University of Ottawa January 1981 - November 1983
Skills
SoC, CMOS, ASIC, IC, Sensors, Circuit Design, Security, Leadership, Team Building, Training, System Design, Hardware, Consumer Electronics, Consulting, Mergers & Acquisitions, Strategic Partnerships, RF, Strategy, Product Management, Start-ups, EDA, Project Management, Integrated Circuit..., Management, Telecommunications, Executive Management
Education
University of Ottawa
M.A.Sc
Université de Montréal - Ecole polytechnique de Montréal
B.Eng.
Razi Education October 2007 - Present
Convergence Devices Inc. August 2008 - March 2010
inVu Semiconductor Corp. June 2004 - June 2006
Pixelworks, formerly Jaldi Semiconductor July 2000 - October 2003
Genesis Microchip December 1998 - July 2000
Cadence Design Systems February 1998 - November 1998
Silcom Technology Inc. February 1995 - November 1997
ATI Technologies Inc. June 1992 - February 1995
Mitel Semiconductor (now Zarlink) January 1984 - June 1992
University of Ottawa January 1981 - November 1983
Skills
SoC, CMOS, ASIC, IC, Sensors, Circuit Design, Security, Leadership, Team Building, Training, System Design, Hardware, Consumer Electronics, Consulting, Mergers & Acquisitions, Strategic Partnerships, RF, Strategy, Product Management, Start-ups, EDA, Project Management, Integrated Circuit..., Management, Telecommunications, Executive Management
Education
University of Ottawa
M.A.Sc
Université de Montréal - Ecole polytechnique de Montréal
B.Eng.
Marc-Olivier Mercier Marc-Olivier Mercier's Cadence Design Systems Experience March 2015 - Present
Job Ingénieur concepteur chez Cadence Design Systems
Industry Electrical/Electronic Manufacturing
Experience
Cadence Design Systems March 2015 - Present
Université de Sherbrooke January 2013 - Present
Micrium Inc. May 2012 - August 2012
Groupe de collaboration international en ingénierie de l'Université de Sherbrooke (GCIUS) September 2011 - December 2011
Nuance Communications January 2011 - April 2011
Cascades January 2010 - April 2010
Cascades May 2009 - August 2009
Skills
Encounter, ModelSim, Cadence Virtuoso, Cadence Skill, Calibre, VHDL, FPGA, Python, Tcl-Tk, Git, Unix Shell Scripting, Verilog, Lisp, Xilinx, VHDL-AMS, Subversion, Altium Designer, ASIC, Linux, Matlab, Scilab, MPLAB, Ubuntu, IAR Embedded Workbench, Eclipse, C, C++, Visual Studio, Code Composer Studio, Java, C#, Microsoft Office, AutoCAD
Education
Université de Sherbrooke 2013 — 2015
Maîtrise de type recherche, Génie électrique
Université de Sherbrooke 2008 — 2012
Baccalauréat, Génie Électrique
Champlain Regional College 2004 — 2007
DEC, Science Nature
Cadence Design Systems March 2015 - Present
Université de Sherbrooke January 2013 - Present
Micrium Inc. May 2012 - August 2012
Groupe de collaboration international en ingénierie de l'Université de Sherbrooke (GCIUS) September 2011 - December 2011
Nuance Communications January 2011 - April 2011
Cascades January 2010 - April 2010
Cascades May 2009 - August 2009
Skills
Encounter, ModelSim, Cadence Virtuoso, Cadence Skill, Calibre, VHDL, FPGA, Python, Tcl-Tk, Git, Unix Shell Scripting, Verilog, Lisp, Xilinx, VHDL-AMS, Subversion, Altium Designer, ASIC, Linux, Matlab, Scilab, MPLAB, Ubuntu, IAR Embedded Workbench, Eclipse, C, C++, Visual Studio, Code Composer Studio, Java, C#, Microsoft Office, AutoCAD
Education
Université de Sherbrooke 2013 — 2015
Maîtrise de type recherche, Génie électrique
Université de Sherbrooke 2008 — 2012
Baccalauréat, Génie Électrique
Champlain Regional College 2004 — 2007
DEC, Science Nature
Carl Long's Cadence Design Systems Experience October 2000 - June 2005
Job Chief Accounting Officer at Intrawest
Industry Accounting
Experience
Intrawest May 2014 - Present
HealthGrades April 2012 - May 2014
DigitalGlobe September 2010 - April 2012
The TriZetto Group May 2007 - August 2010
Mellanox Technologies June 2005 - May 2007
Cadence Design Systems October 2000 - June 2005
PricewaterhouseCoopers July 1996 - October 2000
US Air Force 1992 - 1994
US Air Force 1992 - 1994
Skills
IPO, Technical Accounting, Revenue Recognition, SEC reporting, Public Companies
Education
University of Pittsburgh - Joseph M. Katz Graduate School of Business 1995 — 1996
MBA, Information Technology
United States Air Force Academy 1985 — 1989
BS, Economics
Intrawest May 2014 - Present
HealthGrades April 2012 - May 2014
DigitalGlobe September 2010 - April 2012
The TriZetto Group May 2007 - August 2010
Mellanox Technologies June 2005 - May 2007
Cadence Design Systems October 2000 - June 2005
PricewaterhouseCoopers July 1996 - October 2000
US Air Force 1992 - 1994
US Air Force 1992 - 1994
Skills
IPO, Technical Accounting, Revenue Recognition, SEC reporting, Public Companies
Education
University of Pittsburgh - Joseph M. Katz Graduate School of Business 1995 — 1996
MBA, Information Technology
United States Air Force Academy 1985 — 1989
BS, Economics
Jack Erickson Jack Erickson's Cadence Design Systems Experience August 2010 - February 2014
Job Principal Product Marketing Manager at The MathWorks
Industry Computer Software
Experience
The MathWorks October 2014 - Present
Cadence Design Systems August 2010 - February 2014
Cadence Design Systems April 2006 - August 2010
Cadence Design Systems August 2003 - April 2006
Cadence Design Systems August 1999 - August 2003
Cadence Design Systems April 1995 - August 1999
Skills
Product Marketing, Product Management, Product Launch, Sales Enablement, EDA, Strategic Planning, Competitive Analysis, Go-to-market Strategy, ASIC, SoC, Semiconductors, Strategic Partnerships, Pricing Strategy, Selling Skills, Product Requirements, Solutions Marketing, Social Media, Solution Selling, Technical Marketing, Integrated Circuit..., FPGA, Cross-functional Team..., IC, Marketing Strategy, Demand Generation, Product Development, Verilog, Semiconductor Industry, Power Management, Analog, Launching Of New..., Sales Training, Product Lifecycle..., Strategy, Business Strategy, Enterprise Software, Sales
Education
Worcester Polytechnic Institute 1994 — 1998
Master of Business Administration (MBA), Strategy, marketing
Tufts University 1988 — 1992
Bachelor of Science (BS), Electrical Engineering
The MathWorks October 2014 - Present
Cadence Design Systems August 2010 - February 2014
Cadence Design Systems April 2006 - August 2010
Cadence Design Systems August 2003 - April 2006
Cadence Design Systems August 1999 - August 2003
Cadence Design Systems April 1995 - August 1999
Skills
Product Marketing, Product Management, Product Launch, Sales Enablement, EDA, Strategic Planning, Competitive Analysis, Go-to-market Strategy, ASIC, SoC, Semiconductors, Strategic Partnerships, Pricing Strategy, Selling Skills, Product Requirements, Solutions Marketing, Social Media, Solution Selling, Technical Marketing, Integrated Circuit..., FPGA, Cross-functional Team..., IC, Marketing Strategy, Demand Generation, Product Development, Verilog, Semiconductor Industry, Power Management, Analog, Launching Of New..., Sales Training, Product Lifecycle..., Strategy, Business Strategy, Enterprise Software, Sales
Education
Worcester Polytechnic Institute 1994 — 1998
Master of Business Administration (MBA), Strategy, marketing
Tufts University 1988 — 1992
Bachelor of Science (BS), Electrical Engineering
Jessica Zhang Jessica Zhang's Cadence Design Systems Experience 2000 - 2002
Job Ads, Growth at Facebook
Industry Internet
Experience
Facebook 2013 - Present
SCEA 2009 - Present
Dell 2010 - 2013
SVC Wireless 2010 - 2011
Synopsys 2004 - 2010
US-China Green Energy Council 2008 - January 2009
Magma Design Automation (Acquired by Synopsys) 2003 - 2004
Bay Yellow, Inc. September 2000 - February 2002
Cadence Design Systems 2000 - 2002
Cadence Design Systems 1998 - 2000
Skills
Product Management, Product Marketing, Sales Enablement, MRD, Road Maps, term sheets, Term Sheets, technology investment, M&A, Investment Banking, China Business..., Product Requirements, Technology, Mergers, Market Requirements..., Mergers & Acquisitions, Mobile Devices, Venture Capital, Analytics, SaaS, Android, Enterprise Software, Cloud Computing, Mobile Applications, Cross-functional Team..., Strategic Partnerships, Strategy, Entrepreneurship, Start-ups, Business Intelligence, Program Management, Product Lifecycle..., Product Development, Product Launch, Business Alliances, User Experience, Market Research, Management, Wireless, Leadership, Executive Management, Competitive Analysis, Mobile Technology, E-commerce
Education
University of California, Berkeley
MBA
University of Cincinnati
M.S.
Facebook 2013 - Present
SCEA 2009 - Present
Dell 2010 - 2013
SVC Wireless 2010 - 2011
Synopsys 2004 - 2010
US-China Green Energy Council 2008 - January 2009
Magma Design Automation (Acquired by Synopsys) 2003 - 2004
Bay Yellow, Inc. September 2000 - February 2002
Cadence Design Systems 2000 - 2002
Cadence Design Systems 1998 - 2000
Skills
Product Management, Product Marketing, Sales Enablement, MRD, Road Maps, term sheets, Term Sheets, technology investment, M&A, Investment Banking, China Business..., Product Requirements, Technology, Mergers, Market Requirements..., Mergers & Acquisitions, Mobile Devices, Venture Capital, Analytics, SaaS, Android, Enterprise Software, Cloud Computing, Mobile Applications, Cross-functional Team..., Strategic Partnerships, Strategy, Entrepreneurship, Start-ups, Business Intelligence, Program Management, Product Lifecycle..., Product Development, Product Launch, Business Alliances, User Experience, Market Research, Management, Wireless, Leadership, Executive Management, Competitive Analysis, Mobile Technology, E-commerce
Education
University of California, Berkeley
MBA
University of Cincinnati
M.S.
Federico Politi Federico Politi's Cadence Design Systems Experience July 2014 - Present
Job Engineering Group Director at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems July 2014 - Present
Cadence Design Systems May 2011 - July 2014
Altos Design Automation August 2007 - May 2011
Magma Design Automation November 2003 - June 2007
Circuit Semantics, Inc May 1999 - October 2003
Power Computing Corp. May 1995 - September 1997
Skills
EDA, ASIC, TCL, SoC, Physical Design, Formal Verification, Static Timing Analysis, Mixed Signal, Simulations, IC, Debugging, RTL design, Semiconductors, Verilog, Embedded Systems, Timing Closure, Integrated Circuit..., Algorithms, VLSI
Education
Università degli Studi di Trieste 1992 — 1998
MS
Cadence Design Systems July 2014 - Present
Cadence Design Systems May 2011 - July 2014
Altos Design Automation August 2007 - May 2011
Magma Design Automation November 2003 - June 2007
Circuit Semantics, Inc May 1999 - October 2003
Power Computing Corp. May 1995 - September 1997
Skills
EDA, ASIC, TCL, SoC, Physical Design, Formal Verification, Static Timing Analysis, Mixed Signal, Simulations, IC, Debugging, RTL design, Semiconductors, Verilog, Embedded Systems, Timing Closure, Integrated Circuit..., Algorithms, VLSI
Education
Università degli Studi di Trieste 1992 — 1998
MS
Lan Chuck Lan Chuck's Cadence Design Systems Experience October 2000 - December 2002
Job Senior Software Engineer (commerce lead) at Next Issue Media
Industry Computer Software
Experience
Next Issue Media September 2014 - Present
Gocyto January 2014 - Present
Model N October 2010 - September 2014
Model N November 2005 - September 2010
Atom Shockwave July 2003 - November 2005
Cadence Design Systems October 2000 - December 2002
Skills
JUnit, Agile Methodologies, Java, Software Engineering, CVS, Scrum, Java Enterprise Edition, Tomcat, JavaScript, Software Development, Object Oriented Design, OOP, Perl, Subversion, Eclipse, Git, Enterprise Software, Perforce, ANTLR, Oracle SQL, SableCC, Data Structures, gerrit, SQL, Memcached
Education
University of California, Berkeley 1992 — 1997
Bachelor of Science (BS), Electrical and Electronics Engineering
Next Issue Media September 2014 - Present
Gocyto January 2014 - Present
Model N October 2010 - September 2014
Model N November 2005 - September 2010
Atom Shockwave July 2003 - November 2005
Cadence Design Systems October 2000 - December 2002
Skills
JUnit, Agile Methodologies, Java, Software Engineering, CVS, Scrum, Java Enterprise Edition, Tomcat, JavaScript, Software Development, Object Oriented Design, OOP, Perl, Subversion, Eclipse, Git, Enterprise Software, Perforce, ANTLR, Oracle SQL, SableCC, Data Structures, gerrit, SQL, Memcached
Education
University of California, Berkeley 1992 — 1997
Bachelor of Science (BS), Electrical and Electronics Engineering
Adam Planas Adam Planas's Cadence Design Systems Experience June 2008 - August 2008
Job Creative Problem Solver | Marketing Strategist | Video Production & Graphic Design Specialist
Industry Media Production
Experience
Prism Skylabs June 2015 - Present
Camp Creative June 2014 - June 2015
Camp Creative June 2012 - May 2014
Camp Creative February 2011 - July 2012
Carbonated TV February 2010 - February 2011
CalTV May 2008 - May 2010
Camp Creative June 2009 - August 2009
Cadence Design Systems June 2008 - August 2008
CalTV February 2008 - May 2008
CalTV February 2007 - December 2007
Skills
Creative Direction, Art Direction, Creative Strategy, Media Production, Video Production, Motion Graphics, Graphic Design, Web Design, Marketing Strategy, Social Media Marketing, Music Video Production, Music Marketing, Concert Photography, Post Production, After Effects, Photoshop, Illustrator, HTML, CSS, Final Cut Pro, Multimedia, Video Editing, Editing, Marketing Communications, Cinematography, Music Videos, Adobe Creative Suite, Premiere, Video, Storytelling, Content Strategy, Animation, New Media, Graphics, Digital Media, InDesign, Advertising, Rock Music, Social Media, Compositing, Digital Marketing, Digital Photography, User Experience, CMS, Adobe Creative Cloud, Google Apps, Branding, Chrome OS, Google Drive, Technology Marketing
Education
University of California, Berkeley 2006 — 2010
Bachelor's Degree, Cognitive Science, Practice of Art
Prism Skylabs June 2015 - Present
Camp Creative June 2014 - June 2015
Camp Creative June 2012 - May 2014
Camp Creative February 2011 - July 2012
Carbonated TV February 2010 - February 2011
CalTV May 2008 - May 2010
Camp Creative June 2009 - August 2009
Cadence Design Systems June 2008 - August 2008
CalTV February 2008 - May 2008
CalTV February 2007 - December 2007
Skills
Creative Direction, Art Direction, Creative Strategy, Media Production, Video Production, Motion Graphics, Graphic Design, Web Design, Marketing Strategy, Social Media Marketing, Music Video Production, Music Marketing, Concert Photography, Post Production, After Effects, Photoshop, Illustrator, HTML, CSS, Final Cut Pro, Multimedia, Video Editing, Editing, Marketing Communications, Cinematography, Music Videos, Adobe Creative Suite, Premiere, Video, Storytelling, Content Strategy, Animation, New Media, Graphics, Digital Media, InDesign, Advertising, Rock Music, Social Media, Compositing, Digital Marketing, Digital Photography, User Experience, CMS, Adobe Creative Cloud, Google Apps, Branding, Chrome OS, Google Drive, Technology Marketing
Education
University of California, Berkeley 2006 — 2010
Bachelor's Degree, Cognitive Science, Practice of Art
Weiqi Zou Weiqi Zou's Cadence Design Systems Experience April 2008 - February 2009
Job Design Engineer at Sigma Designs
Industry Semiconductors
Experience
Sigma Designs November 2012 - Present
Sigma Designs Trident August 2010 - November 2012
Alcatel-Lucent Shanghai Bell April 2009 - July 2010
Cadence Design Systems April 2008 - February 2009
Skills
ASIC, SoC, Static Timing Analysis, RTL design, Logic Synthesis, Video Processing, IC, Lint, Conformal LEC, MCU
Education
Tongji University 2006 — 2009
Master of Engineering (M.Eng.), Electrical, Electronics and Communications Engineering
Tongji University 2001 — 2005
Bachelor's degree, Electrical, Electronics and Communications Engineering
Sigma Designs November 2012 - Present
Sigma Designs Trident August 2010 - November 2012
Alcatel-Lucent Shanghai Bell April 2009 - July 2010
Cadence Design Systems April 2008 - February 2009
Skills
ASIC, SoC, Static Timing Analysis, RTL design, Logic Synthesis, Video Processing, IC, Lint, Conformal LEC, MCU
Education
Tongji University 2006 — 2009
Master of Engineering (M.Eng.), Electrical, Electronics and Communications Engineering
Tongji University 2001 — 2005
Bachelor's degree, Electrical, Electronics and Communications Engineering
Daniel Houlihan Daniel Houlihan's Cadence Design Systems Experience 1999 - 2014
Job Software Consultant, EDA/CAD
Industry Computer Software
Experience
Cadence Design Systems 1999 - 2014
HADCO Corporation 1993 - 1999
ComputerVision 1987 - 1993
Skills
EDA, Algorithms, Software Engineering, Debugging, Software Development, Object Oriented Design, Shell Scripting, Physical Design, C, C++, Linux, Unix, Testing, OpenAccess, Software Design, Programming
Education
Tufts University
BS, Computer Science
Cadence Design Systems 1999 - 2014
HADCO Corporation 1993 - 1999
ComputerVision 1987 - 1993
Skills
EDA, Algorithms, Software Engineering, Debugging, Software Development, Object Oriented Design, Shell Scripting, Physical Design, C, C++, Linux, Unix, Testing, OpenAccess, Software Design, Programming
Education
Tufts University
BS, Computer Science
Sai Krishna Renduchintala Sai Krishna Renduchintala's Cadence Design Systems Experience May 2013 - July 2015
Job Application Engineer at ANSYS
Industry Semiconductors
Experience
ANSYS, Inc. August 2015 - Present
Cadence Design Systems May 2013 - July 2015
Skills
Verilog, Cadence Virtuoso, VHDL, Perl, ModelSim, EDA, VLSI, Low-power Design, ASIC, Computer Architecture, C, Matlab, Static Timing Analysis, Digital Design, Mixed-Signal IC Design, Analog Design, PLL, DRC, LVS, Spectre, HFSS, Ansoft Designer, C++, FPGA, Xilinx, Active-HDL, Assembly Language, NS2, TCL, Pspice, Awk, Transmission Lines, Basys, IC, Analog, Xilinx ISE, RTL Design
Education
State University of New York at Buffalo 2011 — 2013
Master of Science (M.S.), Electrical Engineering (Specialized in VLSI), 3.6
Jawaharlal Nehru Technological University, Kakinada 2007 — 2011
Bachelor of Technology, Electrical, Electronics and Communications Engineering, 3.5
ANSYS, Inc. August 2015 - Present
Cadence Design Systems May 2013 - July 2015
Skills
Verilog, Cadence Virtuoso, VHDL, Perl, ModelSim, EDA, VLSI, Low-power Design, ASIC, Computer Architecture, C, Matlab, Static Timing Analysis, Digital Design, Mixed-Signal IC Design, Analog Design, PLL, DRC, LVS, Spectre, HFSS, Ansoft Designer, C++, FPGA, Xilinx, Active-HDL, Assembly Language, NS2, TCL, Pspice, Awk, Transmission Lines, Basys, IC, Analog, Xilinx ISE, RTL Design
Education
State University of New York at Buffalo 2011 — 2013
Master of Science (M.S.), Electrical Engineering (Specialized in VLSI), 3.6
Jawaharlal Nehru Technological University, Kakinada 2007 — 2011
Bachelor of Technology, Electrical, Electronics and Communications Engineering, 3.5
Pero Subasic Pero Subasic's Cadence Design Systems Experience March 2002 - November 2005
Job Vice President, Cloud Computing and Big Data at DOCOMO Innovations
Industry Information Services
Experience
DOCOMO Innovations, Inc. March 2012 - Present
Advertising.com January 2007 - March 2012
Yahoo! December 2005 - September 2006
Cadence Design Systems March 2002 - November 2005
Claritech (Clairvoyance), Justsystem Group January 1998 - June 2001
Research Institute Pupin 1990 - 1997
Skills
Cloud Computing, Big Data, Machine Learning, Information Retrieval, Computational..., Artificial Intelligence, Data Mining, Distributed Systems, Computer Science, Computation, Algorithms, Technology Transfer, Erlang, C++, EDA, CAD, CAE, Hadoop, Natural Language..., Scalability, Java, Perl, Amazon Web Services..., NoSQL, System Architecture, Neural Networks, Software Design, C, Optimization, Search, Multithreading, High Performance..., Mobile Applications, Lucene, Linux, Prolog, Open Source, MapReduce, Text Mining, Start-ups, Programming
Education
Tokyo Institute of Technology 1995 — 1996
Visiting Professor, Interdisciplinary Graduate School of Science and Engineering
Yamagata University 1993 — 1996
Ph.D., Systems and Information Engineering
Tohoku University 1992 — 1993
Visiting Monbusho Scholar, Fuzzy Systems and Fuzzy Expert Systems
University of Belgrade, Faculty of Electrical Engineering 1990 — 1992
M.Sci., Software Systems
University of Belgrade, Faculty of Electrical Engineering 1984 — 1989
Dipl. Eng., Computer Science and Electrical Engineering
Prva Zemunska Gimnazija (ZIG) 1979 — 1983
Technician in Experimental Physics, Physics and Mathematics
DOCOMO Innovations, Inc. March 2012 - Present
Advertising.com January 2007 - March 2012
Yahoo! December 2005 - September 2006
Cadence Design Systems March 2002 - November 2005
Claritech (Clairvoyance), Justsystem Group January 1998 - June 2001
Research Institute Pupin 1990 - 1997
Skills
Cloud Computing, Big Data, Machine Learning, Information Retrieval, Computational..., Artificial Intelligence, Data Mining, Distributed Systems, Computer Science, Computation, Algorithms, Technology Transfer, Erlang, C++, EDA, CAD, CAE, Hadoop, Natural Language..., Scalability, Java, Perl, Amazon Web Services..., NoSQL, System Architecture, Neural Networks, Software Design, C, Optimization, Search, Multithreading, High Performance..., Mobile Applications, Lucene, Linux, Prolog, Open Source, MapReduce, Text Mining, Start-ups, Programming
Education
Tokyo Institute of Technology 1995 — 1996
Visiting Professor, Interdisciplinary Graduate School of Science and Engineering
Yamagata University 1993 — 1996
Ph.D., Systems and Information Engineering
Tohoku University 1992 — 1993
Visiting Monbusho Scholar, Fuzzy Systems and Fuzzy Expert Systems
University of Belgrade, Faculty of Electrical Engineering 1990 — 1992
M.Sci., Software Systems
University of Belgrade, Faculty of Electrical Engineering 1984 — 1989
Dipl. Eng., Computer Science and Electrical Engineering
Prva Zemunska Gimnazija (ZIG) 1979 — 1983
Technician in Experimental Physics, Physics and Mathematics
Reuber Duarte Reuber Duarte's Cadence Design Systems Experience August 2003 - Present
Job Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems August 2003 - Present
Verplex Systems Inc. August 2001 - August 2003
Skills
C++, Software Engineering, EDA, Formal Verification, Programming, Low-power Design, Algorithms, Functional Verification, Eclipse, Architecture, TCL, Debugging, Java, C, Software Development, UML, Python, Hibernate, Distributed Systems, Object Oriented Design, SQL, Java Enterprise Edition, Git, Design Patterns, Shell Scripting, Databases, Machine Learning, Linux
Education
Universidade Federal de Minas Gerais 2000 — 2002
MSc, Computer Science
Universidade Federal de Minas Gerais 1996 — 1999
BS, Computer Science
Cadence Design Systems August 2003 - Present
Verplex Systems Inc. August 2001 - August 2003
Skills
C++, Software Engineering, EDA, Formal Verification, Programming, Low-power Design, Algorithms, Functional Verification, Eclipse, Architecture, TCL, Debugging, Java, C, Software Development, UML, Python, Hibernate, Distributed Systems, Object Oriented Design, SQL, Java Enterprise Edition, Git, Design Patterns, Shell Scripting, Databases, Machine Learning, Linux
Education
Universidade Federal de Minas Gerais 2000 — 2002
MSc, Computer Science
Universidade Federal de Minas Gerais 1996 — 1999
BS, Computer Science
LONG ERIC MA LONG ERIC MA's Cadence Design Systems Experience July 2005 - September 2005
Job Application Manager at Hermes Microvision Inc
Industry Semiconductors
Experience
Hermes Microvision Inc May 2013 - Present
Hermes Microvision Inc November 2006 - Present
Hermes epitek February 2006 - September 2006
Cadence Design Systems July 2005 - September 2005
Skills
Semiconductors, Manufacturing, Semiconductor..., Flash Memory, CMOS, Electrical Engineering, Metrology, Signal Processing
Education
Tsinghua University 1999 — 2005
MS, Microelectronics
Hermes Microvision Inc May 2013 - Present
Hermes Microvision Inc November 2006 - Present
Hermes epitek February 2006 - September 2006
Cadence Design Systems July 2005 - September 2005
Skills
Semiconductors, Manufacturing, Semiconductor..., Flash Memory, CMOS, Electrical Engineering, Metrology, Signal Processing
Education
Tsinghua University 1999 — 2005
MS, Microelectronics
Aine Guiney's Cadence Design Systems Experience January 2001 - June 2003
Job Director of Sales, Caribbean and South Pacific Markets at RMK Worldwide Inc
Industry Marketing and Advertising
Experience
RMK Worldwide Inc September 2010 - Present
Digicel May 2008 - May 2010
Acme Vinyl Inc November 2003 - March 2007
Cadence Design Systems January 2001 - June 2003
Optus January 2000 - September 2000
American Express August 1999 - December 1999
American Express March 1999 - May 1999
Skills
Marketing Management, Promotion Management, Special Events..., Multi-Market Branding, Sponsorship Program..., Financial Analysis, Brand Design, Client and Public..., Budget Administration, New Business Development, Project Management, Risk Assessment, Strategic Planning, Product Launch, Product Launch Events, Merchandising, Marketing, Budgets, Advertising, Mobile Devices, Sales, Management, Strategic Partnerships, Marketing Strategy
Education
University College Cork 1995 — 1998
Bachelor of Arts (B.A.), Geography, Archeology, Philospohy, Honors
RMK Worldwide Inc September 2010 - Present
Digicel May 2008 - May 2010
Acme Vinyl Inc November 2003 - March 2007
Cadence Design Systems January 2001 - June 2003
Optus January 2000 - September 2000
American Express August 1999 - December 1999
American Express March 1999 - May 1999
Skills
Marketing Management, Promotion Management, Special Events..., Multi-Market Branding, Sponsorship Program..., Financial Analysis, Brand Design, Client and Public..., Budget Administration, New Business Development, Project Management, Risk Assessment, Strategic Planning, Product Launch, Product Launch Events, Merchandising, Marketing, Budgets, Advertising, Mobile Devices, Sales, Management, Strategic Partnerships, Marketing Strategy
Education
University College Cork 1995 — 1998
Bachelor of Arts (B.A.), Geography, Archeology, Philospohy, Honors
Ming Ming's Cadence Design Systems Experience July 2004 - November 2013
Job Software Engineer at Machine Zone, Inc.
Industry Computer Software
Experience
Machine Zone, Inc. September 2014 - Present
StreetLight Data, Inc. December 2013 - August 2014
Cadence Design Systems July 2004 - November 2013
Skills
PHP, Python, MySQL, Redis, SQL, JavaScript, HTML, Web Development, Database Design, C++, Machine Learning, OOP, Linux, C
Education
Tsinghua University
Bachelor of Engineering (B.E.)
Machine Zone, Inc. September 2014 - Present
StreetLight Data, Inc. December 2013 - August 2014
Cadence Design Systems July 2004 - November 2013
Skills
PHP, Python, MySQL, Redis, SQL, JavaScript, HTML, Web Development, Database Design, C++, Machine Learning, OOP, Linux, C
Education
Tsinghua University
Bachelor of Engineering (B.E.)
Nilesh Modi Nilesh Modi's Cadence Design Systems Experience July 2006 - September 2006
Job Senior R & D Software Engineer in Computational Lithography Group at Intel Corporation
Industry Semiconductors
Experience
Intel Corporation March 2011 - Present
VLSI Design and Test Group, University of California-Santa Barbara 2004 - 2010
IBM T J Watson Research Center June 2008 - December 2008
IBM Microelectronics Division June 2007 - September 2007
Cadence Design Systems July 2006 - September 2006
IBM Microelectronics June 2005 - September 2005
Algorithms and Genetics Group, UPC January 2003 - June 2004
GAVINA Research Group, UPC, Barcelona September 2002 - June 2004
Computer Architecture Department, UPC, Barcelona September 2002 - June 2003
Tata Institute of Fundamental Research (TIFR) May 2002 - July 2002
Skills
VLSI, EDA, Algorithms, Data Structures, Computer Engineering, Routing, RTL design, Physical Design, C++, Computational Geometry, Logic Synthesis, Optimization, Optimizations, Distributed Systems, ModelSim, IC, Integrated Circuit..., Verilog, Python, Embedded Systems, Computer Science, Static Timing Analysis, High Performance..., Parallel Programming, Machine Learning, Cadence, SPICE, Algorithm Design, SystemVerilog, CMOS, Simulations, Hardware Architecture, Software Engineering, Compilers, Cadence Virtuoso, Microprocessors, Debugging, Computer Architecture, Parallel Computing, Perl, Java, Matlab, VHDL, FPGA, ASIC, Software Design, TCL, C, Circuit Design
Education
University of California, Santa Barbara 2004 — 2010
Ph.D, Electrical and Computer Engineering
University of California, Santa Barbara 2004 — 2010
M.S., Computer Engineering
Universitat Politècnica de Catalunya 2002 — 2004
M.S, Computer Science
Nirma Institute of Technology, Gujarat University 1998 — 2002
B.Tech., Information Technology (Gold Medalist)
Intel Corporation March 2011 - Present
VLSI Design and Test Group, University of California-Santa Barbara 2004 - 2010
IBM T J Watson Research Center June 2008 - December 2008
IBM Microelectronics Division June 2007 - September 2007
Cadence Design Systems July 2006 - September 2006
IBM Microelectronics June 2005 - September 2005
Algorithms and Genetics Group, UPC January 2003 - June 2004
GAVINA Research Group, UPC, Barcelona September 2002 - June 2004
Computer Architecture Department, UPC, Barcelona September 2002 - June 2003
Tata Institute of Fundamental Research (TIFR) May 2002 - July 2002
Skills
VLSI, EDA, Algorithms, Data Structures, Computer Engineering, Routing, RTL design, Physical Design, C++, Computational Geometry, Logic Synthesis, Optimization, Optimizations, Distributed Systems, ModelSim, IC, Integrated Circuit..., Verilog, Python, Embedded Systems, Computer Science, Static Timing Analysis, High Performance..., Parallel Programming, Machine Learning, Cadence, SPICE, Algorithm Design, SystemVerilog, CMOS, Simulations, Hardware Architecture, Software Engineering, Compilers, Cadence Virtuoso, Microprocessors, Debugging, Computer Architecture, Parallel Computing, Perl, Java, Matlab, VHDL, FPGA, ASIC, Software Design, TCL, C, Circuit Design
Education
University of California, Santa Barbara 2004 — 2010
Ph.D, Electrical and Computer Engineering
University of California, Santa Barbara 2004 — 2010
M.S., Computer Engineering
Universitat Politècnica de Catalunya 2002 — 2004
M.S, Computer Science
Nirma Institute of Technology, Gujarat University 1998 — 2002
B.Tech., Information Technology (Gold Medalist)
Peter Hackett Peter Hackett's Cadence Design Systems Experience 1982 - 2006
Job Staff Software Engineer at IC Manage
Industry Computer Software
Experience
IC Manage June 2007 - Present
Cadence Design Systems 1982 - 2006
Valid Logic Systems 1982 - 1991
Skills
EDA, Perl, C++, C, Unix, Python, Linux, TCL, CVS, Multithreading, Object Oriented Design, Software Engineering, Perforce, Shell Scripting, Software Development, Unix Shell Scripting, IBM Rational Purify, Regular Expressions, ClearCase, Design Management, Qt, STL, Cadence Skill, JavaScript, Source Code Control, Coverity, Purify, RCS, SoC, Embedded Systems, Debugging, ASIC, OOP, SCCS
Education
University of California, Berkeley 1985 — 1989
BS EECS, Physics, Electrical Engineering, Computer Science
IC Manage June 2007 - Present
Cadence Design Systems 1982 - 2006
Valid Logic Systems 1982 - 1991
Skills
EDA, Perl, C++, C, Unix, Python, Linux, TCL, CVS, Multithreading, Object Oriented Design, Software Engineering, Perforce, Shell Scripting, Software Development, Unix Shell Scripting, IBM Rational Purify, Regular Expressions, ClearCase, Design Management, Qt, STL, Cadence Skill, JavaScript, Source Code Control, Coverity, Purify, RCS, SoC, Embedded Systems, Debugging, ASIC, OOP, SCCS
Education
University of California, Berkeley 1985 — 1989
BS EECS, Physics, Electrical Engineering, Computer Science
Wai Hung Ho's Cadence Design Systems Experience 1999 - 2009
Job Software Engineering Professional, Engineering and Project Management
Industry Computer Software
Experience
Cadence Design Systems 1999 - 2009
Cadence Design Systems 1995 - 1999
Cadence Design Systems 1992 - 1995
Skills
Software Project..., Product Management, Software Development, EDA, Electronics, Software Engineering, IC, Leadership, Management, Product Development, Cloud Computing, SaaS, Integration, Program Management, PMP, Enterprise Software, Cross-functional Team..., Agile Methodologies, System Architecture, CRM, Start-ups, Agile Project Management
Education
University of California, Berkeley
MS, EECS
Cadence Design Systems 1999 - 2009
Cadence Design Systems 1995 - 1999
Cadence Design Systems 1992 - 1995
Skills
Software Project..., Product Management, Software Development, EDA, Electronics, Software Engineering, IC, Leadership, Management, Product Development, Cloud Computing, SaaS, Integration, Program Management, PMP, Enterprise Software, Cross-functional Team..., Agile Methodologies, System Architecture, CRM, Start-ups, Agile Project Management
Education
University of California, Berkeley
MS, EECS
David Jacobowitz's Cadence Design Systems Experience December 1997 - January 2000
Job Bringing cloud intelligence to residential outdoor watering.
Industry Renewables & Environment
Experience
Blossom November 2014 - Present
BrightSource Energy, Inc. March 2012 - November 2014
Google December 2009 - February 2012
Pacific Gas & Electric November 2007 - November 2009
California Center for Innovative Transportation December 2006 - July 2007
Pacific Gas & Electric January 2007 - May 2007
UC Berkeley 2007 - 2007
Tensilica, Inc. January 2000 - August 2005
Cadence Design Systems December 1997 - January 2000
Intel Corporation July 1995 - December 1997
Skills
Renewable Energy, Energy Policy, Energy Efficiency, Solar Power, Computing, Energy, Solar Energy, Program Management, Business Strategy, Semiconductors, Product Management, Cross-functional Team..., Smart Grid, Power Markets, Demand Response, Embedded Systems, Engineering, Cleantech, Entrepreneurship, EDA, Alternative Energy, Product Marketing
Education
University of California, Berkeley 2005 — 2007
MPP
University of Virginia 1991 — 1995
BSEE
Blossom November 2014 - Present
BrightSource Energy, Inc. March 2012 - November 2014
Google December 2009 - February 2012
Pacific Gas & Electric November 2007 - November 2009
California Center for Innovative Transportation December 2006 - July 2007
Pacific Gas & Electric January 2007 - May 2007
UC Berkeley 2007 - 2007
Tensilica, Inc. January 2000 - August 2005
Cadence Design Systems December 1997 - January 2000
Intel Corporation July 1995 - December 1997
Skills
Renewable Energy, Energy Policy, Energy Efficiency, Solar Power, Computing, Energy, Solar Energy, Program Management, Business Strategy, Semiconductors, Product Management, Cross-functional Team..., Smart Grid, Power Markets, Demand Response, Embedded Systems, Engineering, Cleantech, Entrepreneurship, EDA, Alternative Energy, Product Marketing
Education
University of California, Berkeley 2005 — 2007
MPP
University of Virginia 1991 — 1995
BSEE
Aswin Ramakrishnan's Cadence Design Systems Experience May 2011 - Present
Job
Industry Semiconductors
Experience
Cadence Design Systems May 2011 - Present
Altos Design Automation September 2008 - May 2011
Percipia December 2007 - August 2008
Cadence Design Systems January 2004 - November 2007
Univ of Arizona. Dept of Astronomy/ Dept of Atmo Sciences July 2001 - December 2003
Skills
SoC, EDA, Mixed Signal, C++, Algorithms, ASIC, Semiconductors, TCL, Perl, Verilog, VLSI, Debugging, Analog, IC
Education
University of Arizona 2001 — 2003
MS, Computer Engineering, 3.8/4.0
University of Madras 1997 — 2001
BE, EE, Distinction
SBOA 1981 — 1997
Cadence Design Systems May 2011 - Present
Altos Design Automation September 2008 - May 2011
Percipia December 2007 - August 2008
Cadence Design Systems January 2004 - November 2007
Univ of Arizona. Dept of Astronomy/ Dept of Atmo Sciences July 2001 - December 2003
Skills
SoC, EDA, Mixed Signal, C++, Algorithms, ASIC, Semiconductors, TCL, Perl, Verilog, VLSI, Debugging, Analog, IC
Education
University of Arizona 2001 — 2003
MS, Computer Engineering, 3.8/4.0
University of Madras 1997 — 2001
BE, EE, Distinction
SBOA 1981 — 1997
David Sallard's Cadence Design Systems Experience January 2001 - June 2004
Job
Industry Semiconductors
Experience
Cadence July 2004 - Present
Cadence Design Systems January 2001 - June 2004
Cadence Design Systems September 1996 - January 2002
Zycad Corporation November 1992 - September 1996
General Electric (AstroSpace Division) January 1986 - October 1992
Skills
ASIC, Semiconductors, IC, Electronics, Functional Verification, Systems Engineering, Management, Emulation, EDA, Perl, Verilog, Debugging, SoC, FPGA, Embedded Systems, RTL Design, Hardware, TCL, Simulations, VHDL
Education
University of Pennsylvania 1987 — 1989
MSE, Systems Engineering, Computer Systems
University of Bridgeport 1981 — 1985
BS, Computer Engineering (Major) / Electrical Engineering (Minor)
Cadence July 2004 - Present
Cadence Design Systems January 2001 - June 2004
Cadence Design Systems September 1996 - January 2002
Zycad Corporation November 1992 - September 1996
General Electric (AstroSpace Division) January 1986 - October 1992
Skills
ASIC, Semiconductors, IC, Electronics, Functional Verification, Systems Engineering, Management, Emulation, EDA, Perl, Verilog, Debugging, SoC, FPGA, Embedded Systems, RTL Design, Hardware, TCL, Simulations, VHDL
Education
University of Pennsylvania 1987 — 1989
MSE, Systems Engineering, Computer Systems
University of Bridgeport 1981 — 1985
BS, Computer Engineering (Major) / Electrical Engineering (Minor)
Andrew Xiaohui Zhou's Cadence Design Systems Experience November 2000 - November 2006
Job Principal Software Engineer Manager at Microsoft
Industry Computer Software
Experience
Microsoft September 2014 - Present
Microsoft December 2013 - August 2014
Microsoft May 2012 - November 2013
Microsoft February 2011 - May 2012
Cisco March 2010 - January 2011
Brion Technologies, an ASML Company November 2006 - March 2010
Cadence Design Systems November 2000 - November 2006
General Information Technology Inc. April 2000 - November 2000
China Construction Bank July 1996 - April 2000
Education
Tsinghua University 1991 — 1996
Bachelor, Computer Science
Microsoft September 2014 - Present
Microsoft December 2013 - August 2014
Microsoft May 2012 - November 2013
Microsoft February 2011 - May 2012
Cisco March 2010 - January 2011
Brion Technologies, an ASML Company November 2006 - March 2010
Cadence Design Systems November 2000 - November 2006
General Information Technology Inc. April 2000 - November 2000
China Construction Bank July 1996 - April 2000
Education
Tsinghua University 1991 — 1996
Bachelor, Computer Science
XiaoQin Liu's Cadence Design Systems Experience August 2003 - November 2012
Job RedHawk Product Head at Ansys/Apache
Industry Computer Software
Experience
Ansys December 2012 - Present
Cadence Design Systems August 2003 - November 2012
Institute of Electronics, Chinese Academy of Sciences 1998 - 2001
Skills
EDA, Simulations, C, STL, C++, Customer Engagement, Mixed Signal, IC, Analog, Debugging, ASIC, Physical Design, Low-power Design, Algorithms
Education
Chinese Academy of Sciences
M.S., EE
Tsinghua University
B.S., MSE
Ansys December 2012 - Present
Cadence Design Systems August 2003 - November 2012
Institute of Electronics, Chinese Academy of Sciences 1998 - 2001
Skills
EDA, Simulations, C, STL, C++, Customer Engagement, Mixed Signal, IC, Analog, Debugging, ASIC, Physical Design, Low-power Design, Algorithms
Education
Chinese Academy of Sciences
M.S., EE
Tsinghua University
B.S., MSE
Virgil Nicula's Cadence Design Systems Experience May 2005 - July 2014
Job Expert C++ Software Engineer
Industry Computer Software
Experience
Apple January 2015 - Present
NetApp August 2014 - December 2014
Cadence Design Systems May 2005 - July 2014
BindKey Technologies, Inc., acquired by DuPont Photomasks 2003 - 2005
SYNTAX SRL ROMANIA May 1999 - August 2003
PREFECTURA NEAMT March 1997 - February 1999
Skills
C++, Qt, UML, C/C++ STL, Eclipse, Yacc, Gcc/g++, Generic Programming, EDA, Circuit Simulation, State Machines, Design Patterns, OOAD, Boost, Multithreading, Finite State Machines, Simulations, CVS, GCC, Linux, TCL, C++11, ClearCase, Programming
Education
Universitatea Tehnică „Gh. Asachi” din Iași 1989 — 1994
Engineering Degree, Computer Science
EOMMEX, Athena 1997 — 1997
Management Diploma, Management Of Small and Medium Sized Enterprises
Apple January 2015 - Present
NetApp August 2014 - December 2014
Cadence Design Systems May 2005 - July 2014
BindKey Technologies, Inc., acquired by DuPont Photomasks 2003 - 2005
SYNTAX SRL ROMANIA May 1999 - August 2003
PREFECTURA NEAMT March 1997 - February 1999
Skills
C++, Qt, UML, C/C++ STL, Eclipse, Yacc, Gcc/g++, Generic Programming, EDA, Circuit Simulation, State Machines, Design Patterns, OOAD, Boost, Multithreading, Finite State Machines, Simulations, CVS, GCC, Linux, TCL, C++11, ClearCase, Programming
Education
Universitatea Tehnică „Gh. Asachi” din Iași 1989 — 1994
Engineering Degree, Computer Science
EOMMEX, Athena 1997 — 1997
Management Diploma, Management Of Small and Medium Sized Enterprises
John Ennis's Cadence Design Systems Experience May 2011 - Present
Job Sales Director Worldwide Field Operations at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems May 2011 - Present
Altos Design Automation May 2010 - February 2012
Pyxis Technology September 2006 - May 2010
Circuit Semantics, Inc 2002 - 2003
Avant 1996 - 2002
Cadence Design Systems 1986 - 1996
Rockwell Automation 1980 - 1984
Skills
EDA, Semiconductors, SaaS, Strategic Partnerships, Start-ups, ASIC, Sales Operations, Negotiation, IC, Business Development, Wireless, Sales, Management, Enterprise Software, Product Marketing, Product Management, Go-to-market Strategy, Cloud Computing, SoC
Education
Thomas Edison State College 1976 — 1980
Cadence Design Systems May 2011 - Present
Altos Design Automation May 2010 - February 2012
Pyxis Technology September 2006 - May 2010
Circuit Semantics, Inc 2002 - 2003
Avant 1996 - 2002
Cadence Design Systems 1986 - 1996
Rockwell Automation 1980 - 1984
Skills
EDA, Semiconductors, SaaS, Strategic Partnerships, Start-ups, ASIC, Sales Operations, Negotiation, IC, Business Development, Wireless, Sales, Management, Enterprise Software, Product Marketing, Product Management, Go-to-market Strategy, Cloud Computing, SoC
Education
Thomas Edison State College 1976 — 1980
Patrick Rasetarinera's Cadence Design Systems Experience 2005 - 2008
Job Senior Software Engineer at LinkedIn
Industry Computer Software
Experience
LinkedIn July 2015 - Present
Cadence Design Systems Inc. April 2008 - June 2015
Cadence Design Systems 2005 - 2008
Cadence Design Systems 2002 - 2005
Simplex Solutions Inc 2001 - 2002
Silvaco October 2000 - July 2001
Florida State University April 1997 - September 2000
Skills
Linux, Object Oriented Design, Enterprise Software, Algorithms, Software Engineering, C++, Software Development, EDA, Unix, Distributed Systems, Product Lifecycle..., Testing, Python, C/C++ STL, Multithreading, Distributed Computing, Scalability
Education
Université Bordeaux I 1992 — 1995
PhD, Applied Mathematics
LinkedIn July 2015 - Present
Cadence Design Systems Inc. April 2008 - June 2015
Cadence Design Systems 2005 - 2008
Cadence Design Systems 2002 - 2005
Simplex Solutions Inc 2001 - 2002
Silvaco October 2000 - July 2001
Florida State University April 1997 - September 2000
Skills
Linux, Object Oriented Design, Enterprise Software, Algorithms, Software Engineering, C++, Software Development, EDA, Unix, Distributed Systems, Product Lifecycle..., Testing, Python, C/C++ STL, Multithreading, Distributed Computing, Scalability
Education
Université Bordeaux I 1992 — 1995
PhD, Applied Mathematics
Frederic Doucet's Cadence Design Systems Experience July 2012 - October 2014
Job hw design @ qualcomm
Industry Semiconductors
Experience
Qualcomm October 2014 - Present
Cadence Design Systems July 2012 - October 2014
Cadence Design Systems July 2011 - July 2012
Cadence Design Systems April 2008 - July 2011
IBM March 2006 - June 2006
Conexant June 2003 - September 2003
Intel July 2000 - September 2000
Lockheed Martin January 1997 - September 1997
Skills
Software Engineering, Architectures, Algorithms, C++, Debugging, C, Embedded Systems, Distributed Systems, Software Development, Linux, Embedded Software, Shell Scripting, Unix, Object Oriented Design, Java, Simulations, Software Design, Computer Architecture, EDA, Tcl, SystemC, High-level Synthesis, Technology Pre-Sales, Pre-Sales Consulting, Perl
Education
University of California, San Diego 2003 — 2018
PhD (to be finished eventually), computer science
University of California, Irvine 2000 — 2002
MS, computer science - EDA
Université de Montréal - Ecole polytechnique de Montréal 1994 — 1999
B. Eng, computer engineering
Qualcomm October 2014 - Present
Cadence Design Systems July 2012 - October 2014
Cadence Design Systems July 2011 - July 2012
Cadence Design Systems April 2008 - July 2011
IBM March 2006 - June 2006
Conexant June 2003 - September 2003
Intel July 2000 - September 2000
Lockheed Martin January 1997 - September 1997
Skills
Software Engineering, Architectures, Algorithms, C++, Debugging, C, Embedded Systems, Distributed Systems, Software Development, Linux, Embedded Software, Shell Scripting, Unix, Object Oriented Design, Java, Simulations, Software Design, Computer Architecture, EDA, Tcl, SystemC, High-level Synthesis, Technology Pre-Sales, Pre-Sales Consulting, Perl
Education
University of California, San Diego 2003 — 2018
PhD (to be finished eventually), computer science
University of California, Irvine 2000 — 2002
MS, computer science - EDA
Université de Montréal - Ecole polytechnique de Montréal 1994 — 1999
B. Eng, computer engineering
Pascal Poire's Cadence Design Systems Experience March 2013 - Present
Job Senior Design Engineering Manager at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems March 2013 - Present
PMC Sierra August 1998 - March 2013
Education
Université de Montréal - Ecole polytechnique de Montréal 1997 — 1998
Master, microelectronic
Université de Sherbrooke 1992 — 1996
bachelor, Electrical Engineering
Francois-Xavier Garneau 1990 — 1992
CEGEP, Sciences
Cadence Design Systems March 2013 - Present
PMC Sierra August 1998 - March 2013
Education
Université de Montréal - Ecole polytechnique de Montréal 1997 — 1998
Master, microelectronic
Université de Sherbrooke 1992 — 1996
bachelor, Electrical Engineering
Francois-Xavier Garneau 1990 — 1992
CEGEP, Sciences
shuilong chen's Cadence Design Systems Experience May 2011 - Present
Job R&D at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems May 2011 - Present
Altos Design Automation May 2007 - May 2011
Skills
EDA, SoC, ASIC, Verilog, Algorithms, Perl, TCL, C++, C, Debugging, Simulations, IC, Semiconductors, Software Engineering, Linux, Software Development
Education
Tsinghua University
Doctor of Philosophy (PhD)
Cadence Design Systems May 2011 - Present
Altos Design Automation May 2007 - May 2011
Skills
EDA, SoC, ASIC, Verilog, Algorithms, Perl, TCL, C++, C, Debugging, Simulations, IC, Semiconductors, Software Engineering, Linux, Software Development
Education
Tsinghua University
Doctor of Philosophy (PhD)
Kalps Iyer's Cadence Design Systems Experience June 2007 - January 2009
Job Senior Engineer, Lattice Semiconductor
Industry Computer Software
Experience
Lattice Semiconductor February 2014 - Present
HCL Technologies November 2012 - January 2014
Xerox Global Development Center, HCL Technologies April 2011 - November 2012
Cadence Design Systems June 2007 - January 2009
Athena Design Systems May 2006 - June 2007
Synopsys Inc August 2000 - March 2006
Cadence Design Systems May 1996 - August 2000
Actel Corporation 1993 - 1996
Skills
Verilog, ASIC, Debugging, C++, EDA, Algorithms, FPGA, VHDL, Simulations, Logic Synthesis, C, SoC, TCL, Perl, Software Engineering, RTL Design, VLSI, IC, Linux, Semiconductors, Software Development, Testing, Embedded Systems, Extraction, Parasitic Extraction, Scrum, Agile Project Management, Agile & Waterfall..., Program Management, Unix, Integration, Static Timing Analysis
Education
Santa Clara University
M.S, Computer Engineering
Thiagarajar College of Engineering
B.S, Electronics and Communication Engineering
Lattice Semiconductor February 2014 - Present
HCL Technologies November 2012 - January 2014
Xerox Global Development Center, HCL Technologies April 2011 - November 2012
Cadence Design Systems June 2007 - January 2009
Athena Design Systems May 2006 - June 2007
Synopsys Inc August 2000 - March 2006
Cadence Design Systems May 1996 - August 2000
Actel Corporation 1993 - 1996
Skills
Verilog, ASIC, Debugging, C++, EDA, Algorithms, FPGA, VHDL, Simulations, Logic Synthesis, C, SoC, TCL, Perl, Software Engineering, RTL Design, VLSI, IC, Linux, Semiconductors, Software Development, Testing, Embedded Systems, Extraction, Parasitic Extraction, Scrum, Agile Project Management, Agile & Waterfall..., Program Management, Unix, Integration, Static Timing Analysis
Education
Santa Clara University
M.S, Computer Engineering
Thiagarajar College of Engineering
B.S, Electronics and Communication Engineering
Chris Ashburn's Cadence Design Systems Experience January 1995 - October 2003
Job Hardware Physical Design Staff Eng. at Qualcomm
Industry Semiconductors
Experience
Qualcomm January 2003 - Present
Cadence Design Systems January 1995 - October 2003
Music Semiconductors January 1994 - October 1995
Gec Plessey Semiconductors 1989 - 1993
Plessey 1989 - 1993
Education
University of Bristol 1986 — 1989
BSc Physics, Physics, Mathmatics, Comp. Sci.
Qualcomm January 2003 - Present
Cadence Design Systems January 1995 - October 2003
Music Semiconductors January 1994 - October 1995
Gec Plessey Semiconductors 1989 - 1993
Plessey 1989 - 1993
Education
University of Bristol 1986 — 1989
BSc Physics, Physics, Mathmatics, Comp. Sci.
David Clorfeine's Cadence Design Systems Experience February 2013 - Present
Job Staff Application Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems February 2013 - Present
Texas Instruments April 2012 - Present
Texas Instruments 2010 - 2012
Texas Instruments 1999 - 2010
Texas Instruments 1995 - 1999
Texas Instruments 1987 - 1995
Education
Tulane University
BS, Electrical Engineering
Cadence Design Systems February 2013 - Present
Texas Instruments April 2012 - Present
Texas Instruments 2010 - 2012
Texas Instruments 1999 - 2010
Texas Instruments 1995 - 1999
Texas Instruments 1987 - 1995
Education
Tulane University
BS, Electrical Engineering
Stephen Reinschmidt's Cadence Design Systems Experience June 2008 - May 2014
Job CAD Engineer at Apple
Industry Consumer Electronics
Experience
Apple May 2014 - Present
Cadence Design Systems June 2008 - May 2014
Cadence Design Systems January 2006 - June 2008
Cadence Design Systems November 1999 - January 2006
Cadence Design Systems October 1987 - November 1999
Calma February 1980 - October 1987
National Semiconductor May 1977 - January 1980
Education
University of Arizona 1973 — 1976
Apple May 2014 - Present
Cadence Design Systems June 2008 - May 2014
Cadence Design Systems January 2006 - June 2008
Cadence Design Systems November 1999 - January 2006
Cadence Design Systems October 1987 - November 1999
Calma February 1980 - October 1987
National Semiconductor May 1977 - January 1980
Education
University of Arizona 1973 — 1976
Changsheng Ying's Cadence Design Systems Experience November 2007 - March 2014
Job Engineering Director at ASML/Brion
Industry Computer Software
Experience
ASML/Brion April 2014 - Present
Cadence Design Systems November 2007 - March 2014
Anchor Semiconductor Inc. January 2001 - November 2007
Skills
IC layout optimization,..., C/C++, Linux/Unix,..., Product Management, Semiconductor Industry, R&D, Distributed Systems, Engineering Management, Product Development, Shell Scripting, Multithreading, Start-ups, Programming, Scalability, EDA, Algorithms, Perl, Semiconductors, ASIC
Education
Tsinghua University
Doctor of Philosophy (PhD), Computer Engineering
ASML/Brion April 2014 - Present
Cadence Design Systems November 2007 - March 2014
Anchor Semiconductor Inc. January 2001 - November 2007
Skills
IC layout optimization,..., C/C++, Linux/Unix,..., Product Management, Semiconductor Industry, R&D, Distributed Systems, Engineering Management, Product Development, Shell Scripting, Multithreading, Start-ups, Programming, Scalability, EDA, Algorithms, Perl, Semiconductors, ASIC
Education
Tsinghua University
Doctor of Philosophy (PhD), Computer Engineering
Jingli Hu's Cadence Design Systems Experience November 1997 - November 1999
Job Sr. CAE at Synopsys
Industry Computer Software
Experience
Synopsys May 2008 - Present
Synplicity November 1999 - May 2008
Cadence Design Systems November 1997 - November 1999
Education
Tsinghua University 1983 — 1988
Synopsys May 2008 - Present
Synplicity November 1999 - May 2008
Cadence Design Systems November 1997 - November 1999
Education
Tsinghua University 1983 — 1988
Zhichao Deng's Cadence Design Systems Experience September 2014 - Present
Job Sr. Principal Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems September 2014 - Present
IEEE 2011 - Present
Synopsys April 2006 - August 2014
Analog Devices July 2004 - December 2004
Skills
EDA, Simulations, ASIC, VHDL-AMS, Circuit Simulators, Algorithms, Modelica, C++, Multithreading, Verilog, SoC, C, Parallel Programming, Systems Modeling, Signal Integrity, Electromagnetic..., Fortran, Embedded Systems, Semiconductors, Python, Perl, Digital Signal..., VLSI
Education
University of Illinois at Urbana-Champaign 2001 — 2006
Ph.D, ECE
Tsinghua University 1995 — 2000
B.E., Electronic Engineering
Cadence Design Systems September 2014 - Present
IEEE 2011 - Present
Synopsys April 2006 - August 2014
Analog Devices July 2004 - December 2004
Skills
EDA, Simulations, ASIC, VHDL-AMS, Circuit Simulators, Algorithms, Modelica, C++, Multithreading, Verilog, SoC, C, Parallel Programming, Systems Modeling, Signal Integrity, Electromagnetic..., Fortran, Embedded Systems, Semiconductors, Python, Perl, Digital Signal..., VLSI
Education
University of Illinois at Urbana-Champaign 2001 — 2006
Ph.D, ECE
Tsinghua University 1995 — 2000
B.E., Electronic Engineering
John O'Donovan's Cadence Design Systems Experience 1998 - Present
Job Senior Architect at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems 1998 - Present
Silvaco 1994 - 1998
Education
University College Cork 1991 — 1993
MEngSc, Electronic Engineering
University College Cork 1987 — 1991
BE, Electronic Engineering
Cadence Design Systems 1998 - Present
Silvaco 1994 - 1998
Education
University College Cork 1991 — 1993
MEngSc, Electronic Engineering
University College Cork 1987 — 1991
BE, Electronic Engineering
Ronald Gyurcsik's Cadence Design Systems Experience 1997 - 2003
Job Director, Foundry Business and Strategy at Raytheon
Industry Semiconductors
Experience
Raytheon June 2014 - Present
Raytheon June 2009 - June 2014
Camarillo Microelectronics March 2008 - December 2009
Teradyne October 2004 - February 2008
Cadence 1997 - 2003
Cadence Design Systems 1997 - 2003
Semiconductor Research Corporation 1996 - 1997
North Carolina State University 1986 - 1995
Bell Laboratories 1980 - 1983
Skills
Engineering Management, Intellectual Property, Semiconductors, Product Development, Program Management, IC, EDA, Embedded Systems, Analog, Integrated Circuit..., Strategy, Manufacturing, Engineering, Test Equipment, Microelectronics, Debugging, Electronics, R&D, Analog Circuit Design, VLSI, RF, Simulations, Software Development, Mixed Signal, FPGA, Leadership, Cross-functional Team..., Software Engineering, ASIC, Patents, Systems Engineering, Management, Digital Signal..., DoD, Cadence, Hardware Architecture, Defense, SoC, System Design, Circuit Design, Aerospace, Electrical Engineering, System Architecture, Embedded Software, Earned Value Management, Testing, PCB design, Six Sigma, Security Clearance
Education
University of California, Berkeley 1980 — 1986
PhD, Electrical Engineering
University of Michigan 1976 — 1980
Bachelor of Science (B.S.), Electrical and Electronics Engineering
Cabrini 1972 — 1976
Raytheon June 2014 - Present
Raytheon June 2009 - June 2014
Camarillo Microelectronics March 2008 - December 2009
Teradyne October 2004 - February 2008
Cadence 1997 - 2003
Cadence Design Systems 1997 - 2003
Semiconductor Research Corporation 1996 - 1997
North Carolina State University 1986 - 1995
Bell Laboratories 1980 - 1983
Skills
Engineering Management, Intellectual Property, Semiconductors, Product Development, Program Management, IC, EDA, Embedded Systems, Analog, Integrated Circuit..., Strategy, Manufacturing, Engineering, Test Equipment, Microelectronics, Debugging, Electronics, R&D, Analog Circuit Design, VLSI, RF, Simulations, Software Development, Mixed Signal, FPGA, Leadership, Cross-functional Team..., Software Engineering, ASIC, Patents, Systems Engineering, Management, Digital Signal..., DoD, Cadence, Hardware Architecture, Defense, SoC, System Design, Circuit Design, Aerospace, Electrical Engineering, System Architecture, Embedded Software, Earned Value Management, Testing, PCB design, Six Sigma, Security Clearance
Education
University of California, Berkeley 1980 — 1986
PhD, Electrical Engineering
University of Michigan 1976 — 1980
Bachelor of Science (B.S.), Electrical and Electronics Engineering
Cabrini 1972 — 1976
Ted Vucurevich's Cadence Design Systems Experience August 1992 - March 2009
Job CEO at Enconcert Incorporated
Industry Entertainment
Experience
Enconcert Incorporated 2010 - Present
Slightly Sharp Enterprises March 2009 - Present
Cadence Design Systems August 1992 - March 2009
Analog Devices July 1978 - August 1992
Skills
Executive Management, Semiconductors, Software Development, Capital Budgeting, Technological Innovation, LAMP, Cloud Computing, SaaS, Agile Methodologies, Digital Media, Social Media, Machine Learning, Electronic System Design, Program Management, CAD, Start-ups, Web Services, Web Analytics, Cross-functional Team..., Team Building, Career Development, Dynamic Speaker, C, C++, Objective-C, iOS development, Android Development, Java, Python, Google App Engine, EC2, Wowza, Presenter, EDA, Product Management, Amazon EC2, ASIC, Algorithms, Strategy, Strategic Partnerships, Go-to-market Strategy, SoC, IT Strategy, Software Engineering, Scalability, Mobile Applications, Embedded Systems
Education
University of Arizona 1974 — 1978
BSEE, Electrical Engineering and Computer Science
Enconcert Incorporated 2010 - Present
Slightly Sharp Enterprises March 2009 - Present
Cadence Design Systems August 1992 - March 2009
Analog Devices July 1978 - August 1992
Skills
Executive Management, Semiconductors, Software Development, Capital Budgeting, Technological Innovation, LAMP, Cloud Computing, SaaS, Agile Methodologies, Digital Media, Social Media, Machine Learning, Electronic System Design, Program Management, CAD, Start-ups, Web Services, Web Analytics, Cross-functional Team..., Team Building, Career Development, Dynamic Speaker, C, C++, Objective-C, iOS development, Android Development, Java, Python, Google App Engine, EC2, Wowza, Presenter, EDA, Product Management, Amazon EC2, ASIC, Algorithms, Strategy, Strategic Partnerships, Go-to-market Strategy, SoC, IT Strategy, Software Engineering, Scalability, Mobile Applications, Embedded Systems
Education
University of Arizona 1974 — 1978
BSEE, Electrical Engineering and Computer Science
Xiaosong Wang's Cadence Design Systems Experience AESolarflare2009 - 2011
Job Application Engineer at Cadence Design Systems
Industry Electrical/Electronic Manufacturing
Experience
Cadence Design Systems AESolarflare2009 - 2011
Education
University of Utah 1999 — 2001
Tianjin University 1993 — 1996
master, mechnical
Tianjin University 1989 — 1996
bachelor, mechnical
Tianjin University 1989 — 1993
bachelor, mechnical
Cadence Design Systems AESolarflare2009 - 2011
Education
University of Utah 1999 — 2001
Tianjin University 1993 — 1996
master, mechnical
Tianjin University 1989 — 1996
bachelor, mechnical
Tianjin University 1989 — 1993
bachelor, mechnical
Yong Fu's Cadence Design Systems Experience November 2013 - August 2015
Job Sr. Director CAE at Synopsys Inc
Industry Electrical/Electronic Manufacturing
Experience
Synopsys Inc September 2015 - Present
ChineseTomatoes.com January 2012 - Present
Cadence Design Systems November 2013 - August 2015
Cadence Design Systems 2005 - August 2013
Cadence Design Systems 2011 - 2011
Verisity 2004 - 2005
Axis Systems 2003 - 2004
Quickturn Design Systems 1998 - 2000
Samsung Electronics October 1994 - October 1997
Skills
SoC, ASIC, Hardware, Semiconductors
Education
Tsinghua University 1986 — 1994
MS, EE
Synopsys Inc September 2015 - Present
ChineseTomatoes.com January 2012 - Present
Cadence Design Systems November 2013 - August 2015
Cadence Design Systems 2005 - August 2013
Cadence Design Systems 2011 - 2011
Verisity 2004 - 2005
Axis Systems 2003 - 2004
Quickturn Design Systems 1998 - 2000
Samsung Electronics October 1994 - October 1997
Skills
SoC, ASIC, Hardware, Semiconductors
Education
Tsinghua University 1986 — 1994
MS, EE
David (Shih-Sheng) Li's Cadence Design Systems Experience January 2013 - Present
Job Sales Technical Leader AE at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems January 2013 - Present
Intel June 1997 - November 2012
Intel Corporation June 1996 - August 1996
Skills
Formal Verification, Logic Verification, DFT, Functional Verification, Perl, Debugging, EDA, Intel, Processors, Hardware, TCL, VLSI, Static Timing Analysis, ASIC, SoC, Logic Design, SystemVerilog, Cadence, RTL design, Verilog, Low-power Design, Physical Design, Semiconductors, IC, Timing Closure, Silicon, Mixed Signal, Logic Synthesis, Integrated Circuit..., CMOS, Computer Architecture, Circuit Design, Microprocessors, RTL Design
Education
State University of New York at Buffalo
Master's degree, Electrical and Computer Engineering
National Cheng Kung University, Taiwan
Bachelor's degree, Physics
Cadence Design Systems January 2013 - Present
Intel June 1997 - November 2012
Intel Corporation June 1996 - August 1996
Skills
Formal Verification, Logic Verification, DFT, Functional Verification, Perl, Debugging, EDA, Intel, Processors, Hardware, TCL, VLSI, Static Timing Analysis, ASIC, SoC, Logic Design, SystemVerilog, Cadence, RTL design, Verilog, Low-power Design, Physical Design, Semiconductors, IC, Timing Closure, Silicon, Mixed Signal, Logic Synthesis, Integrated Circuit..., CMOS, Computer Architecture, Circuit Design, Microprocessors, RTL Design
Education
State University of New York at Buffalo
Master's degree, Electrical and Computer Engineering
National Cheng Kung University, Taiwan
Bachelor's degree, Physics
Jack Guedj's Cadence Design Systems Experience May 2013 - Present
Job Corp VP Cadence/ CEO Tensilica, Band of Angels & Sand Hill Angels Member
Industry Semiconductors
Experience
Sand Hill Angels June 2014 - Present
Band of Angels April 2014 - Present
Cadence Design Systems May 2013 - Present
Tensilica June 2008 - May 2013
Magnum Semiconductor June 2008 - November 2012
Magnum Semiconductor March 2003 - June 2008
Skills
Executive Management, Applications Software, Semiconductors, Digital Signal..., Embedded Systems, EDA, SoC, Wireless, Analog, Microprocessors, Start-ups, Product Marketing, Strategic Partnerships, Product Management, Mobile Devices, Cloud Data Analytics..., Internet of Things (IoT), Software Defined..., Intellectual Property, Mergers & Acquisitions, Turn Around Management, Strategic Planning, Business Development
Education
UCLA Anderson School of Management 1984 — 1986
Master of Business Administration (M.B.A.)
University of Paris 1982 — 1983
D.E.A (doctorate cycle), Electrical, Electronics and Communications Engineering
Graduate School of "Physique et Chimie de Paris" 1979 — 1982
Master's Degree, Physics, Chemistry and Electronics
Sand Hill Angels June 2014 - Present
Band of Angels April 2014 - Present
Cadence Design Systems May 2013 - Present
Tensilica June 2008 - May 2013
Magnum Semiconductor June 2008 - November 2012
Magnum Semiconductor March 2003 - June 2008
Skills
Executive Management, Applications Software, Semiconductors, Digital Signal..., Embedded Systems, EDA, SoC, Wireless, Analog, Microprocessors, Start-ups, Product Marketing, Strategic Partnerships, Product Management, Mobile Devices, Cloud Data Analytics..., Internet of Things (IoT), Software Defined..., Intellectual Property, Mergers & Acquisitions, Turn Around Management, Strategic Planning, Business Development
Education
UCLA Anderson School of Management 1984 — 1986
Master of Business Administration (M.B.A.)
University of Paris 1982 — 1983
D.E.A (doctorate cycle), Electrical, Electronics and Communications Engineering
Graduate School of "Physique et Chimie de Paris" 1979 — 1982
Master's Degree, Physics, Chemistry and Electronics
Quentin Chen's Cadence Design Systems Experience 2002 - 2007
Job R&D at Cadence
Industry Semiconductors
Experience
Synopsys 2007 - 2011
Cadence Design Systems 2002 - 2007
Simplex Solutions Inc. April 1999 - May 2002
Coventor 1997 - 1999
Brown Applied Technology April 1995 - April 1997
Skills
EDA, ASIC, SoC, TCL, Semiconductors, IC, VLSI, Static Timing Analysis, Physical Design, Debugging, Perl, Mixed Signal, Simulations, Algorithms, CMOS, Integrated Circuit..., Analog, Physical Verification, Low-power Design, Cadence Virtuoso, Signal Integrity, C, Timing Closure, Analog Circuit Design, C, Hardware Architecture, Digital Signal..., Software Engineering, ARM, Embedded Software, Processors, Circuit Design, Linux, Electronics, Microprocessors, Computer Architecture, SPICE, PCB design, Cadence, Unix
Education
Tianjin University
University of Toronto
Synopsys 2007 - 2011
Cadence Design Systems 2002 - 2007
Simplex Solutions Inc. April 1999 - May 2002
Coventor 1997 - 1999
Brown Applied Technology April 1995 - April 1997
Skills
EDA, ASIC, SoC, TCL, Semiconductors, IC, VLSI, Static Timing Analysis, Physical Design, Debugging, Perl, Mixed Signal, Simulations, Algorithms, CMOS, Integrated Circuit..., Analog, Physical Verification, Low-power Design, Cadence Virtuoso, Signal Integrity, C, Timing Closure, Analog Circuit Design, C, Hardware Architecture, Digital Signal..., Software Engineering, ARM, Embedded Software, Processors, Circuit Design, Linux, Electronics, Microprocessors, Computer Architecture, SPICE, PCB design, Cadence, Unix
Education
Tianjin University
University of Toronto
Ron Pyke's Cadence Design Systems Experience November 2002 - Present
Job Member of Consulting Staff at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems November 2002 - Present
Western Wireless 2001 - 2002
Motorola 2000 - 2001
The Boeing Company 1987 - 2000
Seattle Silicon January 1984 - June 1987
Skills
Perl, EDA, Unix, Software Engineering, Software Development, Shell Scripting, Object Oriented Design, C++, Linux, TCL, Agile Methodologies, Integration, Java, C, Configuration Management, Microsoft Visual Studio...
Education
University of Arizona 1982 — 1983
MS, Computer Science
University of Washington 1978 — 1982
BS, Mathematics
Cadence Design Systems November 2002 - Present
Western Wireless 2001 - 2002
Motorola 2000 - 2001
The Boeing Company 1987 - 2000
Seattle Silicon January 1984 - June 1987
Skills
Perl, EDA, Unix, Software Engineering, Software Development, Shell Scripting, Object Oriented Design, C++, Linux, TCL, Agile Methodologies, Integration, Java, C, Configuration Management, Microsoft Visual Studio...
Education
University of Arizona 1982 — 1983
MS, Computer Science
University of Washington 1978 — 1982
BS, Mathematics
Anwei Liu's Cadence Design Systems Experience Enignerring DirectorCadence2003 - Present
Job Director at Cadence Design Systems
Industry Electrical/Electronic Manufacturing
Experience
Cadence Design Systems Enignerring DirectorCadence2003 - Present
Silvaco 1994 - 1999
Education
University of Alberta 1991 — 1994
Cadence Design Systems Enignerring DirectorCadence2003 - Present
Silvaco 1994 - 1999
Education
University of Alberta 1991 — 1994
Jelena Radumilo-Franklin's Cadence Design Systems Experience January 2003 - Present
Job Member of Consulting Staff at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems January 2003 - Present
Kokusai Semiconductor Equipment Corporation 2000 - 2002
Skills
C++, Visual C++, ClearCase, Software Engineering, Software Development, Algorithms, Software Design, Object Oriented Design, Design Patterns, OOP, Unix, Windows, STL, Programming, Agile Methodologies, EDA, TCL, Perl, Multithreading, CVS, C, Debugging, Linux
Education
University of Massachusetts Lowell 2002 — 2005
MS, Computer Engineering
University of Belgrade 1992 — 1998
Cadence Design Systems January 2003 - Present
Kokusai Semiconductor Equipment Corporation 2000 - 2002
Skills
C++, Visual C++, ClearCase, Software Engineering, Software Development, Algorithms, Software Design, Object Oriented Design, Design Patterns, OOP, Unix, Windows, STL, Programming, Agile Methodologies, EDA, TCL, Perl, Multithreading, CVS, C, Debugging, Linux
Education
University of Massachusetts Lowell 2002 — 2005
MS, Computer Engineering
University of Belgrade 1992 — 1998
Abby Zhang's Cadence Design Systems Experience 1996 - 1998
Job Intellectual Property Sales and Licensing at HP
Industry Information Technology and Services
Experience
HP January 2011 - Present
Arteris, Inc. 2009 - 2010
ARM 2002 - 2009
Cadence Design Systems 1996 - 1998
Fujitsu Microelectronics Inc 1994 - 1996
Skills
- Intellectual Property..., - Major Account Sales, Strategic Partnerships, - New Markets..., Licensing, Intellectual Property, Patents, Processors, IP, Embedded Systems, Start-ups, Mobile Devices, Integrated Circuit..., Semiconductors, ASIC, Go-to-market Strategy, IC, SoC, Product Management
Education
Tsinghua University
BSEE
University of Nevada-Reno
MSEE
HP January 2011 - Present
Arteris, Inc. 2009 - 2010
ARM 2002 - 2009
Cadence Design Systems 1996 - 1998
Fujitsu Microelectronics Inc 1994 - 1996
Skills
- Intellectual Property..., - Major Account Sales, Strategic Partnerships, - New Markets..., Licensing, Intellectual Property, Patents, Processors, IP, Embedded Systems, Start-ups, Mobile Devices, Integrated Circuit..., Semiconductors, ASIC, Go-to-market Strategy, IC, SoC, Product Management
Education
Tsinghua University
BSEE
University of Nevada-Reno
MSEE
Zhichun(Larry) Wang's Cadence Design Systems Experience July 2014 - June 2015
Job Software Engineer at Uber
Industry Computer Software
Experience
Uber June 2015 - Present
Cadence Design Systems July 2014 - June 2015
Cadence Design Systems July 2010 - July 2014
Cadence Design Systems July 2008 - July 2010
University of Minnesota September 2006 - June 2008
Skills
EDA, Simulation, Circuit Simulation, Mixed Signal, Analog, VLSI, Verilog, Algorithms, IC, Perl, C++, C, Simulations, ASIC, TCL, Python, Matlab, Linux, Software Engineering, Semiconductors, Machine Learning
Education
University of Minnesota 2006 — 2008
Master of Science, Electrical and Electronics Engineering
Tsinghua University 2002 — 2006
BE, Electrical Engineering
Shanghai Gezhi High School 1999 — 2002
Uber June 2015 - Present
Cadence Design Systems July 2014 - June 2015
Cadence Design Systems July 2010 - July 2014
Cadence Design Systems July 2008 - July 2010
University of Minnesota September 2006 - June 2008
Skills
EDA, Simulation, Circuit Simulation, Mixed Signal, Analog, VLSI, Verilog, Algorithms, IC, Perl, C++, C, Simulations, ASIC, TCL, Python, Matlab, Linux, Software Engineering, Semiconductors, Machine Learning
Education
University of Minnesota 2006 — 2008
Master of Science, Electrical and Electronics Engineering
Tsinghua University 2002 — 2006
BE, Electrical Engineering
Shanghai Gezhi High School 1999 — 2002
Jinsong Zhao's Cadence Design Systems Experience January 1998 - August 2002
Job President at Lorentz Solution, Inc
Industry Semiconductors
Experience
Lorentz Solution, Inc January 2003 - Present
Cadence Design Systems January 1998 - August 2002
Education
University of California, Berkeley 2000 — 2002
Master of Business Administration (MBA)
University of California, Santa Cruz 1995 — 1997
PhD, Computer Engineering
Tsinghua University 1987 — 1995
BS/MS, Electrical Engineering
Lorentz Solution, Inc January 2003 - Present
Cadence Design Systems January 1998 - August 2002
Education
University of California, Berkeley 2000 — 2002
Master of Business Administration (MBA)
University of California, Santa Cruz 1995 — 1997
PhD, Computer Engineering
Tsinghua University 1987 — 1995
BS/MS, Electrical Engineering
Oriol Roig's Cadence Design Systems Experience October 2001 - Present
Job Sr. R&D Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems October 2001 - Present
Theseus Logic Inc. July 1999 - October 2001
National Semiconductor May 1998 - July 1999
Universitat Politècnica de Catalunya September 1995 - April 1998
Skills
C++, Software Development, Algorithms, ASIC, EDA, Debugging
Education
Universitat Politècnica de Catalunya 1993 — 1997
PhD, Computer Science
Universitat Politècnica de Catalunya 1986 — 1991
Computer Science
Cadence Design Systems October 2001 - Present
Theseus Logic Inc. July 1999 - October 2001
National Semiconductor May 1998 - July 1999
Universitat Politècnica de Catalunya September 1995 - April 1998
Skills
C++, Software Development, Algorithms, ASIC, EDA, Debugging
Education
Universitat Politècnica de Catalunya 1993 — 1997
PhD, Computer Science
Universitat Politècnica de Catalunya 1986 — 1991
Computer Science
Jon Houghten's Cadence Design Systems Experience 1998 - 2000
Job Principal Owner at JLH Enterprises
Industry Leisure, Travel & Tourism
Experience
JLH Enterprises April 2014 - Present
ARM March 2000 - March 2014
Cadence Design Systems 1998 - 2000
Cascade Design Automation 1995 - 1998
Motorola 1988 - 1995
Skills
ARM, Semiconductors, IC, Hardware Design, SoC, ASIC, EDA, Processors, Mixed Signal, Microprocessors, Analog, RTL design, Verilog, FPGA, Semiconductor Industry, Integrated Circuit...
Education
University of Arizona 1984 — 1989
MSEE, Semiconductors
JLH Enterprises April 2014 - Present
ARM March 2000 - March 2014
Cadence Design Systems 1998 - 2000
Cascade Design Automation 1995 - 1998
Motorola 1988 - 1995
Skills
ARM, Semiconductors, IC, Hardware Design, SoC, ASIC, EDA, Processors, Mixed Signal, Microprocessors, Analog, RTL design, Verilog, FPGA, Semiconductor Industry, Integrated Circuit...
Education
University of Arizona 1984 — 1989
MSEE, Semiconductors
Lynn Cai's Cadence Design Systems Experience June 2004 - September 2006
Job Sr. Engineering Manager at Mentor Graphics
Industry Semiconductors
Experience
Mentor Graphics August 2012 - Present
Brion Technologies September 2006 - August 2012
Cadence Design Systems June 2004 - September 2006
Synopsys Inc 1999 - 2004
Numerical Technologies 1999 - 2003
Skills
EDA
Education
University of Windsor 1991 — 1995
Doctor of Philosophy (Ph.D.), Artificial Intelligence
Tsinghua University
Mentor Graphics August 2012 - Present
Brion Technologies September 2006 - August 2012
Cadence Design Systems June 2004 - September 2006
Synopsys Inc 1999 - 2004
Numerical Technologies 1999 - 2003
Skills
EDA
Education
University of Windsor 1991 — 1995
Doctor of Philosophy (Ph.D.), Artificial Intelligence
Tsinghua University
Lingting Ye's Cadence Design Systems Experience 2000 - 2004
Job Principal Design Engineer at IDT
Industry Semiconductors
Experience
IDT November 2011 - Present
Maxim Integrated Products March 2005 - December 2011
Cadence Design Systems 2000 - 2004
Atmel Corporation 1999 - 2000
Education
University of Maryland College Park 1997 — 1999
MS, Microelectronics
Tsinghua University 1988 — 1993
B.S., Material Science and Engineering
IDT November 2011 - Present
Maxim Integrated Products March 2005 - December 2011
Cadence Design Systems 2000 - 2004
Atmel Corporation 1999 - 2000
Education
University of Maryland College Park 1997 — 1999
MS, Microelectronics
Tsinghua University 1988 — 1993
B.S., Material Science and Engineering
Wanling Wen's Cadence Design Systems Experience August 2004 - October 2011
Job R&D Engineer at Synopsys
Industry Computer Software
Experience
Synopsys November 2012 - Present
AMD October 2011 - November 2012
Cadence Design Systems August 2004 - October 2011
Synopsys Inc. Mountain View, CA June 2002 - August 2004
Avanti Corporation, Fremont CA May 2000 - June 2002
The Lawrence Berkeley National Laboratory, Berkeley, CA August 1998 - December 1999
Skills
EDA, Algorithms, Low Power Design, Physical Design, RTL, Computing Architectures, c/c++, Tcl/TK, Perl, Python, VLSI, MIPS, ASIC, TCL, Low-power Design, Semiconductors, Signal Integrity, IC, Semiconductor Industry, SoC, Place & Route, Timing, RTL design, Verilog, Timing Closure, Static Timing Analysis, RTL Design, C++
Education
University of California, Berkeley 1997 — 2000
EECS
Synopsys November 2012 - Present
AMD October 2011 - November 2012
Cadence Design Systems August 2004 - October 2011
Synopsys Inc. Mountain View, CA June 2002 - August 2004
Avanti Corporation, Fremont CA May 2000 - June 2002
The Lawrence Berkeley National Laboratory, Berkeley, CA August 1998 - December 1999
Skills
EDA, Algorithms, Low Power Design, Physical Design, RTL, Computing Architectures, c/c++, Tcl/TK, Perl, Python, VLSI, MIPS, ASIC, TCL, Low-power Design, Semiconductors, Signal Integrity, IC, Semiconductor Industry, SoC, Place & Route, Timing, RTL design, Verilog, Timing Closure, Static Timing Analysis, RTL Design, C++
Education
University of California, Berkeley 1997 — 2000
EECS
Tom Marcacci's Cadence Design Systems Experience 2000 - 2007
Job Computer Software Professional
Industry Computer Software
Experience
Cadence Design Systems 2000 - 2007
Education
University of California, Davis 1972 — 1977
MA, Philosophy
San Jose State University
MBA, Business
University of California, Berkeley
BA, Philosophy, Economics
Cadence Design Systems 2000 - 2007
Education
University of California, Davis 1972 — 1977
MA, Philosophy
San Jose State University
MBA, Business
University of California, Berkeley
BA, Philosophy, Economics
Xianwen (Wayne) Fang's Cadence Design Systems Experience 2000 - 2005
Job Senior Staff VLSI Engineer at ClariPhy Communications
Industry Computer Networking
Experience
ClariPhy Communications May 2010 - Present
QLogic 2009 - 2010
Fulcrum Microsystems September 2005 - December 2008
Cadence Design Systems 2000 - 2005
JTA Research September 2000 - March 2002
Skills
I2C, DFT, ASIC, USB, SPI, AMBA, Analog, CMOS, Digital Signal..., Embedded Systems, FPGA, Integrated Circuit..., Mixed Signal, Semiconductors, Simulations, SoC, Timing Closure, VLSI
Education
University of California, Los Angeles 1997 — 2004
PhD, MS, Electrical Engineering
Tsinghua University 1993 — 1996
ME
ClariPhy Communications May 2010 - Present
QLogic 2009 - 2010
Fulcrum Microsystems September 2005 - December 2008
Cadence Design Systems 2000 - 2005
JTA Research September 2000 - March 2002
Skills
I2C, DFT, ASIC, USB, SPI, AMBA, Analog, CMOS, Digital Signal..., Embedded Systems, FPGA, Integrated Circuit..., Mixed Signal, Semiconductors, Simulations, SoC, Timing Closure, VLSI
Education
University of California, Los Angeles 1997 — 2004
PhD, MS, Electrical Engineering
Tsinghua University 1993 — 1996
ME
Maggie Kang's Cadence Design Systems Experience January 1998 - January 2002
Job Sr. CAD Engineer
Industry Semiconductors
Experience
Nvidia Corp January 2008 - Present
Synopsys, Inc 2002 - 2008
Cadence Design Systems January 1998 - January 2002
Education
University of California, Santa Cruz 1995 — 1998
PhD
Tsinghua University
M.S
Tsinghua University
B.S
Nvidia Corp January 2008 - Present
Synopsys, Inc 2002 - 2008
Cadence Design Systems January 1998 - January 2002
Education
University of California, Santa Cruz 1995 — 1998
PhD
Tsinghua University
M.S
Tsinghua University
B.S
Bo Wu's Cadence Design Systems Experience March 2004 - April 2005
Job Staff Device Modeling Engineer at Micron
Industry Electrical/Electronic Manufacturing
Experience
Micron Technology March 2012 - Present
Synopsys April 2005 - March 2012
Cadence Design Systems March 2004 - April 2005
Skills
EDA, TCAD, Sentaurus TCAD, CMOS, Process Technology, Device Modeling, Raphael, BSIMPro+, HSPICE, GaN or GaAs based HFETs, Tcl, C/C++, SPICE, TCL, Characterization, Silicon
Education
University of Massachusetts, Amherst
Doctor of Philosophy (PhD), Electrical Engineering
Tsinghua University
Master's degree, Microelectroncs
Zhejiang University
Bachelor of Engineering (BE), Electrical and Electronics Engineering
Micron Technology March 2012 - Present
Synopsys April 2005 - March 2012
Cadence Design Systems March 2004 - April 2005
Skills
EDA, TCAD, Sentaurus TCAD, CMOS, Process Technology, Device Modeling, Raphael, BSIMPro+, HSPICE, GaN or GaAs based HFETs, Tcl, C/C++, SPICE, TCL, Characterization, Silicon
Education
University of Massachusetts, Amherst
Doctor of Philosophy (PhD), Electrical Engineering
Tsinghua University
Master's degree, Microelectroncs
Zhejiang University
Bachelor of Engineering (BE), Electrical and Electronics Engineering
David Sternitzke's Cadence Design Systems Experience February 2001 - October 2001
Job Senior Mask Designer
Industry Semiconductors
Experience
LSI-Contract January 2011 - Present
Broadcom November 2007 - July 2009
Toshiba Corporation May 2007 - November 2007
Qualcomm October 2006 - May 2007
Freescale April 2006 - September 2006
Rambus January 2006 - July 2006
IBM July 2005 - December 2005
Intel February 2001 - October 2004
Cadence Design Systems February 2001 - October 2001
Agilent Corporation September 2000 - January 2001
Education
University of California, San Diego 1976 — 1978
B.A, Poli Sci
University of California, Berkeley
Degree
LSI-Contract January 2011 - Present
Broadcom November 2007 - July 2009
Toshiba Corporation May 2007 - November 2007
Qualcomm October 2006 - May 2007
Freescale April 2006 - September 2006
Rambus January 2006 - July 2006
IBM July 2005 - December 2005
Intel February 2001 - October 2004
Cadence Design Systems February 2001 - October 2001
Agilent Corporation September 2000 - January 2001
Education
University of California, San Diego 1976 — 1978
B.A, Poli Sci
University of California, Berkeley
Degree
Bruce Luttrell's Cadence Design Systems Experience January 2006 - June 2009
Job Computer Software Professional focussing on: C, C++, AWK, Perl, UNIX CShell on UNIX and/or Windows platform
Industry Computer Software
Experience
Silver Creek High School 2011 - 2011
Cadence Design Systems January 2006 - June 2009
Synopsys August 2003 - December 2006
Education
University of California, Berkeley
MS, Electrical Engineering and Computer Sciences
Silver Creek High School 2011 - 2011
Cadence Design Systems January 2006 - June 2009
Synopsys August 2003 - December 2006
Education
University of California, Berkeley
MS, Electrical Engineering and Computer Sciences
Chao Jiao's Cadence Design Systems Experience October 2013 - November 2013
Job Lead Sofeware Developer
Industry Computer Software
Experience
ANSYS, Inc. December 2013 - Present
Cadence Design Systems October 2013 - November 2013
Cadence Design Systems July 2011 - September 2013
Cadence Design Systems September 2008 - July 2011
Skills
Software Development, Software Project..., C++, C, HTML, PHP, JavaScript
Education
Tsinghua University 2003 — 2009
Ph.D, Electronic Science and Technology
Tsinghua University 1999 — 2003
Bachelor's degree, Electrical and Electronics Engineering
ANSYS, Inc. December 2013 - Present
Cadence Design Systems October 2013 - November 2013
Cadence Design Systems July 2011 - September 2013
Cadence Design Systems September 2008 - July 2011
Skills
Software Development, Software Project..., C++, C, HTML, PHP, JavaScript
Education
Tsinghua University 2003 — 2009
Ph.D, Electronic Science and Technology
Tsinghua University 1999 — 2003
Bachelor's degree, Electrical and Electronics Engineering
Hongjing Zou's Cadence Design Systems Experience August 2002 - June 2009
Job Computer Software Professional
Industry Financial Services
Experience
Investment Technology Group, Inc. October 2010 - January 2013
Majestic Research November 2009 - October 2010
Cadence Design Systems August 2002 - June 2009
Skills
C++, Perl, SQL, Algorithms, Software Development, C, Databases, Product Management, Simulations, Unix, MySQL, ClearCase, Project Management
Education
University of California, Berkeley 2000 — 2002
MS, Electrical and Computer Engineering
Tsinghua University 1995 — 2000
BS, Electronic Engineering
Investment Technology Group, Inc. October 2010 - January 2013
Majestic Research November 2009 - October 2010
Cadence Design Systems August 2002 - June 2009
Skills
C++, Perl, SQL, Algorithms, Software Development, C, Databases, Product Management, Simulations, Unix, MySQL, ClearCase, Project Management
Education
University of California, Berkeley 2000 — 2002
MS, Electrical and Computer Engineering
Tsinghua University 1995 — 2000
BS, Electronic Engineering
Jenny Pettengill's Cadence Design Systems Experience 1996 - 2002
Job
Industry Electrical/Electronic Manufacturing
Experience
Metprom 2004 - 2015
Metprom 2004 - 2015
Metprom 2004 - 2015
Cadence Design Systems 1996 - 2002
Education
University of California, Berkeley
BS, Electrical Engineering and Computer Science
Metprom 2004 - 2015
Metprom 2004 - 2015
Metprom 2004 - 2015
Cadence Design Systems 1996 - 2002
Education
University of California, Berkeley
BS, Electrical Engineering and Computer Science
Tiejun Yu's Cadence Design Systems Experience July 2012 - Present
Job Architect at Cadence Design System
Industry Computer Software
Experience
Cadence Design Systems July 2012 - Present
Sigrity May 2003 - July 2012
Cadence Design Systems October 2000 - May 2003
ECE Dept., Duke University December 1998 - October 2000
Department of Mathematics, UNC Charlotte January 1997 - December 1998
Skills
EDA, Simulations, C++, IC, Embedded Systems, Semiconductors, C, Matlab, SoC, Algorithms, TCL, Perl, PCB design, Fortran, RF, Signal Integrity, Numerical Analysis, Analog, Mixed Signal, High Performance..., Power Integrity (PI)..., VLSI, Signal Processing, Digital Signal..., SPICE, ASIC
Education
Tsinghua University 1990 — 1996
Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering
Cadence Design Systems July 2012 - Present
Sigrity May 2003 - July 2012
Cadence Design Systems October 2000 - May 2003
ECE Dept., Duke University December 1998 - October 2000
Department of Mathematics, UNC Charlotte January 1997 - December 1998
Skills
EDA, Simulations, C++, IC, Embedded Systems, Semiconductors, C, Matlab, SoC, Algorithms, TCL, Perl, PCB design, Fortran, RF, Signal Integrity, Numerical Analysis, Analog, Mixed Signal, High Performance..., Power Integrity (PI)..., VLSI, Signal Processing, Digital Signal..., SPICE, ASIC
Education
Tsinghua University 1990 — 1996
Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering
Ganping Sun's Cadence Design Systems Experience July 2013 - Present
Job Sr. Architect at Cadence Design Systems
Industry Computer Software
Adrian Leuciuc's Cadence Design Systems Experience September 2004 - Present
Job Staff Design Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems September 2004 - Present
Stony Brook University February 1998 - August 2004
Technical University of Iasi February 1991 - February 1998
Skills
Analog Circuit Design, Mixed Signal IC Design, Nonlinear Circuits, Mixed Signal, Circuits, Analog, Signal Processing, EDA, PCB design, RF, CMOS, IC, ASIC, Circuit Design, SERDES, Device Drivers, Matlab, Verilog-A, SoC, Integrated Circuit..., Cadence Virtuoso, Low-power Design, Algorithms, ModelSim, Signal Integrity, Simulations
Education
Universitatea Tehnică „Gh. Asachi” din Iași 1993 — 1996
PhD, Electrical Engineering
1985 — 1990
Dipl.Eng., Electrical Engineering
Cadence Design Systems September 2004 - Present
Stony Brook University February 1998 - August 2004
Technical University of Iasi February 1991 - February 1998
Skills
Analog Circuit Design, Mixed Signal IC Design, Nonlinear Circuits, Mixed Signal, Circuits, Analog, Signal Processing, EDA, PCB design, RF, CMOS, IC, ASIC, Circuit Design, SERDES, Device Drivers, Matlab, Verilog-A, SoC, Integrated Circuit..., Cadence Virtuoso, Low-power Design, Algorithms, ModelSim, Signal Integrity, Simulations
Education
Universitatea Tehnică „Gh. Asachi” din Iași 1993 — 1996
PhD, Electrical Engineering
1985 — 1990
Dipl.Eng., Electrical Engineering
Rick Pederson's Cadence Design Systems Experience 1985 - 1991
Job Director, Sales and Marketing at CP Medical
Industry Medical Devices
Experience
CP Medical January 2009 - Present
Scanis 2000 - 2005
Epic Design Technology 1992 - 1999
Synopsys 1991 - 1999
Cadence Design Systems 1985 - 1991
Education
University of California, Berkeley 1974 — 1976
BA, Liberal Arts
University of California, Berkeley 1974 — 1976
sociology
University of California, Berkeley 1972 — 1976
CP Medical January 2009 - Present
Scanis 2000 - 2005
Epic Design Technology 1992 - 1999
Synopsys 1991 - 1999
Cadence Design Systems 1985 - 1991
Education
University of California, Berkeley 1974 — 1976
BA, Liberal Arts
University of California, Berkeley 1974 — 1976
sociology
University of California, Berkeley 1972 — 1976
Harry Hung Truong's Cadence Design Systems Experience June 2002 - March 2011
Job Staff Physical Design Engineer
Industry Computer Hardware
Experience
Marvell Semiconductor March 2011 - Present
Cadence Design Systems June 2002 - March 2011
Simplex Solutions, Inc. 2000 - 2002
Cirrus Logic 1997 - 2000
Hal Computer Systems 1996 - 1997
Skills
ASIC, SoC, Physical Design, Timing Closure, Functional Verification, IC, Semiconductors, Verilog, Circuit Design, Debugging, ICC and EDI
Education
University of California, Berkeley 1993 — 1996
BS
Marvell Semiconductor March 2011 - Present
Cadence Design Systems June 2002 - March 2011
Simplex Solutions, Inc. 2000 - 2002
Cirrus Logic 1997 - 2000
Hal Computer Systems 1996 - 1997
Skills
ASIC, SoC, Physical Design, Timing Closure, Functional Verification, IC, Semiconductors, Verilog, Circuit Design, Debugging, ICC and EDI
Education
University of California, Berkeley 1993 — 1996
BS
Victor Markus Purri's Cadence Design Systems Experience June 2014 - Present
Job Formal Verification Expert
Industry Semiconductors
Experience
Cadence Design Systems June 2014 - Present
Jasper Design Automation April 2012 - June 2014
Jasper Design Automation November 2008 - April 2012
Consultoria e Projetos Elétricos Júnior April 2006 - September 2008
Skills
C, Python, Hardware, XML, Software Development, Testing, Bash, Debugging, PHP, TCL, SQL, Formal Verification, C++, Linux, Verilog
Education
Universidade Federal de Minas Gerais 2005 — 2010
BEE, Electrical Engineering
Cadence Design Systems June 2014 - Present
Jasper Design Automation April 2012 - June 2014
Jasper Design Automation November 2008 - April 2012
Consultoria e Projetos Elétricos Júnior April 2006 - September 2008
Skills
C, Python, Hardware, XML, Software Development, Testing, Bash, Debugging, PHP, TCL, SQL, Formal Verification, C++, Linux, Verilog
Education
Universidade Federal de Minas Gerais 2005 — 2010
BEE, Electrical Engineering
saurabh kakkar's Cadence Design Systems Experience February 2015 - Present
Job Senior Application Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems February 2015 - Present
University at Buffalo January 2013 - June 2014
CoreEL Technologies July 2011 - July 2012
Bharti Airtel Limited June 2009 - July 2011
Skills
Verilog, VHDL, ModelSim, FPGA, Xilinx ISE, VLSI, Cadence Spectre, ASIC, DFT, Logic Synthesis, Unix Shell Scripting, Cadence Virtuoso, Xilinx, Integrated Circuit..., Analog, RTL Design, Static Timing Analysis, Cadence Virtuoso Layout..., Tanner EDA, IC Station, Eldo, Calibre, RTL compiler, Cadence Encounter, Spectre, Perl
Education
State University of New York at Buffalo 2013 — 2014
Master of Science (MS), electrical engineering, 3.46/4.0
BSA Institute of Technology and Mgmt, Maharshi Dayanand University, Rohtak 2004 — 2008
Bachelors of Engineering, Electronics and Communications Engineering, 65.2%
Cadence Design Systems February 2015 - Present
University at Buffalo January 2013 - June 2014
CoreEL Technologies July 2011 - July 2012
Bharti Airtel Limited June 2009 - July 2011
Skills
Verilog, VHDL, ModelSim, FPGA, Xilinx ISE, VLSI, Cadence Spectre, ASIC, DFT, Logic Synthesis, Unix Shell Scripting, Cadence Virtuoso, Xilinx, Integrated Circuit..., Analog, RTL Design, Static Timing Analysis, Cadence Virtuoso Layout..., Tanner EDA, IC Station, Eldo, Calibre, RTL compiler, Cadence Encounter, Spectre, Perl
Education
State University of New York at Buffalo 2013 — 2014
Master of Science (MS), electrical engineering, 3.46/4.0
BSA Institute of Technology and Mgmt, Maharshi Dayanand University, Rohtak 2004 — 2008
Bachelors of Engineering, Electronics and Communications Engineering, 65.2%
Xun Tang's Cadence Design Systems Experience November 2010 - August 2013
Job Senior R&D Engineer at Synopsys
Industry Computer Software
Experience
Cadence Design Systems November 2010 - August 2013
Mentor Graphics January 2008 - September 2010
Dept. of ECE, University of Iowa January 2007 - September 2010
Mentor Graphics May 2007 - August 2007
University of Iowa October 2005 - October 2006
Tsinghua University March 2004 - May 2005
Skills
Circuit Simulators, C, C++, Verification, Data Structures, Algorithms, Linux, Verilog, Perl, DFT, Low-power Design, FPGA, Embedded Systems
Education
University of Iowa 2005 — 2010
Ph.D, Electrical and Computer Engineering, DFT (Design-for-Test), Circuit Diagnosis/Debug
Tsinghua University 2000 — 2004
BE, Engineering Physics
Cadence Design Systems November 2010 - August 2013
Mentor Graphics January 2008 - September 2010
Dept. of ECE, University of Iowa January 2007 - September 2010
Mentor Graphics May 2007 - August 2007
University of Iowa October 2005 - October 2006
Tsinghua University March 2004 - May 2005
Skills
Circuit Simulators, C, C++, Verification, Data Structures, Algorithms, Linux, Verilog, Perl, DFT, Low-power Design, FPGA, Embedded Systems
Education
University of Iowa 2005 — 2010
Ph.D, Electrical and Computer Engineering, DFT (Design-for-Test), Circuit Diagnosis/Debug
Tsinghua University 2000 — 2004
BE, Engineering Physics
Dongmin Xu's Cadence Design Systems Experience June 2001 - Present
Job Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems June 2001 - Present
Skills
EDA
Education
Tsinghua University 1986 — 1991
Ph.D., Electrical Engineering
Cadence Design Systems June 2001 - Present
Skills
EDA
Education
Tsinghua University 1986 — 1991
Ph.D., Electrical Engineering
Radu Zlatanovici's Cadence Design Systems Experience September 2006 - May 2011
Job Component Design Engineer at Intel Corporation
Industry Computer Hardware
Experience
Intel Corporation May 2011 - Present
Cadence Design Systems September 2006 - May 2011
University of California, Berkeley January 2001 - September 2006
IBM May 2003 - August 2003
IBM May 2002 - August 2002
University of California, Berkeley August 2001 - December 2001
University of California, Berkeley August 2000 - December 2000
Politehnica University of Bucharest September 1999 - August 2000
Darmstadt University of Technology July 1998 - September 1998
Darmstadt University of Technology July 1997 - September 1997
Skills
IC, Simulation, Analog Design, Mixed Signal, Digital Electronics
Education
University of California, Berkeley 2000 — 2006
PHD, Electrical Engineering and Computer Sciences
University of California, Berkeley 2000 — 2002
M.S., Electrical Engineering and Computer Sciences
1999 — 2000
M.S., Electronics
1994 — 1999
B.S., Electronics and Telecommunications
Intel Corporation May 2011 - Present
Cadence Design Systems September 2006 - May 2011
University of California, Berkeley January 2001 - September 2006
IBM May 2003 - August 2003
IBM May 2002 - August 2002
University of California, Berkeley August 2001 - December 2001
University of California, Berkeley August 2000 - December 2000
Politehnica University of Bucharest September 1999 - August 2000
Darmstadt University of Technology July 1998 - September 1998
Darmstadt University of Technology July 1997 - September 1997
Skills
IC, Simulation, Analog Design, Mixed Signal, Digital Electronics
Education
University of California, Berkeley 2000 — 2006
PHD, Electrical Engineering and Computer Sciences
University of California, Berkeley 2000 — 2002
M.S., Electrical Engineering and Computer Sciences
1999 — 2000
M.S., Electronics
1994 — 1999
B.S., Electronics and Telecommunications
Olivier Robert's Cadence Design Systems Experience March 2013 - Present
Job Senior Design Engineer at Cadence Design Systems
Industry Semiconductors
Experience
Cadence Design Systems March 2013 - Present
PMC-Sierra March 2011 - March 2013
Université du Québec à Montréal 2008 - 2011
Hydro Québec 2005 - 2007
Skills
Place & Route, Physical Verification, Parasitic Extraction, DRC, Physical Design, Clock Tree Synthesis, LVS, Floorplanning, Timing Closure, Power Analysis, Static Timing Analysis, Conformal LEC
Education
Université du Québec à Montréal 2005 — 2010
Baccalauréat (B.Ing.), Génie Microélectronique
Cadence Design Systems March 2013 - Present
PMC-Sierra March 2011 - March 2013
Université du Québec à Montréal 2008 - 2011
Hydro Québec 2005 - 2007
Skills
Place & Route, Physical Verification, Parasitic Extraction, DRC, Physical Design, Clock Tree Synthesis, LVS, Floorplanning, Timing Closure, Power Analysis, Static Timing Analysis, Conformal LEC
Education
Université du Québec à Montréal 2005 — 2010
Baccalauréat (B.Ing.), Génie Microélectronique
Yutao Ma's Cadence Design Systems Experience 2003 - 2007
Job Sr. Director at ProPlus Design Solutions, Inc.
Industry Computer Software
Experience
ProPlus Design Solutions, Inc. January 2007 - Present
Cadence Design Systems 2003 - 2007
Skills
EDA, Algorithms, Linux, Software Development, Verilog, Simulations, C, Software Engineering, Perl, C++, Matlab, Object Oriented Design, CMOS, Software Architectural..., Product Management
Education
Tsinghua University 1991 — 2001
Ph.D., MicroElectronics
ProPlus Design Solutions, Inc. January 2007 - Present
Cadence Design Systems 2003 - 2007
Skills
EDA, Algorithms, Linux, Software Development, Verilog, Simulations, C, Software Engineering, Perl, C++, Matlab, Object Oriented Design, CMOS, Software Architectural..., Product Management
Education
Tsinghua University 1991 — 2001
Ph.D., MicroElectronics
Ed Cooner's Cadence Design Systems Experience August 2000 - Present
Job Senior Principal Configuration Management Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems August 2000 - Present
IKOS Systems 1987 - 2000
Skills
Software Development, Perl, Software Engineering, Unix, Shell Scripting, CVS, Linux, ClearCase, Software Project..., Software Design, Object Oriented Design
Education
Nazarene Theological Seminary 1980 — 1983
MDiv, Theology
Trevecca Nazarene University 1973 — 1977
BS, Music Education
Fort Walton Beach High School 1969 — 1973
Cadence Design Systems August 2000 - Present
IKOS Systems 1987 - 2000
Skills
Software Development, Perl, Software Engineering, Unix, Shell Scripting, CVS, Linux, ClearCase, Software Project..., Software Design, Object Oriented Design
Education
Nazarene Theological Seminary 1980 — 1983
MDiv, Theology
Trevecca Nazarene University 1973 — 1977
BS, Music Education
Fort Walton Beach High School 1969 — 1973
Antonio Caldeira's Cadence Design Systems Experience June 2014 - February 2015
Job Verification Engineer at Apple
Industry Computer Software
Experience
Apple February 2015 - Present
Cadence Design Systems June 2014 - February 2015
Jasper Design Automation November 2010 - June 2014
Jasper Design Automation April 2008 - November 2010
Universidade Federal de Minas Gerais June 2006 - July 2008
Open Systems Engineering - OSE September 2005 - May 2006
Universidade Federal de Minas Gerais - Laboratory of Computer Engineering June 2004 - August 2005
Skills
EDA, Formal Verification, Creative Problem Solving, Team Leadership, Low-power Design, Cross-cultural..., TCL, Debugging, Verilog, Perl, Bash, Algorithms, Linux, Java, Shell Scripting, Testing, SystemVerilog, C, C++, XML, VHDL, Python, Software Development, Subversion, Eclipse, Functional Verification, Architecture, Innovation, Semiconductors, Web Development, SoC, Low Power Design
Education
Universidade Federal de Minas Gerais 2007 — 2009
Master of Science (M.Sc.), Computer Science
Universidade Federal de Minas Gerais 2003 — 2006
Bachelor of Science (B.Sc.), Computer Science
Escola Tecnica de Formacao Gerencial - SEBRAE-MG 1999 — 2002
Technician, Business Administration and Management, General
Apple February 2015 - Present
Cadence Design Systems June 2014 - February 2015
Jasper Design Automation November 2010 - June 2014
Jasper Design Automation April 2008 - November 2010
Universidade Federal de Minas Gerais June 2006 - July 2008
Open Systems Engineering - OSE September 2005 - May 2006
Universidade Federal de Minas Gerais - Laboratory of Computer Engineering June 2004 - August 2005
Skills
EDA, Formal Verification, Creative Problem Solving, Team Leadership, Low-power Design, Cross-cultural..., TCL, Debugging, Verilog, Perl, Bash, Algorithms, Linux, Java, Shell Scripting, Testing, SystemVerilog, C, C++, XML, VHDL, Python, Software Development, Subversion, Eclipse, Functional Verification, Architecture, Innovation, Semiconductors, Web Development, SoC, Low Power Design
Education
Universidade Federal de Minas Gerais 2007 — 2009
Master of Science (M.Sc.), Computer Science
Universidade Federal de Minas Gerais 2003 — 2006
Bachelor of Science (B.Sc.), Computer Science
Escola Tecnica de Formacao Gerencial - SEBRAE-MG 1999 — 2002
Technician, Business Administration and Management, General
William Haydamack's Cadence Design Systems Experience 1986 - 1993
Job Senior recruiter
Industry Individual & Family Services
Experience
Self-employed April 2013 - Present
SiSolve 2002 - 2006
Electroglas November 1997 - July 2002
Data I/O 1993 - 1997
Cadence Design Systems 1986 - 1993
Skills
Engineering, Software Project..., Vice Presidents, CEOs, Employee Benefits, Recruiting, Risk Management, Sales, Recruiters, Resume, Industrial Sector, Job Fairs, Behavioral Interviewing, Leadership, Resume Writing, College Recruiting, Interview Preparation, Corporate Recruiting
Education
University of Alberta
BSEE
University of Alberta
MSEE, Electrical and Electronics Engineering
Self-employed April 2013 - Present
SiSolve 2002 - 2006
Electroglas November 1997 - July 2002
Data I/O 1993 - 1997
Cadence Design Systems 1986 - 1993
Skills
Engineering, Software Project..., Vice Presidents, CEOs, Employee Benefits, Recruiting, Risk Management, Sales, Recruiters, Resume, Industrial Sector, Job Fairs, Behavioral Interviewing, Leadership, Resume Writing, College Recruiting, Interview Preparation, Corporate Recruiting
Education
University of Alberta
BSEE
University of Alberta
MSEE, Electrical and Electronics Engineering
Tao Li's Cadence Design Systems Experience July 2002 - November 2014
Job Senior Software Engineer, AMS verification products at Tiburon Design Automation
Industry Computer Software
Experience
Tiburon Design Automation January 2015 - Present
Cadence Design Systems July 2002 - November 2014
Skills
Mixed-Signal IC Design, Numerical Simulation, C/C++ programming, IC design, Analysis of Computer..., Verilog, VHDL,..., EDA, Integrated Circuit..., Algorithms, Debugging, C, Verilog, ASIC, Linux, Perl, Software Development, Simulations, C++
Education
Tsinghua University 1995 — 2002
Master's degree of CS Bachelor 's degree of EE, EDA, Computer software programming, IC Design
Tiburon Design Automation January 2015 - Present
Cadence Design Systems July 2002 - November 2014
Skills
Mixed-Signal IC Design, Numerical Simulation, C/C++ programming, IC design, Analysis of Computer..., Verilog, VHDL,..., EDA, Integrated Circuit..., Algorithms, Debugging, C, Verilog, ASIC, Linux, Perl, Software Development, Simulations, C++
Education
Tsinghua University 1995 — 2002
Master's degree of CS Bachelor 's degree of EE, EDA, Computer software programming, IC Design
Deyi Li's Cadence Design Systems Experience August 2015 - Present
Job Software Engineer at Cadence Design Systems
Industry Computer Software
Experience
Cadence Design Systems August 2015 - Present
Intel Corporation June 2012 - August 2012
Skills
Java, Python, C, Scheme, MIPS, Logisim, SQL, Teamwork, Public Speaking
Education
University of California, Berkeley 2013 — 2015
Bachelor of Science (B.S.), Electrical Engineering and Computer Science
Cadence Design Systems August 2015 - Present
Intel Corporation June 2012 - August 2012
Skills
Java, Python, C, Scheme, MIPS, Logisim, SQL, Teamwork, Public Speaking
Education
University of California, Berkeley 2013 — 2015
Bachelor of Science (B.S.), Electrical Engineering and Computer Science
Hewlett-Packard
SAP
Symantec
Intuit
HP
salesforce.com
Bloomberg LP
Autodesk